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Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01

FPGA:
- Enable fpga loading on Versal
- Minor fix

Microblaze:
- Fix LMB configurations to support initrds
- Some other cleanups

Zynq:
- Minor config/dt changes
- Add distro boot support for usb1 and mmc1
- Remove Xilinx private boot commands and use only distro boot

ZynqMP:
- Kconfig cleanups, defconfig updates
- Update some dt files
- Add firmware driver for talking to PMUFW
- Extend distro boot support for jtag
- Add new IDs
- Add system controller configurations
- Convert code to talk firmware via mailbox or SMCs

Versal:
- Add board_late_init()
- Add run time DT memory setup
- Add DFU support
- Extend distro boot support for jtag and dfu
- Add clock driver
- Tune mini configurations

Xilinx:
- Improve documentation (boot scripts, dt binding)
- Enable run time initrd_high calculation
- Define default SYS_PROMPT
- Add zynq/zynqmp virtual defconfig

Drivers:
- Add Xilinx mailbox driver for talking to firmware
- Clean zynq_gem for Versal
- Move ZYNQ_HISPD_BROKEN to Kconfig
- Wire genphy_init() in phy.c
- Add Xilinx gii2rgmii bridge
- Cleanup zynq_sdhci
- dwc3 fix
- zynq_gpio fix
- axi_emac fix

Others:
- apalis-tk1 - clean config file
Tom Rini 4 years ago
parent
commit
44fb0d6c9f
100 changed files with 4604 additions and 338 deletions
  1. 4 0
      MAINTAINERS
  2. 22 0
      arch/arm/Kconfig
  3. 4 0
      arch/arm/dts/Makefile
  4. 4 0
      arch/arm/dts/zynq-cse-qspi-single.dts
  5. 1 0
      arch/arm/dts/zynq-zc702.dts
  6. 282 0
      arch/arm/dts/zynqmp-a2197-g-revA.dts
  7. 461 0
      arch/arm/dts/zynqmp-a2197-m-revA.dts
  8. 567 0
      arch/arm/dts/zynqmp-a2197-p-revA.dts
  9. 89 0
      arch/arm/dts/zynqmp-a2197-revA.dts
  10. 1 0
      arch/arm/dts/zynqmp-clk.dtsi
  11. 1 1
      arch/arm/dts/zynqmp-mini-qspi.dts
  12. 39 5
      arch/arm/dts/zynqmp.dtsi
  13. 7 5
      arch/arm/mach-versal/Kconfig
  14. 60 24
      arch/arm/mach-versal/cpu.c
  15. 23 0
      arch/arm/mach-versal/include/mach/hardware.h
  16. 61 0
      arch/arm/mach-versal/include/mach/sys_proto.h
  17. 0 4
      arch/arm/mach-zynqmp/Makefile
  18. 1 23
      arch/arm/mach-zynqmp/cpu.c
  19. 5 19
      arch/arm/mach-zynqmp/include/mach/sys_proto.h
  20. 0 112
      arch/arm/mach-zynqmp/pmu_ipc.c
  21. 8 0
      arch/microblaze/Kconfig
  22. 4 0
      arch/microblaze/include/asm/config.h
  23. 88 48
      arch/microblaze/lib/bootm.c
  24. 8 0
      board/xilinx/Kconfig
  25. 10 0
      board/xilinx/bootscripts/qspiboot.cmd
  26. 10 0
      board/xilinx/bootscripts/sdboot.cmd
  27. 14 0
      board/xilinx/common/board.c
  28. 19 9
      board/xilinx/microblaze-generic/microblaze-generic.c
  29. 1 0
      board/xilinx/versal/Makefile
  30. 139 1
      board/xilinx/versal/board.c
  31. 1 1
      board/xilinx/zynq/board.c
  32. 1 0
      board/xilinx/zynqmp/cmds.c
  33. 1 0
      board/xilinx/zynqmp/zynqmp-a2197-g-revA
  34. 1 0
      board/xilinx/zynqmp/zynqmp-a2197-m-revA
  35. 1 0
      board/xilinx/zynqmp/zynqmp-a2197-p-revA
  36. 1171 0
      board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
  37. 22 13
      board/xilinx/zynqmp/zynqmp.c
  38. 2 0
      cmd/Kconfig
  39. 3 2
      common/image.c
  40. 1 0
      common/spl/Kconfig
  41. 0 2
      configs/avnet_ultra96_rev1_defconfig
  42. 0 2
      configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
  43. 2 0
      configs/microblaze-generic_defconfig
  44. 0 1
      configs/syzygy_hub_defconfig
  45. 3 0
      configs/xilinx_versal_mini_defconfig
  46. 4 0
      configs/xilinx_versal_mini_emmc0_defconfig
  47. 4 0
      configs/xilinx_versal_mini_emmc1_defconfig
  48. 2 5
      configs/xilinx_versal_virt_defconfig
  49. 115 0
      configs/xilinx_zynqmp_a2197_g_revA_defconfig
  50. 115 0
      configs/xilinx_zynqmp_a2197_m_revA_defconfig
  51. 116 0
      configs/xilinx_zynqmp_a2197_p_revA_defconfig
  52. 117 0
      configs/xilinx_zynqmp_a2197_revA_defconfig
  53. 0 1
      configs/xilinx_zynqmp_mini_defconfig
  54. 0 2
      configs/xilinx_zynqmp_mini_emmc0_defconfig
  55. 0 2
      configs/xilinx_zynqmp_mini_emmc1_defconfig
  56. 1 1
      configs/xilinx_zynqmp_mini_nand_defconfig
  57. 0 2
      configs/xilinx_zynqmp_mini_qspi_defconfig
  58. 108 0
      configs/xilinx_zynqmp_virt_defconfig
  59. 0 2
      configs/xilinx_zynqmp_zc1232_revA_defconfig
  60. 0 2
      configs/xilinx_zynqmp_zc1254_revA_defconfig
  61. 0 2
      configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
  62. 0 2
      configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
  63. 0 2
      configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
  64. 0 2
      configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
  65. 0 2
      configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
  66. 0 2
      configs/xilinx_zynqmp_zcu100_revC_defconfig
  67. 1 2
      configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
  68. 1 2
      configs/xilinx_zynqmp_zcu102_revA_defconfig
  69. 1 2
      configs/xilinx_zynqmp_zcu102_revB_defconfig
  70. 0 2
      configs/xilinx_zynqmp_zcu104_revA_defconfig
  71. 3 2
      configs/xilinx_zynqmp_zcu104_revC_defconfig
  72. 0 2
      configs/xilinx_zynqmp_zcu106_revA_defconfig
  73. 0 2
      configs/xilinx_zynqmp_zcu111_revA_defconfig
  74. 0 2
      configs/xilinx_zynqmp_zcu1275_revA_defconfig
  75. 0 2
      configs/xilinx_zynqmp_zcu1275_revB_defconfig
  76. 0 1
      configs/zynq_cc108_defconfig
  77. 0 1
      configs/zynq_cse_nand_defconfig
  78. 0 1
      configs/zynq_cse_nor_defconfig
  79. 0 1
      configs/zynq_cse_qspi_defconfig
  80. 0 1
      configs/zynq_dlc20_rev1_0_defconfig
  81. 0 1
      configs/zynq_microzed_defconfig
  82. 0 1
      configs/zynq_minized_defconfig
  83. 0 1
      configs/zynq_picozed_defconfig
  84. 79 0
      configs/zynq_virt_defconfig
  85. 0 1
      configs/zynq_z_turn_defconfig
  86. 0 1
      configs/zynq_zc702_defconfig
  87. 0 1
      configs/zynq_zc706_defconfig
  88. 0 1
      configs/zynq_zc770_xm010_defconfig
  89. 0 1
      configs/zynq_zc770_xm011_defconfig
  90. 0 1
      configs/zynq_zc770_xm011_x16_defconfig
  91. 0 1
      configs/zynq_zc770_xm012_defconfig
  92. 0 1
      configs/zynq_zc770_xm013_defconfig
  93. 0 1
      configs/zynq_zed_defconfig
  94. 0 1
      configs/zynq_zybo_defconfig
  95. 0 1
      configs/zynq_zybo_z7_defconfig
  96. 1 0
      doc/board/xilinx/index.rst
  97. 38 0
      doc/board/xilinx/xilinx.rst
  98. 9 0
      drivers/clk/Kconfig
  99. 1 0
      drivers/clk/Makefile
  100. 746 0
      drivers/clk/clk_versal.c

+ 4 - 0
MAINTAINERS

@@ -404,6 +404,7 @@ M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-versal/
+N:	(?<!uni)versal
 
 ARM VERSATILE EXPRESS DRIVERS
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
@@ -442,11 +443,13 @@ S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp/
 F:	drivers/clk/clk_zynqmp.c
+F:	driver/firmware/firmware-zynqmp.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
 F:	drivers/i2c/i2c-cdns.c
 F:	drivers/i2c/muxes/pca954x.c
 F:	drivers/i2c/zynq_i2c.c
+F:	drivers/mailbox/zynqmp-ipi.c
 F:	drivers/mmc/zynq_sdhci.c
 F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
@@ -458,6 +461,7 @@ F:	drivers/timer/cadence-ttc.c
 F:	drivers/usb/host/ehci-zynq.c
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqmppl.h
+F:	include/zynqmp_firmware.h
 F:	tools/zynqmp*
 N:	ultra96
 N:	zynqmp

+ 22 - 0
arch/arm/Kconfig

@@ -462,6 +462,22 @@ config TPL_USE_ARCH_MEMSET
 	  Such implementation may be faster under some conditions
 	  but may increase the binary size.
 
+config SET_STACK_SIZE
+	bool "Enable an option to set max stack size that can be used"
+	default y if ARCH_VERSAL || ARCH_ZYNQMP
+	help
+	  This will enable an option to set max stack size that can be
+	  used by u-boot.
+
+config STACK_SIZE
+	hex "Define max stack size that can be used by u-boot"
+	depends on SET_STACK_SIZE
+	default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
+	help
+	  Defines Max stack size that can be used by u-boot so that the
+	  initrd_high will be calculated as base stack pointer minus this
+	  stack size.
+
 config ARM64_SUPPORT_AARCH32
 	bool "ARM64 system support AArch32 execution state"
 	depends on ARM64
@@ -980,6 +996,7 @@ config ARCH_VERSAL
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select OF_CONTROL
+	imply BOARD_LATE_INIT
 
 config ARCH_VF610
 	bool "Freescale Vybrid"
@@ -1034,16 +1051,21 @@ config ARCH_ZYNQMP
 	select CLK
 	select DM
 	select DM_ETH if NET
+	select DM_MAILBOX
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_SPI if SPI
 	select DM_SPI_FLASH if DM_SPI
 	select DM_USB if USB
+	select FIRMWARE
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
 	select SPL_CLK if SPL
+	select SPL_DM_MAILBOX if SPL
+	select SPL_FIRMWARE if SPL
 	select SPL_SEPARATE_BSS if SPL
 	select SUPPORT_SPL
+	select ZYNQMP_IPI
 	imply BOARD_LATE_INIT
 	imply CMD_DM
 	imply FAT_WRITE

+ 4 - 0
arch/arm/dts/Makefile

@@ -247,6 +247,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	avnet-ultra96-rev1.dtb			\
 	avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb	\
+	zynqmp-a2197-revA.dtb			\
+	zynqmp-a2197-g-revA.dtb			\
+	zynqmp-a2197-m-revA.dtb			\
+	zynqmp-a2197-p-revA.dtb			\
 	zynqmp-mini.dtb				\
 	zynqmp-mini-emmc0.dtb			\
 	zynqmp-mini-emmc1.dtb			\

+ 4 - 0
arch/arm/dts/zynq-cse-qspi-single.dts

@@ -7,6 +7,10 @@
 
 #include "zynq-cse-qspi.dtsi"
 
+/ {
+	model = "Zynq CSE QSPI SINGLE Board";
+};
+
 &flash0 {
 	spi-rx-bus-width = <4>;
 };

+ 1 - 0
arch/arm/dts/zynq-zc702.dts

@@ -16,6 +16,7 @@
 		serial0 = &uart1;
 		spi0 = &qspi;
 		mmc0 = &sdhci0;
+		usb0 = &usb0;
 	};
 
 	memory@0 {

+ 282 - 0
arch/arm/dts/zynqmp-a2197-g-revA.dts

@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller on MGT
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Versal System Controller on a2197 MGT Char board RevA";
+	compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA",
+		     "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem0;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		mmc0 = &sdhci0;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &dcc;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+		xlnx,eeprom = <&eeprom>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&sdhci0 { /* emmc MIO 13-23 16GB */
+	status = "okay";
+	non-removable;
+	disable-wp;
+	bus-width = <8>;
+	xlnx,mio_bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&gem0 { /* eth MDIO 76/77 */
+	status = "okay";
+	phy-handle = <&phy0>;
+	phy-mode = "sgmii";
+	is-internal-pcspma;
+	phy0: phy@0 { /* marwell m88e1512 */
+		reg = <0>;
+		reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+/*		xlnx,phy-type = <PHY_TYPE_SGMII>; */
+	};
+/*	phy-names = "...";
+	phys = <&lane0 PHY_TYPE_SGMII ... >
+	Note: lane0 sgmii/lane1 usb3 */
+};
+
+&gpio {
+	status = "okay";
+	gpio-line-names = "", "", "", "", "", /* 0 - 4 */
+		  "", "", "", "", "", /* 5 - 9 */
+		  "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+		  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+		  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+		  "", "", "", "", "", /* 25 - 29 */
+		  "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+		  "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+		  "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+		  "", "", "", "", "", /* 45 - 49 */
+		  "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+		  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+		  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+		  "", "", "", "", "", /* 65 - 69 */
+		  "", "", "", "", "", /* 70 - 74 */
+		  "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+		  "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+		  "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
+		  "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+		  "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+		  "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+		  "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
+		  "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
+		  "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
+		  "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
+		  "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
+		  "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
+		  "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
+		  "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
+		  "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+		  "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
+		  "", "", "", "", "", /* 150 - 154 */
+		  "", "", "", "", "", /* 155 - 159 */
+		  "", "", "", "", "", /* 160 - 164 */
+		  "", "", "", "", "", /* 165 - 169 */
+		  "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+	status = "okay";
+	clock-frequency = <400000>;
+	scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+	i2c-mux@74 { /* u94 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* Use for storing information about SC board */
+			eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */
+				compatible = "atmel,24c32";
+				reg = <0x50>;
+			};
+		};
+		i2c@1 { /* CM_I2C_SCL - Samtec */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+		i2c@2 { /* PMBUS - AFX_PMBUS */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			tps544@d { /* u85 */
+				compatible = "ti,tps544b25";
+				reg = <0xd>;
+			};
+			tps544@10 { /* u73 */
+				compatible = "ti,tps544b25";
+				reg = <0x10>;
+			};
+			tps544@11 { /* u76 */
+				compatible = "ti,tps544b25";
+				reg = <0x11>;
+			};
+			tps544@12 { /* u77 */
+				compatible = "ti,tps544b25";
+				reg = <0x12>;
+			};
+			tps544@13 { /* u80 */
+				compatible = "ti,tps544b25";
+				reg = <0x13>;
+			};
+			tps544@14 { /* u81 */
+				compatible = "ti,tps544b25";
+				reg = <0x14>;
+			};
+			tps544@15 { /* u83 */
+				compatible = "ti,tps544b25";
+				reg = <0x15>;
+			};
+			tps544@16 { /* u63 */
+				compatible = "ti,tps544b25";
+				reg = <0x16>;
+			};
+			tps544@17 { /* u66 */
+				compatible = "ti,tps544b25";
+				reg = <0x17>;
+			};
+			tps544@18 { /* u67 */
+				compatible = "ti,tps544b25";
+				reg = <0x18>;
+			};
+			tps544@19 { /* u69 */
+				compatible = "ti,tps544b25";
+				reg = <0x19>;
+			};
+			tps544@1d { /* u88 */
+				compatible = "ti,tps544b25";
+				reg = <0x1d>;
+			};
+			tps544@1e { /* u89 */
+				compatible = "ti,tps544b25";
+				reg = <0x1e>;
+			};
+			tps544@1f { /* u87 */
+				compatible = "ti,tps544b25";
+				reg = <0x1f>;
+			};
+			tps544@20 { /* u71 */
+				compatible = "ti,tps544b25";
+				reg = <0x20>;
+			};
+			ina226@40 { /* u74 */
+				compatible = "ti,ina226";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+			ina226@41 { /* u75 */
+				compatible = "ti,ina226";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+			ina226@42 { /* u78 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			ina226@43 { /* u79 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <1000>;
+			};
+			ina226@44 { /* u82 */
+				compatible = "ti,ina226";
+				reg = <0x44>;
+				shunt-resistor = <1000>;
+			};
+			ina226@45 { /* u84 */
+				compatible = "ti,ina226";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+			tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
+				compatible = "ti,tps53681"; /* FIXME no linux driver */
+				reg = <0xc0>;
+			};
+		};
+		i2c@3 { /* fmc1 via JA2G */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			eeprom_fmc1: eeprom@50 { /* on FMC */
+				compatible = "atmel,24c04";
+				reg = <0x50>;
+			};
+		};
+		i2c@4 { /* fmc2 via JA3G */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			eeprom_fmc2: eeprom@50 { /* on FMC */
+				compatible = "atmel,24c04";
+				reg = <0x50>;
+			};
+		};
+		i2c@5 { /* fmc3 via JA4G */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			eeprom_fmc3: eeprom@50 { /* on FMC */
+				compatible = "atmel,24c04";
+				reg = <0x50>;
+			};
+		};
+		i2c@6 { /* ddr dimm */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+		};
+		/* 7 unused */
+	};
+};
+
+&usb0 { /* USB0 MIO52-63 */
+	status = "okay";
+	xlnx,usb-polarity = <0>;
+	xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "peripheral";
+	maximum-speed = "high-speed";
+};

+ 461 - 0
arch/arm/dts/zynqmp-a2197-m-revA.dts

@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Versal System Controller on a2197 Memory Char board RevA";
+	compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA",
+		     "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem0;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &dcc;
+		usb0 = &usb0;
+		usb1 = &usb1;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+		xlnx,eeprom = <&eeprom>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
+	};
+};
+
+&qspi {
+	status = "okay";
+	is-dual = <1>;
+	flash@0 {
+		compatible = "m25p80", "spi-flash"; /* 32MB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <108000000>;
+	};
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings  16GB */
+	status = "okay";
+	non-removable;
+	disable-wp;
+	bus-width = <8>;
+	xlnx,mio_bank = <0>; /* FIXME tap delay */
+};
+
+&uart0 { /* uart0 MIO38-39 */
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 { /* uart1 MIO40-41 */
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+	status = "disable";
+	no-1-8-v;
+	disable-wp;
+	xlnx,mio_bank = <1>;
+};
+
+&gem0 {
+	status = "okay";
+	phy-handle = <&phy0>;
+	phy-mode = "sgmii"; /* DTG generates this properly  1512 */
+	phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
+	phy0: phy@0 { /* marwell m88e1512 - SGMII */
+		reg = <0>;
+/*		xlnx,phy-type = <PHY_TYPE_SGMII>; */
+	};
+/*	phy-names = "...";
+	phys = <&lane0 PHY_TYPE_SGMII ... >
+	Note: lane0 sgmii/lane1 usb3 */
+};
+
+&gpio {
+	status = "okay";
+	gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
+		  "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
+		  "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+		  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+		  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+		  "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
+		  "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+		  "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+		  "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
+		  "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+		  "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+		  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+		  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+		  "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+		  "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+		  "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+		  "", "", "", "", "", /* 78 - 79 */
+		  "", "", "", "", "", /* 80 - 84 */
+		  "", "", "", "", "", /* 85 -89 */
+		  "", "", "", "", "", /* 90 - 94 */
+		  "", "", "", "", "", /* 95 - 99 */
+		  "", "", "", "", "", /* 100 - 104 */
+		  "", "", "", "", "", /* 105 - 109 */
+		  "", "", "", "", "", /* 110 - 114 */
+		  "", "", "", "", "", /* 115 - 119 */
+		  "", "", "", "", "", /* 120 - 124 */
+		  "", "", "", "", "", /* 125 - 129 */
+		  "", "", "", "", "", /* 130 - 134 */
+		  "", "", "", "", "", /* 135 - 139 */
+		  "", "", "", "", "", /* 140 - 144 */
+		  "", "", "", "", "", /* 145 - 149 */
+		  "", "", "", "", "", /* 150 - 154 */
+		  "", "", "", "", "", /* 155 - 159 */
+		  "", "", "", "", "", /* 160 - 164 */
+		  "", "", "", "", "", /* 165 - 169 */
+		  "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+	status = "okay";
+	clock-frequency = <400000>;
+	i2c-mux@74 { /* u46 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+		i2c@0 { /* PMBUS  must be enabled via SW21 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			reg_vcc1v2_lp4: tps544@15 { /* u97 */
+				compatible = "ti,tps544b25";
+				reg = <0x15>;
+			};
+			reg_vcc1v1_lp4: tps544@16 { /* u95 */
+				compatible = "ti,tps544b25";
+				reg = <0x16>;
+			};
+			reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
+				compatible = "ti,tps544b25";
+				reg = <0x17>;
+			};
+			/* UTIL_PMBUS connection */
+			reg_vcc1v8: tps544@13 { /* u92 */
+				compatible = "ti,tps544b25";
+				reg = <0x13>;
+			};
+			reg_vcc3v3: tps544@14 { /* u93 */
+				compatible = "ti,tps544b25";
+				reg = <0x14>;
+			};
+			reg_vcc5v0: tps544@1e { /* u94 */
+				compatible = "ti,tps544b25";
+				reg = <0x1e>;
+			};
+		};
+		i2c@1 { /* PMBUS_INA226 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			vcc_aux: ina226@42 { /* u86 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			vcc_ram: ina226@43 { /* u81 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			vcc1v1_lp4: ina226@46 { /* u96 */
+				compatible = "ti,ina226";
+				reg = <0x46>;
+				shunt-resistor = <5000>;
+			};
+			vcc1v2_lp4: ina226@47 { /* u98 */
+				compatible = "ti,ina226";
+				reg = <0x47>;
+				shunt-resistor = <5000>;
+			};
+			vdd1_1v8_lp4: ina226@48 { /* u100 */
+				compatible = "ti,ina226";
+				reg = <0x48>;
+				shunt-resistor = <5000>;
+			};
+			vcc0v6_lp4: ina226@49 { /* u101 */
+				compatible = "ti,ina226";
+				reg = <0x49>;
+				shunt-resistor = <5000>;
+			};
+		};
+		i2c@2 { /* PMBUS1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			reg_vccint: tps53681@c0 { /* u69 */
+				compatible = "ti,tps53681"; /* FIXME no linux driver */
+				reg = <0xc0>;
+			};
+			reg_vcc_pmc: tps544@7 { /* u80 */
+				compatible = "ti,tps544b25";
+				reg = <0x7>;
+			};
+			reg_vcc_ram: tps544@8 { /* u82 */
+				compatible = "ti,tps544b25";
+				reg = <0x8>;
+			};
+			reg_vcc_pslp: tps544@9 { /* u83 */
+				compatible = "ti,tps544b25";
+				reg = <0x9>;
+			};
+			reg_vcc_psfp: tps544@a { /* u84 */
+				compatible = "ti,tps544b25";
+				reg = <0xa>;
+			};
+			reg_vccaux: tps544@d { /* u85 */
+				compatible = "ti,tps544b25";
+				reg = <0xd>;
+			};
+			reg_vccaux_pmc: tps544@e { /* u87 */
+				compatible = "ti,tps544b25";
+				reg = <0xe>;
+			};
+			reg_vcco_500: tps544@f { /* u88 */
+				compatible = "ti,tps544b25";
+				reg = <0xf>;
+			};
+			reg_vcco_501: tps544@10 { /* u89 */
+				compatible = "ti,tps544b25";
+				reg = <0x10>;
+			};
+			reg_vcco_502: tps544@11 { /* u90 */
+				compatible = "ti,tps544b25";
+				reg = <0x11>;
+			};
+			reg_vcco_503: tps544@12 { /* u91 */
+				compatible = "ti,tps544b25";
+				reg = <0x12>;
+			};
+		};
+		i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			/* reg = <3>; */
+		};
+		i2c@4 { /* LP_I2C_SM */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			/* connected to U20G */
+		};
+		/* 5-7 unused */
+	};
+};
+
+/* TODO sysctrl via J239 */
+/* TODO samtec J212G/H via J242 */
+/* TODO teensy via U30 PCA9543A bus 1 */
+&i2c1 { /* i2c1 MIO 36-37 */
+	status = "okay";
+	clock-frequency = <400000>;
+
+	/* Must be enabled via J242 */
+	eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+	};
+
+	i2c-mux@74 { /* u35 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
+		dc_i2c: i2c@0 { /* DC_I2C */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* Use for storing information about SC board */
+			eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
+				compatible = "atmel,24c08";
+				reg = <0x54>;
+			};
+			si570_ref_clk: clock-generator@5d { /* u26 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>; /* FIXME addr */
+				temperature-stability = <50>;
+				factory-fout = <156250000>; /* FIXME every chip can be different */
+				clock-frequency = <33333333>;
+				clock-output-names = "REF_CLK"; /* FIXME */
+			};
+			/* Connection via Samtec U20D */
+			/* Use for storing information about X-PRC card */
+			x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			/* Use for setting up certain features on X-PRC card */
+			x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
+				compatible = "nxp,pca9534";
+				reg = <0x22>;
+				gpio-controller; /* IRQ not connected */
+				#gpio-cells = <2>;
+				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+						  "", "", "", "";
+				gtr_sel0 {
+					gpio-hog;
+					gpios = <0 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_1";
+				};
+				gtr_sel1 {
+					gpio-hog;
+					gpios = <1 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_2";
+				};
+				gtr_sel2 {
+					gpio-hog;
+					gpios = <2 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_3";
+				};
+				gtr_sel3 {
+					gpio-hog;
+					gpios = <3 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_4";
+				};
+			};
+		};
+		i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			/* reg = <1>; */
+		};
+		i2c@2 { /* C0_LP4 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			si570_c0_lp4: clock-generator@5d { /* u10 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>; /* FIXME addr */
+				temperature-stability = <50>;
+				factory-fout = <30000000>;
+				clock-frequency = <30000000>;
+				clock-output-names = "C0_LP4_SI570_CLK";
+			};
+		};
+		i2c@3 { /* C1_LP4 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			si570_c1_lp4: clock-generator@5d { /* u10 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>; /* FIXME addr */
+				temperature-stability = <50>;
+				factory-fout = <30000000>;
+				clock-frequency = <30000000>;
+				clock-output-names = "C1_LP4_SI570_CLK";
+			};
+		};
+		i2c@4 { /* C2_LP4 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			si570_c2_lp4: clock-generator@5d { /* u10 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>; /* FIXME addr */
+				temperature-stability = <50>;
+				factory-fout = <30000000>;
+				clock-frequency = <30000000>;
+				clock-output-names = "C2_LP4_SI570_CLK";
+			};
+		};
+		i2c@5 { /* C3_LP4 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			si570_c3_lp4: clock-generator@5d { /* u15 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>; /* FIXME addr */
+				temperature-stability = <50>;
+				factory-fout = <30000000>;
+				clock-frequency = <30000000>;
+				clock-output-names = "C3_LP4_SI570_CLK";
+			};
+		};
+		i2c@6 { /* HSDP_SI570 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			si570_hsdp: clock-generator@5d { /* u19 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>; /* FIXME addr */
+				temperature-stability = <50>;
+				factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+				clock-frequency = <33333333>;
+				clock-output-names = "HSDP_SI570";
+			};
+		};
+	};
+};
+
+&usb0 {
+	status = "okay";
+	xlnx,usb-polarity = <0>;
+	xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+	/* dr_mode = "peripheral"; */
+	maximum-speed = "high-speed";
+};
+
+&usb1 {
+	status = "disabled"; /* not at mem board */
+	xlnx,usb-polarity = <0>;
+	xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+	/delete-property/ phy-names ;
+	/delete-property/ phys ;
+	maximum-speed = "high-speed";
+	snps,dis_u2_susphy_quirk ;
+	snps,dis_u3_susphy_quirk ;
+	status = "disabled";
+};

+ 567 - 0
arch/arm/dts/zynqmp-a2197-p-revA.dts

@@ -0,0 +1,567 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
+	compatible = "xlnx,zynqmp-a2197-p-revA", "xlnx,zynqmp-a2197-revA",
+		     "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem0;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &dcc;
+		usb0 = &usb0;
+		usb1 = &usb1;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+		xlnx,eeprom = <&eeprom>;
+		/* xlnx,fmc-eeprom = FIXME */
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
+	};
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings  16GB */
+	status = "okay";
+	non-removable;
+	disable-wp;
+	bus-width = <8>;
+	xlnx,mio_bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&uart1 { /* uart1 MIO40-41 */
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+	status = "okay";
+	no-1-8-v;
+	disable-wp;
+	xlnx,mio_bank = <1>;
+};
+
+&gem0 {
+	status = "okay";
+	phy-handle = <&phy0>;
+	phy-mode = "sgmii"; /* DTG generates this properly  1512 */
+	is-internal-pcspma;
+	/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+	phy0: phy@0 {
+		reg = <0>;
+	};
+};
+
+&gpio {
+	status = "okay";
+	gpio-line-names = "", "", "", "", "", /* 0 - 4 */
+		  "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
+		  "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+		  "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+		  "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+		  "", "", "", "", "", /* 25 - 29 */
+		  "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+		  "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+		  "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
+		  "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+		  "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+		  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+		  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+		  "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+		  "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+		  "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+		  "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+		  "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
+		  "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+		  "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+		  "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+		  "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
+		  "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
+		  "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
+		  "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
+		  "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
+		  "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
+		  "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
+		  "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
+		  "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+		  "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
+		  "", "", "", "", "", /* 150 - 154 */
+		  "", "", "", "", "", /* 155 - 159 */
+		  "", "", "", "", "", /* 160 - 164 */
+		  "", "", "", "", "", /* 165 - 169 */
+		  "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+	status = "okay";
+	clock-frequency = <400000>;
+	i2c-mux@74 { /* u33 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+		i2c@0 { /* PMBUS1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* On connector J98 */
+			reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x7>;
+				regulator-name = "reg_vcc_fmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <2600000>;
+				/* enable-gpio = <&gpio0 23 0x4>; optional */
+			};
+			reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x8>;
+			};
+			reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x9>;
+			};
+			reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0xa>;
+			};
+			reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
+				compatible = "ti,tps53681"; /* FIXME no linux driver */
+				reg = <0xc0>;
+				/* vccint, vcc_io_soc */
+			};
+		};
+		i2c@1 { /* PMBUS1_INA226 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* FIXME check alerts comming to SC */
+			vcc_fmc: ina226@42 { /* u81 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			vcc_ram: ina226@43 { /* u82 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			vcc_pslp: ina226@44 { /* u84 */
+				compatible = "ti,ina226";
+				reg = <0x44>;
+				shunt-resistor = <5000>;
+			};
+			vcc_psfp: ina226@45 { /* u87 */
+				compatible = "ti,ina226";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+		};
+		i2c@2 { /* PMBUS2 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* On connector J104 */
+			reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0xd>;
+			};
+			reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0xe>;
+			};
+			reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0xf>;
+			};
+			reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x10>;
+			};
+			reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x11>;
+			};
+			reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x12>;
+			};
+			reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x13>;
+			};
+			reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x14>;
+			};
+			reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x15>;
+			};
+			reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x16>;
+			};
+			reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x17>;
+			};
+			reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x19>;
+			};
+			reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x1a>;
+			};
+			reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x1b>;
+			};
+			reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x1c>;
+			};
+			reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x1d>;
+			};
+			reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x1e>;
+			};
+			reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */
+				compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+				reg = <0x1f>;
+			};
+		};
+		i2c@3 { /* PMBUS2_INA226 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			/* FIXME check alerts coming to SC */
+			vccaux: ina226@40 { /* u89 */
+				compatible = "ti,ina226";
+				reg = <0x40>;
+				shunt-resistor = <5000>;
+			};
+			vccaux_fmc: ina226@41 { /* u91 */
+				compatible = "ti,ina226";
+				reg = <0x41>;
+				shunt-resistor = <5000>;
+			};
+			vcco_500: ina226@42 { /* u92 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			vcco_501: ina226@43 { /* u94 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			vcco_502: ina226@44 { /* u96 */
+				compatible = "ti,ina226";
+				reg = <0x44>;
+				shunt-resistor = <5000>;
+			};
+			vcco_503: ina226@45 { /* u98 */
+				compatible = "ti,ina226";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+			vcc_1v8: ina226@46 { /* u100 */
+				compatible = "ti,ina226";
+				reg = <0x46>;
+				shunt-resistor = <5000>;
+			};
+			vcc_3v3: ina226@47 { /* u103 */
+				compatible = "ti,ina226";
+				reg = <0x47>;
+				shunt-resistor = <5000>;
+			};
+			vcc_1v2_ddr4: ina226@48 { /* u105 */
+				compatible = "ti,ina226";
+				reg = <0x48>;
+				shunt-resistor = <1000>;
+			};
+			vcc1v1_lp4: ina226@49 { /* u107 */
+				compatible = "ti,ina226";
+				reg = <0x49>;
+				shunt-resistor = <5000>;
+			};
+			vadj_fmc: ina226@4a { /* u110 */
+				compatible = "ti,ina226";
+				reg = <0x4a>;
+				shunt-resistor = <5000>;
+			};
+			mgtyavcc: ina226@4b { /* u112 */
+				compatible = "ti,ina226";
+				reg = <0x4b>;
+				shunt-resistor = <1000>;
+			};
+			mgtyavtt: ina226@4c { /* u113 */
+				compatible = "ti,ina226";
+				reg = <0x4c>;
+				shunt-resistor = <1000>;
+			};
+			mgtyvccaux: ina226@4d { /* u116 */
+				compatible = "ti,ina226";
+				reg = <0x4d>;
+				shunt-resistor = <5000>;
+			};
+			vcc_bat: ina226@4e { /* u12 */
+				compatible = "ti,ina226";
+				reg = <0x4e>;
+				shunt-resistor = <10000000>; /* 10 ohm */
+			};
+		};
+		i2c@4 { /* LP_I2C_SM */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			/* connected to J212G */
+			/* zynqmp sm alert or samtec J212H */
+		};
+		/* 5-7 unused */
+	};
+};
+
+&i2c1 { /* i2c1 MIO 36-37 */
+	status = "okay";
+	clock-frequency = <400000>;
+
+	/* Must be enabled via J242 */
+	eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+	};
+
+	i2c-mux@74 { /* u35 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+		dc_i2c: i2c@0 { /* DC_I2C */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* Use for storing information about SC board */
+			eeprom: eeprom@54 { /* u34 - m24128 16kB */
+				compatible = "st,24c128", "atmel,24c128";
+				reg = <0x54>;
+			};
+			si570_ref_clk: clock-generator@5d { /* u32 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;	/* 570JAC000900DG */
+				temperature-stability = <50>;
+				factory-fout = <156250000>; /* FIXME every chip can be different */
+				clock-frequency = <33333333>;
+				clock-output-names = "REF_CLK"; /* FIXME */
+			};
+			/* Connection via Samtec J212D */
+			/* Use for storing information about X-PRC card */
+			x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			/* Use for setting up certain features on X-PRC card */
+			x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
+				compatible = "nxp,pca9534";
+				reg = <0x22>;
+				gpio-controller; /* IRQ not connected */
+				#gpio-cells = <2>;
+				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+						  "", "", "", "";
+				gtr_sel0 {
+					gpio-hog;
+					gpios = <0 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_1";
+				};
+				gtr_sel1 {
+					gpio-hog;
+					gpios = <1 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_2";
+				};
+				gtr_sel2 {
+					gpio-hog;
+					gpios = <2 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_3";
+				};
+				gtr_sel3 {
+					gpio-hog;
+					gpios = <3 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_4";
+				};
+			};
+		};
+		i2c@1 { /* FMCP1_IIC */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* FIXME connection to Samtec J51C */
+			/* expected eeprom 0x50 SE cards */
+		};
+		i2c@2 { /* FMCP2_IIC */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* FIXME connection to Samtec J53C */
+			/* expected eeprom 0x50 SE cards */
+		};
+		i2c@3 { /* DDR4_DIMM1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			si570_ddr_dimm1: clock-generator@60 { /* u2 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x60>;	/* 570BAB000299DG */
+				temperature-stability = <50>;
+				factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+				clock-frequency = <33333333>;
+				clock-output-names = "REF_CLK"; /* FIXME */
+			};
+			/* 0x50 SPD? */
+		};
+		i2c@4 { /* DDR4_DIMM2 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			si570_ddr_dimm2: clock-generator@60 { /* u3 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x60>;	/* 570BAB000299DG */
+				temperature-stability = <50>;
+				factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+				clock-frequency = <33333333>;
+				clock-output-names = "REF_CLK"; /* FIXME */
+			};
+			/* 0x50 SPD? */
+		};
+		i2c@5 { /* LPDDR4_SI570_CLK */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			si570_lpddr4: clock-generator@60 { /* u4 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x60>;	/* 570BAB000299DG */
+				temperature-stability = <50>;
+				factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+				clock-frequency = <33333333>;
+				clock-output-names = "LPDDR4_SI570_CLK";
+			};
+		};
+		i2c@6 { /* HSDP_SI570 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			si570_hsdp: clock-generator@5d { /* u5 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;	/* 570JAC000900DG */
+				temperature-stability = <50>;
+				factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+				clock-frequency = <33333333>;
+				clock-output-names = "HSDP_SI570";
+			};
+		};
+		i2c@7 { /* PCIE_CLK */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+			/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
+			/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */
+			/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
+			clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */
+				#clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
+				compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
+				reg = <0xd8>;
+				/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
+				/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
+
+			};
+
+		};
+	};
+};
+
+&usb0 {
+	status = "okay";
+	xlnx,usb-polarity = <0>;
+	xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "peripheral";
+	snps,dis_u2_susphy_quirk;
+	snps,dis_u3_susphy_quirk;
+	maximum-speed = "super-speed";
+};
+
+&usb1 {
+	status = "okay";
+	xlnx,usb-polarity = <0>;
+	xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+	/delete-property/ phy-names ;
+	/delete-property/ phys ;
+	dr_mode = "host";
+	maximum-speed = "high-speed";
+	snps,dis_u2_susphy_quirk ;
+	snps,dis_u3_susphy_quirk ;
+	status = "okay";
+};
+
+&xilinx_ams {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
+&ams_pl {
+	status = "okay";
+};

+ 89 - 0
arch/arm/dts/zynqmp-a2197-revA.dts

@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Versal System Controller on a2197 board RevA";
+	compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+	aliases {
+		i2c0 = &i2c0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+		xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&uart0 { /* uart0 MIO38-39 */
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+	clock-frequency = <400000>;
+	i2c-mux@74 { /* this cover MGT board */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		u-boot,dm-pre-reloc;
+		/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* Use for storing information about SC board */
+			eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */
+				compatible = "atmel,24c32";
+				u-boot,dm-pre-reloc;
+				reg = <0x50>;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+	clock-frequency = <400000>;
+	i2c-mux@74 { /* This cover processor board */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		u-boot,dm-pre-reloc;
+		/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* Use for storing information about SC board */
+			eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */
+				compatible = "atmel,24c32";
+				u-boot,dm-pre-reloc;
+				reg = <0x50>;
+			};
+		};
+	};
+};

+ 1 - 0
arch/arm/dts/zynqmp-clk.dtsi

@@ -38,6 +38,7 @@
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <300000000>;
+		u-boot,dm-pre-reloc;
 	};
 
 	clk600: clk600 {

+ 1 - 1
arch/arm/dts/zynqmp-mini-qspi.dts

@@ -64,7 +64,7 @@
 &qspi {
 	status = "okay";
 	flash0: flash@0 {
-		compatible = "n25q512a11", "spi-flash";
+		compatible = "n25q512a11", "jedec,spi-nor";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;

+ 39 - 5
arch/arm/dts/zynqmp.dtsi

@@ -96,6 +96,29 @@
 		};
 	};
 
+	zynqmp_ipi {
+		u-boot,dm-pre-reloc;
+		compatible = "xlnx,zynqmp-ipi-mailbox";
+		interrupt-parent = <&gic>;
+		interrupts = <0 35 4>;
+		xlnx,ipi-id = <0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ipi_mailbox_pmu1: mailbox@ff990400 {
+			u-boot,dm-pre-reloc;
+			reg = <0x0 0xff9905c0 0x0 0x20>,
+			      <0x0 0xff9905e0 0x0 0x20>,
+			      <0x0 0xff990e80 0x0 0x20>,
+			      <0x0 0xff990ea0 0x0 0x20>;
+			reg-names = "local_request_region" , "local_response_region",
+				    "remote_request_region", "remote_response_region";
+			#mbox-cells = <1>;
+			xlnx,ipi-id = <4>;
+		};
+	};
+
 	dcc: dcc {
 		compatible = "arm,dcc";
 		status = "disabled";
@@ -116,11 +139,22 @@
 		method = "smc";
 	};
 
-	pmufw: firmware {
-		compatible = "xlnx,zynqmp-pm";
-		method = "smc";
-		interrupt-parent = <&gic>;
-		interrupts = <0 35 4>;
+	firmware {
+		zynqmp-firmware {
+			compatible = "xlnx,zynqmp-firmware";
+			method = "smc";
+			#power-domain-cells = <0x1>;
+			u-boot,dm-pre-reloc;
+
+			zynqmp_power: zynqmp-power {
+				u-boot,dm-pre-reloc;
+				compatible = "xlnx,zynqmp-power";
+				interrupt-parent = <&gic>;
+				interrupts = <0 35 4>;
+				mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
+				mbox-names = "tx", "rx";
+			};
+		};
 	};
 
 	timer {

+ 7 - 5
arch/arm/mach-versal/Kconfig

@@ -36,11 +36,6 @@ config COUNTER_FREQUENCY
 config ZYNQ_SDHCI_MAX_FREQ
 	default 200000000
 
-config VERSAL_OF_BOARD_DTB_ADDR
-	hex
-	default 0x1000
-	depends on OF_BOARD
-
 config IOU_SWITCH_DIVISOR0
 	hex "IOU switch divisor0"
 	default 0x20
@@ -54,4 +49,11 @@ config SYS_MEM_RSVD_FOR_MMU
 	  MMU table than the one which will be allocated during
 	  relocation.
 
+config DEFINE_TCM_OCM_MMAP
+	bool "Define TCM and OCM memory in MMU Table"
+	default y if MP
+	help
+	  This option if enabled defines the TCM and OCM memory and its
+	  memory attributes in MMU table entry.
+
 endif

+ 60 - 24
arch/arm/mach-versal/cpu.c

@@ -12,14 +12,21 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct mm_region versal_mem_map[] = {
+#define VERSAL_MEM_MAP_USED	5
+
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#define TCM_MAP 1
+#else
+#define TCM_MAP 0
+#endif
+
+/* +1 is end of list which needs to be empty */
+#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
+
+static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
 	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
 		.size = 0x70000000UL,
@@ -33,12 +40,6 @@ static struct mm_region versal_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0xffe00000UL,
-		.phys = 0xffe00000UL,
-		.size = 0x00200000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
 	}, {
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
@@ -59,12 +60,36 @@ static struct mm_region versal_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
 	}
 };
 
+void mem_map_fill(void)
+{
+	int banks = VERSAL_MEM_MAP_USED;
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+	versal_mem_map[banks].virt = 0xffe00000UL;
+	versal_mem_map[banks].phys = 0xffe00000UL;
+	versal_mem_map[banks].size = 0x00200000UL;
+	versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				      PTE_BLOCK_INNER_SHARE;
+	banks = banks + 1;
+#endif
+
+	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* Zero size means no more DDR that's this is end */
+		if (!gd->bd->bi_dram[i].size)
+			break;
+
+		versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+		versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+		versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+		versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+					      PTE_BLOCK_INNER_SHARE;
+		banks = banks + 1;
+	}
+}
+
 struct mm_region *mem_map = versal_mem_map;
 
 u64 get_page_table_size(void)
@@ -83,16 +108,27 @@ int reserve_mmu(void)
 }
 #endif
 
-#if defined(CONFIG_OF_BOARD)
-void *board_fdt_blob_setup(void)
+int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+		      u32 arg3, u32 *ret_payload)
 {
-	static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR;
+	struct pt_regs regs;
+
+	if (current_el() == 3)
+		return 0;
 
-	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
-		printf("DTB is not passed via %llx\n", (u64)fw_dtb);
-		return NULL;
+	regs.regs[0] = PM_SIP_SVC | api_id;
+	regs.regs[1] = ((u64)arg1 << 32) | arg0;
+	regs.regs[2] = ((u64)arg3 << 32) | arg2;
+
+	smc_call(&regs);
+
+	if (ret_payload) {
+		ret_payload[0] = (u32)regs.regs[0];
+		ret_payload[1] = upper_32_bits(regs.regs[0]);
+		ret_payload[2] = (u32)regs.regs[1];
+		ret_payload[3] = upper_32_bits(regs.regs[1]);
+		ret_payload[4] = (u32)regs.regs[2];
 	}
 
-	return fw_dtb;
+	return regs.regs[0];
 }
-#endif

+ 23 - 0
arch/arm/mach-versal/include/mach/hardware.h

@@ -51,3 +51,26 @@ struct rpu_regs {
 };
 
 #define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR)
+
+#define VERSAL_CRP_BASEADDR	0xF1260000
+
+struct crp_regs {
+	u32 reserved0[128];
+	u32 boot_mode_usr;
+};
+
+#define crp_base ((struct crp_regs *)VERSAL_CRP_BASEADDR)
+
+/* Bootmode setting values */
+#define BOOT_MODES_MASK	0x0000000F
+#define QSPI_MODE_24BIT	0x00000001
+#define QSPI_MODE_32BIT	0x00000002
+#define SD_MODE		0x00000003 /* sd 0 */
+#define SD_MODE1	0x00000005 /* sd 1 */
+#define EMMC_MODE	0x00000006
+#define USB_MODE	0x00000007
+#define OSPI_MODE	0x00000008
+#define SD1_LSHFT_MODE	0x0000000E /* SD1 Level shifter */
+#define JTAG_MODE	0x00000000
+#define BOOT_MODE_USE_ALT	0x100
+#define BOOT_MODE_ALT_SHIFT	12

+ 61 - 0
arch/arm/mach-versal/include/mach/sys_proto.h

@@ -8,4 +8,65 @@ enum {
 	TCM_SPLIT,
 };
 
+enum pm_api_id {
+	PM_GET_API_VERSION = 1,
+	PM_SET_CONFIGURATION,
+	PM_GET_NODE_STATUS,
+	PM_GET_OPERATING_CHARACTERISTIC,
+	PM_REGISTER_NOTIFIER,
+	PM_REQUEST_SUSPEND,
+	PM_SELF_SUSPEND,
+	PM_FORCE_POWERDOWN,
+	PM_ABORT_SUSPEND,
+	PM_REQUEST_WAKEUP,
+	PM_SET_WAKEUP_SOURCE,
+	PM_SYSTEM_SHUTDOWN,
+	PM_REQUEST_NODE,
+	PM_RELEASE_NODE,
+	PM_SET_REQUIREMENT,
+	PM_SET_MAX_LATENCY,
+	PM_RESET_ASSERT,
+	PM_RESET_GET_STATUS,
+	PM_MMIO_WRITE,
+	PM_MMIO_READ,
+	PM_PM_INIT_FINALIZE,
+	PM_FPGA_LOAD,
+	PM_FPGA_GET_STATUS,
+	PM_GET_CHIPID,
+	PM_SECURE_SHA = 26,
+	PM_SECURE_RSA,
+	PM_PINCTRL_REQUEST,
+	PM_PINCTRL_RELEASE,
+	PM_PINCTRL_GET_FUNCTION,
+	PM_PINCTRL_SET_FUNCTION,
+	PM_PINCTRL_CONFIG_PARAM_GET,
+	PM_PINCTRL_CONFIG_PARAM_SET,
+	PM_IOCTL,
+	PM_QUERY_DATA,
+	PM_CLOCK_ENABLE,
+	PM_CLOCK_DISABLE,
+	PM_CLOCK_GETSTATE,
+	PM_CLOCK_SETDIVIDER,
+	PM_CLOCK_GETDIVIDER,
+	PM_CLOCK_SETRATE,
+	PM_CLOCK_GETRATE,
+	PM_CLOCK_SETPARENT,
+	PM_CLOCK_GETPARENT,
+	PM_SECURE_IMAGE,
+	PM_FPGA_READ = 46,
+	PM_SECURE_AES,
+	PM_CLOCK_PLL_GETPARAM = 49,
+	PM_REGISTER_ACCESS = 52,
+	PM_EFUSE_ACCESS,
+	PM_FEATURE_CHECK = 63,
+	PM_API_MAX,
+};
+
+#define PM_SIP_SVC	0xC2000000
+#define PAYLOAD_ARG_CNT	4U
+
 void tcm_init(u8 mode);
+void mem_map_fill(void);
+
+int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+		      u32 arg3, u32 *ret_payload);

+ 0 - 4
arch/arm/mach-zynqmp/Makefile

@@ -8,7 +8,3 @@ obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
 obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
 obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED)	+= psu_spl_init.o
-
-ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
-obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o
-endif

+ 1 - 23
arch/arm/mach-zynqmp/cpu.c

@@ -9,6 +9,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
+#include <zynqmp_firmware.h>
 
 #define ZYNQ_SILICON_VER_MASK	0xF000
 #define ZYNQ_SILICON_VER_SHIFT	12
@@ -179,29 +180,6 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
 	return regs.regs[0];
 }
 
-unsigned int  __maybe_unused zynqmp_pmufw_version(void)
-{
-	int ret;
-	u32 ret_payload[PAYLOAD_ARG_CNT];
-	static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
-
-	/*
-	 * Get PMU version only once and later
-	 * just return stored values instead of
-	 * asking PMUFW again.
-	 */
-	if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
-		ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
-				 ret_payload);
-		pm_api_version = ret_payload[1];
-
-		if (ret)
-			panic("PMUFW is not found - Please load it!\n");
-	}
-
-	return pm_api_version;
-}
-
 static int zynqmp_mmio_rawwrite(const u32 address,
 		      const u32 mask,
 		      const u32 value)

+ 5 - 19
arch/arm/mach-zynqmp/include/mach/sys_proto.h

@@ -10,7 +10,6 @@
 #define PAYLOAD_ARG_CNT		5
 
 #define ZYNQMP_CSU_SILICON_VER_MASK	0xF
-#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD	0xC200002D
 #define KEY_PTR_LEN	32
 
 #define ZYNQMP_FPGA_BIT_AUTH_DDR	1
@@ -21,21 +20,6 @@
 
 #define ZYNQMP_FPGA_AUTH_DDR	1
 
-#define ZYNQMP_SIP_SVC_GET_API_VERSION		0xC2000001
-
-#define ZYNQMP_PM_VERSION_MAJOR		1
-#define ZYNQMP_PM_VERSION_MINOR		0
-#define ZYNQMP_PM_VERSION_MAJOR_SHIFT	16
-#define ZYNQMP_PM_VERSION_MINOR_MASK	0xFFFF
-
-#define ZYNQMP_PM_VERSION	\
-	((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
-				 ZYNQMP_PM_VERSION_MINOR)
-
-#define ZYNQMP_PM_VERSION_INVALID	~0
-
-#define PMUFW_V1_0	((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
-
 enum {
 	IDCODE,
 	VERSION,
@@ -54,12 +38,16 @@ enum {
 	TCM_SPLIT,
 };
 
+struct zynqmp_ipi_msg {
+	size_t len;
+	u32 *buf;
+};
+
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 unsigned int zynqmp_get_silicon_version(void);
 
 void handoff_setup(void);
 
-unsigned int zynqmp_pmufw_version(void);
 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
 int zynqmp_mmio_read(const u32 address, u32 *value);
 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
@@ -72,6 +60,4 @@ int chip_id(unsigned char id);
 void tcm_init(u8 mode);
 #endif
 
-void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
-
 #endif /* _ASM_ARCH_SYS_PROTO_H */

+ 0 - 112
arch/arm/mach-zynqmp/pmu_ipc.c

@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Inter-Processor Communication with the Platform Management Unit (PMU)
- * firmware.
- *
- * (C) Copyright 2019 Luca Ceresoli
- * Luca Ceresoli <luca@lucaceresoli.net>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-
-/* IPI bitmasks, register base and register offsets */
-#define IPI_BIT_MASK_APU      0x00001
-#define IPI_BIT_MASK_PMU0     0x10000
-#define IPI_REG_BASE_APU      0xFF300000
-#define IPI_REG_BASE_PMU0     0xFF330000
-#define IPI_REG_OFFSET_TRIG   0x00
-#define IPI_REG_OFFSET_OBR    0x04
-
-/* IPI mailbox buffer offsets */
-#define IPI_BUF_BASE_APU               0xFF990400
-#define IPI_BUF_OFFSET_TARGET_PMU      0x1C0
-#define IPI_BUF_OFFSET_REQ             0x00
-#define IPI_BUF_OFFSET_RESP            0x20
-
-#define PMUFW_PAYLOAD_ARG_CNT          8
-
-/* PMUFW commands */
-#define PMUFW_CMD_SET_CONFIGURATION    2
-
-static void pmu_ipc_send_request(const u32 *req, size_t req_len)
-{
-	u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
-			   IPI_BUF_OFFSET_TARGET_PMU +
-			   IPI_BUF_OFFSET_REQ);
-	size_t i;
-
-	for (i = 0; i < req_len; i++)
-		writel(req[i], &mbx[i]);
-}
-
-static void pmu_ipc_read_response(unsigned int *value, size_t count)
-{
-	u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
-			   IPI_BUF_OFFSET_TARGET_PMU +
-			   IPI_BUF_OFFSET_RESP);
-	size_t i;
-
-	for (i = 0; i < count; i++)
-		value[i] = readl(&mbx[i]);
-}
-
-/**
- * Send request to PMU and get the response.
- *
- * @req:        Request buffer. Byte 0 is the API ID, other bytes are optional
- *              parameters.
- * @req_len:    Request length in number of 32-bit words.
- * @res:        Response buffer. Byte 0 is the error code, other bytes are
- *              optional parameters. Optional, if @res_maxlen==0 the parameters
- *              will not be read.
- * @res_maxlen: Space allocated for the response in number of 32-bit words.
- *
- * @return Error code returned by the PMU (i.e. the first word of the response)
- */
-static int pmu_ipc_request(const u32 *req, size_t req_len,
-			   u32 *res, size_t res_maxlen)
-{
-	u32 status;
-
-	if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
-	    res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
-		return -EINVAL;
-
-	pmu_ipc_send_request(req, req_len);
-
-	/* Raise Inter-Processor Interrupt to PMU and wait for response */
-	writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG);
-	do {
-		status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR);
-	} while (status & IPI_BIT_MASK_PMU0);
-
-	pmu_ipc_read_response(res, res_maxlen);
-
-	return 0;
-}
-
-/**
- * Send a configuration object to the PMU firmware.
- *
- * @cfg_obj: Pointer to the configuration object
- * @size:    Size of @cfg_obj in bytes
- */
-void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
-{
-	const u32 request[] = {
-		PMUFW_CMD_SET_CONFIGURATION,
-		(u32)((u64)cfg_obj)
-	};
-	u32 response;
-	int err;
-
-	printf("Loading PMUFW cfg obj (%ld bytes)\n", size);
-
-	err = pmu_ipc_request(request,  ARRAY_SIZE(request), &response, 1);
-	if (err)
-		panic("Cannot load PMUFW configuration object (%d)\n", err);
-	if (response != 0)
-		panic("PMUFW returned 0x%08x status!\n", response);
-}

+ 8 - 0
arch/microblaze/Kconfig

@@ -20,6 +20,14 @@ config TARGET_MICROBLAZE_GENERIC
 
 endchoice
 
+config STACK_SIZE
+	hex "Define max stack size that can be used by u-boot"
+	default 0x200000
+	help
+	  Defines Max stack size that can be used by u-boot so that the
+	  initrd_high will be calculated as base stack pointer minus this
+	  stack size.
+
 source "board/xilinx/microblaze-generic/Kconfig"
 
 config SPL_LDSCRIPT

+ 4 - 0
arch/microblaze/include/asm/config.h

@@ -6,8 +6,12 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_LMB
+
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_NEEDS_MANUAL_RELOC
 #endif
 
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #endif

+ 88 - 48
arch/microblaze/lib/bootm.c

@@ -15,71 +15,111 @@
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
 
-int do_bootm_linux(int flag, int argc, char * const argv[],
-		   bootm_headers_t *images)
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
+{
+	ulong ret;
+
+	asm("addik %0, r1, 0" : "=r"(ret) : );
+	return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
 {
-	/* First parameter is mapped to $r5 for kernel boot args */
-	void	(*thekernel) (char *, ulong, ulong);
-	char	*commandline = env_get("bootargs");
-	ulong	rd_data_start, rd_data_end;
+	ulong sp, bank_end;
+	int bank;
 
 	/*
-	 * allow the PREP bootm subcommand, it is required for bootm to work
+	 * Booting a (Linux) kernel image
+	 *
+	 * Allocate space for command line and board info - the
+	 * address should be as high as possible within the reach of
+	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+	 * memory, which means far enough below the current stack
+	 * pointer.
 	 */
-	if (flag & BOOTM_STATE_OS_PREP)
-		return 0;
+	sp = get_sp();
+	debug("## Current stack ends at 0x%08lx ", sp);
 
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
-
-	int	ret;
+	/* adjust sp by 4K to be safe */
+	sp -= 4096;
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		if (sp < gd->bd->bi_dram[bank].start)
+			continue;
+		bank_end = gd->bd->bi_dram[bank].start +
+			gd->bd->bi_dram[bank].size;
+		if (sp >= bank_end)
+			continue;
+		lmb_reserve(lmb, sp, bank_end - sp);
+		break;
+	}
+}
 
-	char	*of_flat_tree = NULL;
-#if defined(CONFIG_OF_LIBFDT)
-	/* did generic code already find a device tree? */
-	if (images->ft_len)
-		of_flat_tree = images->ft_addr;
-#endif
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+	void (*thekernel)(char *cmdline, ulong rd, ulong dt);
+	ulong dt = (ulong)images->ft_addr;
+	ulong rd_start = images->initrd_start;
+	ulong cmdline = images->cmdline_start;
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
 
 	thekernel = (void (*)(char *, ulong, ulong))images->ep;
 
-	/* find ramdisk */
-	ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_MICROBLAZE,
-			&rd_data_start, &rd_data_end);
-	if (ret)
-		return 1;
-
-	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
-	if (!of_flat_tree && argc > 1)
-		of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
-
-	/* fixup the initrd now that we know where it should be */
-	if (images->rd_start && images->rd_end && of_flat_tree) {
-		ret = fdt_initrd(of_flat_tree, images->rd_start,
-				 images->rd_end);
-		if (ret)
-			return 1;
-	}
-
 #ifdef DEBUG
 	printf("## Transferring control to Linux (at address 0x%08lx) ",
 	       (ulong)thekernel);
-	printf("ramdisk 0x%08lx, FDT 0x%08lx...\n",
-	       rd_data_start, (ulong) of_flat_tree);
+	printf("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n",
+	       cmdline, rd_start, dt);
 #endif
 
 #ifdef XILINX_USE_DCACHE
 	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
 #endif
-	/*
-	 * Linux Kernel Parameters (passing device tree):
-	 * r5: pointer to command line
-	 * r6: pointer to ramdisk
-	 * r7: pointer to the fdt, followed by the board info data
-	 */
-	thekernel(commandline, rd_data_start, (ulong)of_flat_tree);
-	/* does not return */
 
+	if (!fake) {
+		/*
+		 * Linux Kernel Parameters (passing device tree):
+		 * r5: pointer to command line
+		 * r6: pointer to ramdisk
+		 * r7: pointer to the fdt, followed by the board info data
+		 */
+		thekernel((char *)cmdline, rd_start, dt);
+		/* does not return */
+	}
+}
+
+static void boot_prep_linux(bootm_headers_t *images)
+{
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+		printf("using: FDT\n");
+		if (image_setup_linux(images)) {
+			printf("FDT creation failed! hanging...");
+			hang();
+		}
+	}
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+		   bootm_headers_t *images)
+{
+	images->cmdline_start = (ulong)env_get("bootargs");
+
+	/* cmdline init is the part of 'prep' and nothing to do for 'bdt' */
+	if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+		return -1;
+
+	if (flag & BOOTM_STATE_OS_PREP) {
+		boot_prep_linux(images);
+		return 0;
+	}
+
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+		boot_jump_linux(images, flag);
+		return 0;
+	}
+
+	boot_prep_linux(images);
+	boot_jump_linux(images, flag);
 	return 1;
 }

+ 8 - 0
board/xilinx/Kconfig

@@ -39,3 +39,11 @@ config XILINX_PS_INIT_FILE
 	     before the build.
 
 endif
+
+config XILINX_OF_BOARD_DTB_ADDR
+	hex
+	default 0x1000 if ARCH_VERSAL
+	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
+	depends on OF_BOARD
+	help
+	  Offset in the memory where the board configuration DTB is placed.

+ 10 - 0
board/xilinx/bootscripts/qspiboot.cmd

@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d qspiboot.cmd boot.scr
+#
+# It requires a list of environment variables to be defined before load:
+# fdt_addr, fdt_offset, fdt_size, kernel_addr, kernel_offset, kernel_size
+#
+sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && sf read $kernel_addr $kernel_offset $kernel_size && booti $kernel_addr - $fdt_addr

+ 10 - 0
board/xilinx/bootscripts/sdboot.cmd

@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d sdboot.cmd boot.scr
+#
+# It requires a list of environment variables used below to be defined
+# before load
+#
+mmc dev $devnum && mmcinfo && run uenvboot || run sdroot$devnum;load mmc $devnum:$partid $fdt_addr system.dtb && load mmc $devnum:$partid $kernel_addr Image && booti $kernel_addr - $fdt_addr

+ 14 - 0
board/xilinx/common/board.c

@@ -36,3 +36,17 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 
 	return ret;
 }
+
+#if defined(CONFIG_OF_BOARD)
+void *board_fdt_blob_setup(void)
+{
+	static void *fw_dtb = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
+
+	if (fdt_magic(fw_dtb) != FDT_MAGIC) {
+		printf("DTB is not passed via %p\n", fw_dtb);
+		return NULL;
+	}
+
+	return fw_dtb;
+}
+#endif

+ 19 - 9
board/xilinx/microblaze-generic/microblaze-generic.c

@@ -12,20 +12,12 @@
 
 #include <common.h>
 #include <config.h>
-#include <dm.h>
 #include <dm/lists.h>
 #include <fdtdec.h>
-#include <asm/processor.h>
-#include <asm/microblaze_intc.h>
-#include <asm/asm.h>
-#include <asm/gpio.h>
-#include <dm/uclass.h>
-#include <wdt.h>
+#include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-ulong ram_base;
-
 int dram_init_banksize(void)
 {
 	return fdtdec_setup_memory_banksize();
@@ -41,6 +33,8 @@ int dram_init(void)
 
 int board_late_init(void)
 {
+	ulong max_size, lowmem_size;
+
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
 	int ret;
 
@@ -49,5 +43,21 @@ int board_late_init(void)
 	if (ret)
 		printf("Warning: No reset driver: ret=%d\n", ret);
 #endif
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	max_size = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	max_size = round_down(max_size, SZ_16M);
+
+	/* Linux default LOWMEM_SIZE is 0x30000000 = 768MB */
+	lowmem_size = gd->ram_base + 768 * 1024 * 1024;
+
+	env_set_addr("initrd_high", (void *)min_t(ulong, max_size,
+						  lowmem_size));
+	env_set_addr("fdt_high", (void *)min_t(ulong, max_size, lowmem_size));
+
 	return 0;
 }

+ 1 - 0
board/xilinx/versal/Makefile

@@ -5,3 +5,4 @@
 #
 
 obj-y	:= board.o
+obj-y	+= ../common/board.o

+ 139 - 1
board/xilinx/versal/board.c

@@ -9,13 +9,27 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <versalpl.h>
+#include <linux/sizes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+#endif
+
 int board_init(void)
 {
 	printf("EL Level:\tEL%d\n", current_el());
 
+#if defined(CONFIG_FPGA_VERSALPL)
+	fpga_init();
+	fpga_add(fpga_xilinx, &versalpl);
+#endif
+
 	return 0;
 }
 
@@ -65,9 +79,133 @@ int board_early_init_r(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	u32 reg = 0;
+	u8 bootmode;
+	struct udevice *dev;
+	int bootseq = -1;
+	int bootseq_len = 0;
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+	ulong initrd_hi;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	reg = readl(&crp_base->boot_mode_usr);
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	puts("Bootmode: ");
+	switch (bootmode) {
+	case USB_MODE:
+		puts("USB_MODE\n");
+		mode = "dfu_usb";
+		break;
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		mode = "jtag pxe dhcp";
+		break;
+	case QSPI_MODE_24BIT:
+		puts("QSPI_MODE_24\n");
+		mode = "xspi0";
+		break;
+	case QSPI_MODE_32BIT:
+		puts("QSPI_MODE_32\n");
+		mode = "xspi0";
+		break;
+	case OSPI_MODE:
+		puts("OSPI_MODE\n");
+		mode = "xspi0";
+		break;
+	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		mode = "mmc0";
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1040000", &dev)) {
+			puts("Boot from SD0 but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
+
+		mode = "mmc";
+		bootseq = dev->seq;
+		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		/* fall through */
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1050000", &dev)) {
+			puts("Boot from SD1 but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
+
+		mode = "mmc";
+		bootseq = dev->seq;
+		break;
+	default:
+		mode = "";
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	if (bootseq >= 0) {
+		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+		debug("Bootseq len: %x\n", bootseq_len);
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+			     bootseq_len);
+	if (!new_targets)
+		return -ENOMEM;
+
+	if (bootseq >= 0)
+		sprintf(new_targets, "%s%x %s", mode, bootseq,
+			env_targets ? env_targets : "");
+	else
+		sprintf(new_targets, "%s %s", mode,
+			env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
+	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	initrd_hi = round_down(initrd_hi, SZ_16M);
+	env_set_addr("initrd_high", (void *)initrd_hi);
+
+	return 0;
+}
+
 int dram_init_banksize(void)
 {
-	fdtdec_setup_memory_banksize();
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	mem_map_fill();
 
 	return 0;
 }

+ 1 - 1
board/xilinx/zynq/board.c

@@ -52,7 +52,7 @@ int board_late_init(void)
 		env_set("modeboot", "norboot");
 		break;
 	case ZYNQ_BM_SD:
-		mode = "mmc";
+		mode = "mmc0";
 		env_set("modeboot", "sdboot");
 		break;
 	case ZYNQ_BM_JTAG:

+ 1 - 0
board/xilinx/zynqmp/cmds.c

@@ -7,6 +7,7 @@
 #include <common.h>
 #include <env.h>
 #include <malloc.h>
+#include <zynqmp_firmware.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>

+ 1 - 0
board/xilinx/zynqmp/zynqmp-a2197-g-revA

@@ -0,0 +1 @@
+zynqmp-a2197-revA

+ 1 - 0
board/xilinx/zynqmp/zynqmp-a2197-m-revA

@@ -0,0 +1 @@
+zynqmp-a2197-revA

+ 1 - 0
board/xilinx/zynqmp/zynqmp-a2197-p-revA

@@ -0,0 +1 @@
+zynqmp-a2197-revA

+ 1171 - 0
board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c

@@ -0,0 +1,1171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
+	psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010B02U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1310U);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0510U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0129A4A4U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180204, 0x00FFE000U, 0x00000000U);
+	psu_mask_write(0xFF180208, 0xFFFFE3FCU, 0x00B02240U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U);
+	psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
+		      int d_lfhf, int d_cp, int d_res)
+{
+	unsigned int pll_ctrl_regval;
+	unsigned int pll_status_regval;
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 16);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
+	pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
+	pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+	pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_status_regval = 0x00000000;
+	while ((pll_status_regval & 0x00000002U) != 0x00000002U)
+		pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+	pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	int cur_PLLCR0;
+
+	cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL0PLLCR0;
+
+	cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL1PLLCR0;
+
+	cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL2PLLCR0;
+
+	cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL3PLLCR0;
+
+	cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL4PLLCR0;
+
+	cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SLBPLLCR0;
+
+	cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	Xil_Out32(0xFD080068, 0x02120000);
+	Xil_Out32(0xFD081404, 0x02120000);
+	Xil_Out32(0xFD081444, 0x02120000);
+	Xil_Out32(0xFD081484, 0x02120000);
+	Xil_Out32(0xFD0814C4, 0x02120000);
+	Xil_Out32(0xFD081504, 0x02120000);
+	Xil_Out32(0xFD0817C4, 0x02120000);
+	int cur_fbdiv;
+
+	cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
+	dpll_prog(48, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return (0);
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000331U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000B36U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000C21U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000E19U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00001616U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD070010U, 0x80000010U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	Xil_Out32(0xFD080068, cur_PLLCR0);
+	Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
+	Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
+	Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
+	Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
+	Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
+	Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	dpll_prog(cur_fbdiv, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
+	prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0014FE01);
+
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x8000007E)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x000091C7U);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80008FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return (0);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
+	Xil_Out32(0xFD070180U, 0x02160010U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+	for (int tp = 0; tp < 4000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
+	prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
+	prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
+	prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
+	prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0, count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}

+ 22 - 13
board/xilinx/zynqmp/zynqmp.c

@@ -21,7 +21,9 @@
 #include <usb.h>
 #include <dwc3-uboot.h>
 #include <zynqmppl.h>
+#include <zynqmp_firmware.h>
 #include <g_dnl.h>
+#include <linux/sizes.h>
 
 #include "pm_cfg_obj.h"
 
@@ -173,6 +175,14 @@ static const struct {
 		.id = 0x66,
 		.name = "39dr",
 	},
+	{
+		.id = 0x7b,
+		.name = "48dr",
+	},
+	{
+		.id = 0x7e,
+		.name = "49dr",
+	},
 };
 #endif
 
@@ -308,18 +318,6 @@ static char *zynqmp_get_silicon_idcode_name(void)
 int board_early_init_f(void)
 {
 	int ret = 0;
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
-	u32 pm_api_version;
-
-	pm_api_version = zynqmp_pmufw_version();
-	printf("PMUFW:\tv%d.%d\n",
-	       pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
-	       pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
-
-	if (pm_api_version < ZYNQMP_PM_VERSION)
-		panic("PMUFW version error. Expected: v%d.%d\n",
-		      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
-#endif
 
 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 	ret = psu_init();
@@ -330,6 +328,12 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct udevice *dev;
+
+	uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
+	if (!dev)
+		panic("PMU Firmware device not found - Enable it");
+
 #if defined(CONFIG_SPL_BUILD)
 	/* Check *at build time* if the filename is an non-empty string */
 	if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
@@ -530,6 +534,7 @@ int board_late_init(void)
 	char *new_targets;
 	char *env_targets;
 	int ret;
+	ulong initrd_hi;
 
 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 	usb_ether_init();
@@ -562,7 +567,7 @@ int board_late_init(void)
 		break;
 	case JTAG_MODE:
 		puts("JTAG_MODE\n");
-		mode = "pxe dhcp";
+		mode = "jtag pxe dhcp";
 		env_set("modeboot", "jtagboot");
 		break;
 	case QSPI_MODE_24BIT:
@@ -647,6 +652,10 @@ int board_late_init(void)
 
 	env_set("boot_targets", new_targets);
 
+	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	initrd_hi = round_down(initrd_hi, SZ_16M);
+	env_set_addr("initrd_high", (void *)initrd_hi);
+
 	reset_reason();
 
 	return 0;

+ 2 - 0
cmd/Kconfig

@@ -48,6 +48,8 @@ config SYS_LONGHELP
 
 config SYS_PROMPT
 	string "Shell prompt"
+	default "Zynq> " if ARCH_ZYNQ
+	default "ZynqMP> " if ARCH_ZYNQMP
 	default "=> "
 	help
 	  This string is displayed in the command line to the left of the

+ 3 - 2
common/image.c

@@ -583,7 +583,7 @@ ulong env_get_bootm_low(void)
 
 #if defined(CONFIG_SYS_SDRAM_BASE)
 	return CONFIG_SYS_SDRAM_BASE;
-#elif defined(CONFIG_ARM)
+#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
 	return gd->bd->bi_dram[0].start;
 #else
 	return 0;
@@ -600,7 +600,8 @@ phys_size_t env_get_bootm_size(void)
 		return tmp;
 	}
 
-#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS)
+#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
+     defined(CONFIG_NR_DRAM_BANKS)
 	start = gd->bd->bi_dram[0].start;
 	size = gd->bd->bi_dram[0].size;
 #else

+ 1 - 0
common/spl/Kconfig

@@ -139,6 +139,7 @@ config SPL_TEXT_BASE
 	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
 	default 0x20060 if MACH_SUN50I_H6
 	default 0x00060 if ARCH_SUNXI
+	default 0xfffc0000 if ARCH_ZYNQMP
 	default 0x0
 	help
 	  The address in memory that SPL will be running from.

+ 0 - 2
configs/avnet_ultra96_rev1_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_BOOTMENU=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_BIND=y

+ 0 - 2
configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig

@@ -9,7 +9,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -17,7 +16,6 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_BOOTDELAY=0
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADP=y

+ 2 - 0
configs/microblaze-generic_defconfig

@@ -37,10 +37,12 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_JFFS2=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_SPL_DM=y
 CONFIG_XILINX_GPIO=y

+ 0 - 1
configs/syzygy_hub_defconfig

@@ -19,7 +19,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y

+ 3 - 0
configs/xilinx_versal_mini_defconfig

@@ -8,8 +8,11 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MALLOC_LEN=0x2000
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_COUNTER_FREQUENCY=2720000
+# CONFIG_PSCI_RESET is not set
+# CONFIG_EXPERT is not set
 # CONFIG_LEGACY_IMAGE_FORMAT is not set
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_CMDLINE_EDITING is not set

+ 4 - 0
configs/xilinx_versal_mini_emmc0_defconfig

@@ -7,7 +7,10 @@ CONFIG_ENV_SIZE=0x80
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MALLOC_LEN=0x80000
 CONFIG_COUNTER_FREQUENCY=2720000
+# CONFIG_PSCI_RESET is not set
+# CONFIG_EXPERT is not set
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_CMDLINE_EDITING is not set
@@ -49,4 +52,5 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0"
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_FAT_WRITE=y
 # CONFIG_EFI_LOADER is not set

+ 4 - 0
configs/xilinx_versal_mini_emmc1_defconfig

@@ -7,7 +7,10 @@ CONFIG_ENV_SIZE=0x80
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MALLOC_LEN=0x80000
 CONFIG_COUNTER_FREQUENCY=2720000
+# CONFIG_PSCI_RESET is not set
+# CONFIG_EXPERT is not set
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_CMDLINE_EDITING is not set
@@ -49,4 +52,5 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1"
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_FAT_WRITE=y
 # CONFIG_EFI_LOADER is not set

+ 2 - 5
configs/xilinx_versal_virt_defconfig

@@ -2,16 +2,14 @@ CONFIG_ARM=y
 CONFIG_ARCH_VERSAL=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=0
 CONFIG_COUNTER_FREQUENCY=62500000
-CONFIG_DEBUG_UART=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 CONFIG_BOOTDELAY=-1
 CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_BOARD_LATE_INIT is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_HUSH_PARSER=y
@@ -44,6 +42,7 @@ CONFIG_OF_BOARD=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_IP_DEFRAG=y
 CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_CLK_VERSAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
@@ -66,8 +65,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y

+ 115 - 0
configs/xilinx_zynqmp_a2197_g_revA_defconfig

@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-g-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

+ 115 - 0
configs/xilinx_zynqmp_a2197_m_revA_defconfig

@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-m-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

+ 116 - 0
configs/xilinx_zynqmp_a2197_p_revA_defconfig

@@ -0,0 +1,116 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-p-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

+ 117 - 0
configs/xilinx_zynqmp_a2197_revA_defconfig

@@ -0,0 +1,117 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA"
+CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA zynqmp-a2197-m-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

+ 0 - 1
configs/xilinx_zynqmp_mini_defconfig

@@ -13,7 +13,6 @@ CONFIG_ZYNQMP_PSU_INIT_ENABLED=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 # CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set

+ 0 - 2
configs/xilinx_zynqmp_mini_emmc0_defconfig

@@ -7,7 +7,6 @@ CONFIG_ENV_SIZE=0x80
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 # CONFIG_CMD_ZYNQMP is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_FIT=y
 CONFIG_SUPPORT_RAW_INITRD=y
 # CONFIG_BOARD_LATE_INIT is not set
@@ -15,7 +14,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set

+ 0 - 2
configs/xilinx_zynqmp_mini_emmc1_defconfig

@@ -7,7 +7,6 @@ CONFIG_ENV_SIZE=0x80
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 # CONFIG_CMD_ZYNQMP is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_FIT=y
 CONFIG_SUPPORT_RAW_INITRD=y
 # CONFIG_BOARD_LATE_INIT is not set
@@ -15,7 +14,6 @@ CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set

+ 1 - 1
configs/xilinx_zynqmp_mini_nand_defconfig

@@ -14,7 +14,6 @@ CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 # CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -49,4 +48,5 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
 # CONFIG_MMC is not set
 CONFIG_NAND=y
 CONFIG_NAND_ARASAN=y
+CONFIG_SYS_NAND_MAX_CHIPS=2
 # CONFIG_EFI_LOADER is not set

+ 0 - 2
configs/xilinx_zynqmp_mini_qspi_defconfig

@@ -10,7 +10,6 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 CONFIG_ZYNQMP_NO_DDR=y
 # CONFIG_PSCI_RESET is not set
 # CONFIG_CMD_ZYNQMP is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 # CONFIG_EXPERT is not set
 # CONFIG_LEGACY_IMAGE_FORMAT is not set
 # CONFIG_BOARD_LATE_INIT is not set
@@ -18,7 +17,6 @@ CONFIG_SPL_TEXT_BASE=0xfffc0000
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 # CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set

+ 108 - 0
configs/xilinx_zynqmp_virt_defconfig

@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

+ 0 - 2
configs/xilinx_zynqmp_zc1232_revA_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 # CONFIG_SPL_FS_FAT is not set
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 2
configs/xilinx_zynqmp_zc1254_revA_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 # CONFIG_SPL_FS_FAT is not set
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 2
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig

@@ -9,7 +9,6 @@ CONFIG_ZYNQMP_USB=y
 CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -20,7 +19,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y

+ 0 - 2
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig

@@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -20,7 +19,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y

+ 0 - 2
configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y

+ 0 - 2
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig

@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -17,7 +16,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_CLK=y

+ 0 - 2
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig

@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -17,7 +16,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_CLK=y

+ 0 - 2
configs/xilinx_zynqmp_zcu100_revC_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_BOOTMENU=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_BIND=y

+ 1 - 2
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig

@@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -21,7 +20,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
@@ -59,6 +57,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
 CONFIG_XILINX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y

+ 1 - 2
configs/xilinx_zynqmp_zcu102_revA_defconfig

@@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -21,7 +20,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
@@ -59,6 +57,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
 CONFIG_XILINX_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y

+ 1 - 2
configs/xilinx_zynqmp_zcu102_revB_defconfig

@@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -21,7 +20,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
@@ -59,6 +57,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
 CONFIG_XILINX_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y

+ 0 - 2
configs/xilinx_zynqmp_zcu104_revA_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y

+ 3 - 2
configs/xilinx_zynqmp_zcu104_revC_defconfig

@@ -5,10 +5,11 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -17,8 +18,8 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y

+ 0 - 2
configs/xilinx_zynqmp_zcu106_revA_defconfig

@@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -20,7 +19,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y

+ 0 - 2
configs/xilinx_zynqmp_zcu111_revA_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_ZYNQMP_USB=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y

+ 0 - 2
configs/xilinx_zynqmp_zcu1275_revA_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 # CONFIG_SPL_FS_FAT is not set
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 2
configs/xilinx_zynqmp_zcu1275_revB_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 # CONFIG_SPL_FS_FAT is not set
 # CONFIG_SPL_LIBDISK_SUPPORT is not set
 CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_cc108_defconfig

@@ -18,7 +18,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y

+ 0 - 1
configs/zynq_cse_nand_defconfig

@@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 # CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set

+ 0 - 1
configs/zynq_cse_nor_defconfig

@@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R=y
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 # CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set

+ 0 - 1
configs/zynq_cse_qspi_defconfig

@@ -26,7 +26,6 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
 # CONFIG_CMDLINE_EDITING is not set
 # CONFIG_AUTO_COMPLETE is not set
 # CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set

+ 0 - 1
configs/zynq_dlc20_rev1_0_defconfig

@@ -21,7 +21,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_microzed_defconfig

@@ -16,7 +16,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_minized_defconfig

@@ -16,7 +16,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_picozed_defconfig

@@ -10,7 +10,6 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 79 - 0
configs/zynq_virt_defconfig

@@ -0,0 +1,79 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CUSTOM_LDSCRIPT=y
+CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_THOR=y

+ 0 - 1
configs/zynq_z_turn_defconfig

@@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_zc702_defconfig

@@ -20,7 +20,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y

+ 0 - 1
configs/zynq_zc706_defconfig

@@ -23,7 +23,6 @@ CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_zc770_xm010_defconfig

@@ -20,7 +20,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y

+ 0 - 1
configs/zynq_zc770_xm011_defconfig

@@ -19,7 +19,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y

+ 0 - 1
configs/zynq_zc770_xm011_x16_defconfig

@@ -19,7 +19,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y

+ 0 - 1
configs/zynq_zc770_xm012_defconfig

@@ -16,7 +16,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_IMLS=y
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y

+ 0 - 1
configs/zynq_zc770_xm013_defconfig

@@ -18,7 +18,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_FPGA_LOADBP=y
 CONFIG_CMD_FPGA_LOADFS=y

+ 0 - 1
configs/zynq_zed_defconfig

@@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_zybo_defconfig

@@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 0 - 1
configs/zynq_zybo_z7_defconfig

@@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_THOR_DOWNLOAD=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set

+ 1 - 0
doc/board/xilinx/index.rst

@@ -6,4 +6,5 @@ Xilinx
 .. toctree::
    :maxdepth: 2
 
+   xilinx
    zynq

+ 38 - 0
doc/board/xilinx/xilinx.rst

@@ -0,0 +1,38 @@
+.. SPDX-License-Identifier: GPL-2.0+
+..  (C) Copyright 2019 Xilinx, Inc.
+
+U-Boot device tree bindings
+----------------------------
+
+All the device tree bindings used in U-Boot are specified in Linux
+kernel. Please refer dt bindings from below specified paths in Linux
+kernel.
+
+* ata
+	- Documentation/devicetree/bindings/ata/ahci-ceva.txt
+* gpio
+	- Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
+	- Documentation/devicetree/bindings/gpio/gpio-zynq.txt
+* i2c
+	- Documentation/devicetree/bindings/i2c/i2c-xiic.txt
+	- Documentation/devicetree/bindings/i2c/i2c-cadence.txt
+* mmc
+	- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+* net
+	- Documentation/devicetree/bindings/net/macb.txt
+	- Documentation/devicetree/bindings/net/xilinx_axienet.txt
+	- Documentation/devicetree/bindings/net/xilinx_emaclite.txt
+* serial
+	- Documentation/devicetree/bindings/serial/cdns,uart.txt
+	- Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt
+* spi
+	- Documentation/devicetree/bindings/spi/spi-cadence.txt
+	- Documentation/devicetree/bindings/spi/spi-xilinx.txt
+	- Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
+	- Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
+* usb
+	- Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
+	- Documentation/devicetree/bindings/usb/dwc3.txt
+	- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
+* wdt
+	- Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt

+ 9 - 0
drivers/clk/Kconfig

@@ -95,6 +95,14 @@ config CLK_HSDK
 	help
 	  Enable this to support the cgu clocks on Synopsys ARC HSDK
 
+config CLK_VERSAL
+	bool "Enable clock driver support for Versal"
+	depends on ARCH_VERSAL
+	select ZYNQMP_FIRMWARE
+	help
+	  This clock driver adds support for clock realted settings for
+	  Versal platform.
+
 config CLK_VEXPRESS_OSC
 	bool "Enable driver for Arm Versatile Express OSC clock generators"
 	depends on CLK && VEXPRESS_CONFIG
@@ -113,6 +121,7 @@ config CLK_ZYNQ
 config CLK_ZYNQMP
 	bool "Enable clock driver support for ZynqMP"
 	depends on ARCH_ZYNQMP
+	select ZYNQMP_FIRMWARE
 	help
 	  This clock driver adds support for clock realted settings for
 	  ZynqMP platform.

+ 1 - 0
drivers/clk/Makefile

@@ -43,3 +43,4 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
 obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
 obj-$(CONFIG_STM32H7) += clk_stm32h7.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
+obj-$(CONFIG_CLK_VERSAL) += clk_versal.o

+ 746 - 0
drivers/clk/clk_versal.c

@@ -0,0 +1,746 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/arch/sys_proto.h>
+
+#define MAX_PARENT			100
+#define MAX_NODES			6
+#define MAX_NAME_LEN			50
+
+#define CLK_TYPE_SHIFT			2
+
+#define PM_API_PAYLOAD_LEN		3
+
+#define NA_PARENT			0xFFFFFFFF
+#define DUMMY_PARENT			0xFFFFFFFE
+
+#define CLK_TYPE_FIELD_LEN		4
+#define CLK_TOPOLOGY_NODE_OFFSET	16
+#define NODES_PER_RESP			3
+
+#define CLK_TYPE_FIELD_MASK		0xF
+#define CLK_FLAG_FIELD_MASK		GENMASK(21, 8)
+#define CLK_TYPE_FLAG_FIELD_MASK	GENMASK(31, 24)
+#define CLK_TYPE_FLAG2_FIELD_MASK	GENMASK(7, 4)
+#define CLK_TYPE_FLAG_BITS		8
+
+#define CLK_PARENTS_ID_LEN		16
+#define CLK_PARENTS_ID_MASK		0xFFFF
+
+#define END_OF_TOPOLOGY_NODE		1
+#define END_OF_PARENTS			1
+
+#define CLK_VALID_MASK			0x1
+#define NODE_CLASS_SHIFT		26U
+#define NODE_SUBCLASS_SHIFT		20U
+#define NODE_TYPE_SHIFT			14U
+#define NODE_INDEX_SHIFT		0U
+
+#define CLK_GET_NAME_RESP_LEN		16
+#define CLK_GET_TOPOLOGY_RESP_WORDS	3
+#define CLK_GET_PARENTS_RESP_WORDS	3
+#define CLK_GET_ATTR_RESP_WORDS		1
+
+#define NODE_SUBCLASS_CLOCK_PLL	1
+#define NODE_SUBCLASS_CLOCK_OUT	2
+#define NODE_SUBCLASS_CLOCK_REF	3
+
+#define NODE_CLASS_CLOCK	2
+#define NODE_CLASS_MASK		0x3F
+
+#define CLOCK_NODE_TYPE_MUX	1
+#define CLOCK_NODE_TYPE_DIV	4
+#define CLOCK_NODE_TYPE_GATE	6
+
+enum pm_query_id {
+	PM_QID_INVALID,
+	PM_QID_CLOCK_GET_NAME,
+	PM_QID_CLOCK_GET_TOPOLOGY,
+	PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
+	PM_QID_CLOCK_GET_PARENTS,
+	PM_QID_CLOCK_GET_ATTRIBUTES,
+	PM_QID_PINCTRL_GET_NUM_PINS,
+	PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
+	PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
+	PM_QID_PINCTRL_GET_FUNCTION_NAME,
+	PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
+	PM_QID_PINCTRL_GET_PIN_GROUPS,
+	PM_QID_CLOCK_GET_NUM_CLOCKS,
+	PM_QID_CLOCK_GET_MAX_DIVISOR,
+};
+
+enum clk_type {
+	CLK_TYPE_OUTPUT,
+	CLK_TYPE_EXTERNAL,
+};
+
+struct clock_parent {
+	char name[MAX_NAME_LEN];
+	int id;
+	u32 flag;
+};
+
+struct clock_topology {
+	u32 type;
+	u32 flag;
+	u32 type_flag;
+};
+
+struct versal_clock {
+	char clk_name[MAX_NAME_LEN];
+	u32 valid;
+	enum clk_type type;
+	struct clock_topology node[MAX_NODES];
+	u32 num_nodes;
+	struct clock_parent parent[MAX_PARENT];
+	u32 num_parents;
+	u32 clk_id;
+};
+
+struct versal_clk_priv {
+	struct versal_clock *clk;
+};
+
+static ulong alt_ref_clk;
+static ulong pl_alt_ref_clk;
+static ulong ref_clk;
+
+struct versal_pm_query_data {
+	u32 qid;
+	u32 arg1;
+	u32 arg2;
+	u32 arg3;
+};
+
+static struct versal_clock *clock;
+static unsigned int clock_max_idx;
+
+#define PM_QUERY_DATA	35
+
+static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA;
+	regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid;
+	regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2;
+
+	smc_call(&regs);
+
+	if (ret_payload) {
+		ret_payload[0] = (u32)regs.regs[0];
+		ret_payload[1] = upper_32_bits(regs.regs[0]);
+		ret_payload[2] = (u32)regs.regs[1];
+		ret_payload[3] = upper_32_bits(regs.regs[1]);
+		ret_payload[4] = (u32)regs.regs[2];
+	}
+
+	return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0];
+}
+
+static inline int versal_is_valid_clock(u32 clk_id)
+{
+	if (clk_id >= clock_max_idx)
+		return -ENODEV;
+
+	return clock[clk_id].valid;
+}
+
+static int versal_get_clock_name(u32 clk_id, char *clk_name)
+{
+	int ret;
+
+	ret = versal_is_valid_clock(clk_id);
+	if (ret == 1) {
+		strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
+		return 0;
+	}
+
+	return ret == 0 ? -EINVAL : ret;
+}
+
+static int versal_get_clock_type(u32 clk_id, u32 *type)
+{
+	int ret;
+
+	ret = versal_is_valid_clock(clk_id);
+	if (ret == 1) {
+		*type = clock[clk_id].type;
+		return 0;
+	}
+
+	return ret == 0 ? -EINVAL : ret;
+}
+
+static int versal_pm_clock_get_num_clocks(u32 *nclocks)
+{
+	struct versal_pm_query_data qdata = {0};
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
+
+	ret = versal_pm_query(qdata, ret_payload);
+	*nclocks = ret_payload[1];
+
+	return ret;
+}
+
+static int versal_pm_clock_get_name(u32 clock_id, char *name)
+{
+	struct versal_pm_query_data qdata = {0};
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	qdata.qid = PM_QID_CLOCK_GET_NAME;
+	qdata.arg1 = clock_id;
+
+	ret = versal_pm_query(qdata, ret_payload);
+	if (ret)
+		return ret;
+	memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
+
+	return 0;
+}
+
+static int versal_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
+{
+	struct versal_pm_query_data qdata = {0};
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
+	qdata.arg1 = clock_id;
+	qdata.arg2 = index;
+
+	ret = versal_pm_query(qdata, ret_payload);
+	memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
+
+	return ret;
+}
+
+static int versal_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
+{
+	struct versal_pm_query_data qdata = {0};
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	qdata.qid = PM_QID_CLOCK_GET_PARENTS;
+	qdata.arg1 = clock_id;
+	qdata.arg2 = index;
+
+	ret = versal_pm_query(qdata, ret_payload);
+	memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
+
+	return ret;
+}
+
+static int versal_pm_clock_get_attributes(u32 clock_id, u32 *attr)
+{
+	struct versal_pm_query_data qdata = {0};
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
+	qdata.arg1 = clock_id;
+
+	ret = versal_pm_query(qdata, ret_payload);
+	memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
+
+	return ret;
+}
+
+static int __versal_clock_get_topology(struct clock_topology *topology,
+				       u32 *data, u32 *nnodes)
+{
+	int i;
+
+	for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
+		if (!(data[i] & CLK_TYPE_FIELD_MASK))
+			return END_OF_TOPOLOGY_NODE;
+		topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
+		topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
+						   data[i]);
+		topology[*nnodes].type_flag =
+				FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
+		topology[*nnodes].type_flag |=
+			FIELD_GET(CLK_TYPE_FLAG2_FIELD_MASK, data[i]) <<
+			CLK_TYPE_FLAG_BITS;
+		debug("topology type:0x%x, flag:0x%x, type_flag:0x%x\n",
+		      topology[*nnodes].type, topology[*nnodes].flag,
+		      topology[*nnodes].type_flag);
+		(*nnodes)++;
+	}
+
+	return 0;
+}
+
+static int versal_clock_get_topology(u32 clk_id,
+				     struct clock_topology *topology,
+				     u32 *num_nodes)
+{
+	int j, ret;
+	u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
+
+	*num_nodes = 0;
+	for (j = 0; j <= MAX_NODES; j += 3) {
+		ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j,
+						   pm_resp);
+		if (ret)
+			return ret;
+		ret = __versal_clock_get_topology(topology, pm_resp, num_nodes);
+		if (ret == END_OF_TOPOLOGY_NODE)
+			return 0;
+	}
+
+	return 0;
+}
+
+static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data,
+				      u32 *nparent)
+{
+	int i;
+	struct clock_parent *parent;
+
+	for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
+		if (data[i] == NA_PARENT)
+			return END_OF_PARENTS;
+
+		parent = &parents[i];
+		parent->id = data[i] & CLK_PARENTS_ID_MASK;
+		if (data[i] == DUMMY_PARENT) {
+			strcpy(parent->name, "dummy_name");
+			parent->flag = 0;
+		} else {
+			parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
+			if (versal_get_clock_name(parent->id, parent->name))
+				continue;
+		}
+		debug("parent name:%s\n", parent->name);
+		*nparent += 1;
+	}
+
+	return 0;
+}
+
+static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents,
+				    u32 *num_parents)
+{
+	int j = 0, ret;
+	u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
+
+	*num_parents = 0;
+	do {
+		/* Get parents from firmware */
+		ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j,
+						  pm_resp);
+		if (ret)
+			return ret;
+
+		ret = __versal_clock_get_parents(&parents[j], pm_resp,
+						 num_parents);
+		if (ret == END_OF_PARENTS)
+			return 0;
+		j += PM_API_PAYLOAD_LEN;
+	} while (*num_parents <= MAX_PARENT);
+
+	return 0;
+}
+
+static u32 versal_clock_get_div(u32 clk_id)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 div;
+
+	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	div = ret_payload[1];
+
+	return div;
+}
+
+static u32 versal_clock_set_div(u32 clk_id, u32 div)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+
+	versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
+
+	return div;
+}
+
+static u64 versal_clock_ref(u32 clk_id)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ref;
+
+	versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
+	ref = ret_payload[0];
+	if (!(ref & 1))
+		return ref_clk;
+	if (ref & 2)
+		return pl_alt_ref_clk;
+	return 0;
+}
+
+static u64 versal_clock_get_pll_rate(u32 clk_id)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 fbdiv;
+	u32 res;
+	u32 frac;
+	u64 freq;
+	u32 parent_rate, parent_id;
+	u32 id = clk_id & 0xFFF;
+
+	versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+	res = ret_payload[1];
+	if (!res) {
+		printf("0%x PLL not enabled\n", clk_id);
+		return 0;
+	}
+
+	parent_id = clock[clock[id].parent[0].id].clk_id;
+	parent_rate = versal_clock_ref(parent_id);
+
+	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	fbdiv = ret_payload[1];
+	versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+	frac = ret_payload[1];
+
+	freq = (fbdiv * parent_rate) >> (1 << frac);
+
+	return freq;
+}
+
+static u32 versal_clock_mux(u32 clk_id)
+{
+	int i;
+	u32 id = clk_id & 0xFFF;
+
+	for (i = 0; i < clock[id].num_nodes; i++)
+		if (clock[id].node[i].type == CLOCK_NODE_TYPE_MUX)
+			return 1;
+
+	return 0;
+}
+
+static u32 versal_clock_get_parentid(u32 clk_id)
+{
+	u32 parent_id = 0;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 id = clk_id & 0xFFF;
+
+	if (versal_clock_mux(clk_id)) {
+		versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
+				  ret_payload);
+		parent_id = ret_payload[1];
+	}
+
+	debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id);
+	return clock[clock[id].parent[parent_id].id].clk_id;
+}
+
+static u32 versal_clock_gate(u32 clk_id)
+{
+	u32 id = clk_id & 0xFFF;
+	int i;
+
+	for (i = 0; i < clock[id].num_nodes; i++)
+		if (clock[id].node[i].type == CLOCK_NODE_TYPE_GATE)
+			return 1;
+
+	return 0;
+}
+
+static u32 versal_clock_div(u32 clk_id)
+{
+	int i;
+	u32 id = clk_id & 0xFFF;
+
+	for (i = 0; i < clock[id].num_nodes; i++)
+		if (clock[id].node[i].type == CLOCK_NODE_TYPE_DIV)
+			return 1;
+
+	return 0;
+}
+
+static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate)
+{
+	if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) ==
+	    NODE_SUBCLASS_CLOCK_PLL &&
+	    ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) ==
+	    NODE_CLASS_CLOCK) {
+		*clk_rate = versal_clock_get_pll_rate(clk_id);
+		return 1;
+	}
+
+	return 0;
+}
+
+static u64 versal_clock_calc(u32 clk_id)
+{
+	u32 parent_id;
+	u64 clk_rate;
+	u32 div;
+
+	if (versal_clock_pll(clk_id, &clk_rate))
+		return clk_rate;
+
+	parent_id = versal_clock_get_parentid(clk_id);
+	if (((parent_id >> NODE_SUBCLASS_SHIFT) &
+	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
+		return versal_clock_ref(clk_id);
+
+	clk_rate = versal_clock_calc(parent_id);
+
+	if (versal_clock_div(clk_id)) {
+		div = versal_clock_get_div(clk_id);
+		clk_rate =  DIV_ROUND_CLOSEST(clk_rate, div);
+	}
+
+	return clk_rate;
+}
+
+static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
+{
+	if (((clk_id >>  NODE_SUBCLASS_SHIFT) &
+	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
+		*clk_rate = versal_clock_ref(clk_id);
+
+	if (versal_clock_pll(clk_id, clk_rate))
+		return 0;
+
+	if (((clk_id >> NODE_SUBCLASS_SHIFT) &
+	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
+	    ((clk_id >> NODE_CLASS_SHIFT) &
+	     NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
+		if (!versal_clock_gate(clk_id))
+			return -EINVAL;
+		*clk_rate = versal_clock_calc(clk_id);
+		return 0;
+	}
+
+	return 0;
+}
+
+int soc_clk_dump(void)
+{
+	u64 clk_rate = 0;
+	u32 type, ret, i = 0;
+
+	printf("\n ****** VERSAL CLOCKS *****\n");
+
+	printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n",
+	       alt_ref_clk, pl_alt_ref_clk, ref_clk);
+	for (i = 0; i < clock_max_idx; i++) {
+		debug("%s\n", clock[i].clk_name);
+		ret = versal_get_clock_type(i, &type);
+		if (ret || type != CLK_TYPE_OUTPUT)
+			continue;
+
+		ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate);
+
+		if (ret != -EINVAL)
+			printf("clk: %s  freq:%lld\n",
+			       clock[i].clk_name, clk_rate);
+	}
+
+	return 0;
+}
+
+static void versal_get_clock_info(void)
+{
+	int i, ret;
+	u32 attr, type = 0, nodetype, subclass, class;
+
+	for (i = 0; i < clock_max_idx; i++) {
+		ret = versal_pm_clock_get_attributes(i, &attr);
+		if (ret)
+			continue;
+
+		clock[i].valid = attr & CLK_VALID_MASK;
+		clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
+				CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
+		nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
+		subclass = (attr >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK;
+		class = (attr >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK;
+
+		clock[i].clk_id = (class << NODE_CLASS_SHIFT) |
+				  (subclass << NODE_SUBCLASS_SHIFT) |
+				  (nodetype << NODE_TYPE_SHIFT) |
+				  (i << NODE_INDEX_SHIFT);
+
+		ret = versal_pm_clock_get_name(clock[i].clk_id,
+					       clock[i].clk_name);
+		if (ret)
+			continue;
+		debug("clk name:%s, Valid:%d, type:%d, clk_id:0x%x\n",
+		      clock[i].clk_name, clock[i].valid,
+		      clock[i].type, clock[i].clk_id);
+	}
+
+	/* Get topology of all clock */
+	for (i = 0; i < clock_max_idx; i++) {
+		ret = versal_get_clock_type(i, &type);
+		if (ret || type != CLK_TYPE_OUTPUT)
+			continue;
+		debug("clk name:%s\n", clock[i].clk_name);
+		ret = versal_clock_get_topology(i, clock[i].node,
+						&clock[i].num_nodes);
+		if (ret)
+			continue;
+
+		ret = versal_clock_get_parents(i, clock[i].parent,
+					       &clock[i].num_parents);
+		if (ret)
+			continue;
+	}
+}
+
+int versal_clock_setup(void)
+{
+	int ret;
+
+	ret = versal_pm_clock_get_num_clocks(&clock_max_idx);
+	if (ret)
+		return ret;
+
+	debug("%s, clock_max_idx:0x%x\n", __func__, clock_max_idx);
+	clock = calloc(clock_max_idx, sizeof(*clock));
+	if (!clock)
+		return -ENOMEM;
+
+	versal_get_clock_info();
+
+	return 0;
+}
+
+static int versal_clock_get_freq_by_name(char *name, struct udevice *dev,
+					 ulong *freq)
+{
+	struct clk clk;
+	int ret;
+
+	ret = clk_get_by_name(dev, name, &clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get %s\n", name);
+		return ret;
+	}
+
+	*freq = clk_get_rate(&clk);
+	if (IS_ERR_VALUE(*freq)) {
+		dev_err(dev, "failed to get rate %s\n", name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int versal_clk_probe(struct udevice *dev)
+{
+	int ret;
+	struct versal_clk_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk);
+	if (ret < 0)
+		return -EINVAL;
+
+	ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
+					    dev, &pl_alt_ref_clk);
+	if (ret < 0)
+		return -EINVAL;
+
+	ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
+	if (ret < 0)
+		return -EINVAL;
+
+	versal_clock_setup();
+
+	priv->clk = clock;
+
+	return ret;
+}
+
+static ulong versal_clk_get_rate(struct clk *clk)
+{
+	struct versal_clk_priv *priv = dev_get_priv(clk->dev);
+	u32 id = clk->id;
+	u32 clk_id;
+	u64 clk_rate = 0;
+
+	debug("%s\n", __func__);
+
+	clk_id = priv->clk[id].clk_id;
+
+	versal_clock_get_rate(clk_id, &clk_rate);
+
+	return clk_rate;
+}
+
+static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct versal_clk_priv *priv = dev_get_priv(clk->dev);
+	u32 id = clk->id;
+	u32 clk_id;
+	u64 clk_rate = 0;
+	u32 div;
+	int ret;
+
+	debug("%s\n", __func__);
+
+	clk_id = priv->clk[id].clk_id;
+
+	ret = versal_clock_get_rate(clk_id, &clk_rate);
+	if (ret) {
+		printf("Clock is not a Gate:0x%x\n", clk_id);
+		return 0;
+	}
+
+	do {
+		if (versal_clock_div(clk_id)) {
+			div = versal_clock_get_div(clk_id);
+			clk_rate *= div;
+			div = DIV_ROUND_CLOSEST(clk_rate, rate);
+			versal_clock_set_div(clk_id, div);
+			debug("%s, div:%d, newrate:%lld\n", __func__,
+			      div, DIV_ROUND_CLOSEST(clk_rate, div));
+			return DIV_ROUND_CLOSEST(clk_rate, div);
+		}
+		clk_id = versal_clock_get_parentid(clk_id);
+	} while (((clk_id >> NODE_SUBCLASS_SHIFT) &
+		 NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
+
+	printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
+
+	return clk_rate;
+}
+
+static struct clk_ops versal_clk_ops = {
+	.set_rate = versal_clk_set_rate,
+	.get_rate = versal_clk_get_rate,
+};
+
+static const struct udevice_id versal_clk_ids[] = {
+	{ .compatible = "xlnx,versal-clk" },
+	{ }
+};
+
+U_BOOT_DRIVER(versal_clk) = {
+	.name = "versal-clk",
+	.id = UCLASS_CLK,
+	.of_match = versal_clk_ids,
+	.probe = versal_clk_probe,
+	.ops = &versal_clk_ops,
+	.priv_auto_alloc_size = sizeof(struct versal_clk_priv),
+};

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