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@@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/dts-v1/;
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+#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/x86-gpio.h>
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/include/ "skeleton.dtsi"
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@@ -99,6 +100,7 @@
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clk: clock {
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compatible = "intel,apl-clk";
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#clock-cells = <1>;
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+ u-boot,dm-pre-reloc;
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};
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cpus {
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@@ -139,6 +141,7 @@
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};
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acpi_gpe: general-purpose-events {
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+ u-boot,dm-pre-reloc;
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reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
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compatible = "intel,acpi-gpe";
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interrupt-controller;
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@@ -417,8 +420,10 @@
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};
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i2c_2: i2c2@16,2 {
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- compatible = "intel,apl-i2c";
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+ compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
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reg = <0x0200b210 0 0 0 0>;
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+ early-regs = <IOMAP_I2C2_BASE 0x1000>;
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+ u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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@@ -429,6 +434,7 @@
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tpm: tpm@50 {
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reg = <0x50>;
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compatible = "google,cr50";
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+ u-boot,dm-pre-reloc;
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u-boot,i2c-offset-len = <0>;
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ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
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interrupts-extended = <&acpi_gpe GPIO_28_IRQ
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@@ -583,6 +589,7 @@
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u-boot,dm-pre-reloc;
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cros_ec: cros-ec {
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u-boot,dm-pre-proper;
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+ u-boot,dm-vpl;
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compatible = "google,cros-ec-lpc";
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reg = <0x204 1 0x200 1 0x880 0x80>;
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@@ -658,6 +665,11 @@
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PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
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PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
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PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
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+
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+ PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
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+ PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
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+ PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
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+ PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
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>;
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};
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@@ -1211,3 +1223,9 @@
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PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */
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>;
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};
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+
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+&rtc {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ u-boot,dm-pre-reloc;
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+};
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