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@@ -0,0 +1,76 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Xilinx Versal SOC driver
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+ *
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+ * Copyright (C) 2021 Xilinx, Inc.
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <soc.h>
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+#include <zynqmp_firmware.h>
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+#include <asm/io.h>
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+#include <asm/arch/hardware.h>
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+
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+/*
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+ * v1 -> 0x10 - ES1
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+ * v2 -> 0x20 - Production
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+ */
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+static const char versal_family[] = "Versal";
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+
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+struct soc_xilinx_versal_priv {
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+ const char *family;
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+ char revision;
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+};
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+
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+static int soc_xilinx_versal_get_family(struct udevice *dev, char *buf, int size)
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+{
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+ struct soc_xilinx_versal_priv *priv = dev_get_priv(dev);
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+
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+ return snprintf(buf, size, "%s", priv->family);
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+}
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+
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+static int soc_xilinx_versal_get_revision(struct udevice *dev, char *buf, int size)
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+{
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+ struct soc_xilinx_versal_priv *priv = dev_get_priv(dev);
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+
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+ return snprintf(buf, size, "v%d", priv->revision);
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+}
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+
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+static const struct soc_ops soc_xilinx_versal_ops = {
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+ .get_family = soc_xilinx_versal_get_family,
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+ .get_revision = soc_xilinx_versal_get_revision,
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+};
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+
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+static int soc_xilinx_versal_probe(struct udevice *dev)
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+{
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+ struct soc_xilinx_versal_priv *priv = dev_get_priv(dev);
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+ u32 ret_payload[4];
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+ int ret;
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+
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+ priv->family = versal_family;
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+
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+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
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+ ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
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+ ret_payload);
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+ if (ret)
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+ return ret;
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+ } else {
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+ ret_payload[2] = readl(VERSAL_PS_PMC_VERSION);
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+ if (!ret_payload[2])
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+ return -EINVAL;
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+ }
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+
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+ priv->revision = ret_payload[2] >> VERSAL_PS_VER_SHIFT;
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+
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+ return 0;
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+}
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+
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+U_BOOT_DRIVER(soc_xilinx_versal) = {
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+ .name = "soc_xilinx_versal",
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+ .id = UCLASS_SOC,
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+ .ops = &soc_xilinx_versal_ops,
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+ .probe = soc_xilinx_versal_probe,
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+ .priv_auto = sizeof(struct soc_xilinx_versal_priv),
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+ .flags = DM_FLAG_PRE_RELOC,
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+};
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