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Code cleanup; make several boards compile & link.

wdenk 20 anni fa
parent
commit
42dfe7a184
64 ha cambiato i file con 724 aggiunte e 701 eliminazioni
  1. 1 1
      CHANGELOG
  2. 9 9
      Makefile
  3. 1 1
      board/cogent/mb.c
  4. 0 1
      board/csb272/csb272.c
  5. 0 3
      board/dave/B2/flash.c
  6. 2 2
      board/dave/B2/u-boot.lds
  7. 1 1
      board/emk/common/flash.c
  8. 1 1
      board/emk/top5200/top5200.c
  9. 1 1
      board/gcplus/flash.c
  10. 1 1
      board/icecube/icecube.c
  11. 1 1
      board/integratorap/config.mk
  12. 245 223
      board/integratorap/integratorap.c
  13. 2 2
      board/integratorap/u-boot.lds
  14. 1 1
      board/integratorcp/config.mk
  15. 0 1
      board/integratorcp/integratorcp.c
  16. 2 2
      board/integratorcp/u-boot.lds
  17. 1 1
      board/mpl/common/common_util.c
  18. 0 1
      board/ocotea/ocotea.c
  19. 4 4
      board/siemens/CCM/ccm.c
  20. 5 5
      board/siemens/pcu_e/pcu_e.c
  21. 16 16
      board/ssv/common/cmd_sled.c
  22. 2 2
      board/trab/trab_fkt.c
  23. 1 1
      board/versatile/config.mk
  24. 2 2
      board/versatile/u-boot.lds
  25. 0 1
      board/versatile/versatile.c
  26. 27 19
      common/cmd_ide.c
  27. 1 1
      common/devices.c
  28. 17 17
      cpu/arm920t/serial.c
  29. 1 1
      cpu/arm926ejs/interrupts.c
  30. 5 5
      cpu/i386/serial.c
  31. 1 1
      cpu/mpc5xxx/ide.c
  32. 1 1
      cpu/ppc4xx/405gp_pci.c
  33. 5 5
      cpu/ppc4xx/cpu.c
  34. 3 3
      cpu/ppc4xx/serial.c
  35. 1 1
      cpu/ppc4xx/speed.c
  36. 9 10
      cpu/s3c44b0/start.S
  37. 4 4
      cpu/sa1100/serial.c
  38. 4 4
      disk/part.c
  39. 2 2
      doc/README.adnpesc1
  40. 1 1
      drivers/cs8900.h
  41. 1 1
      drivers/pci.c
  42. 93 96
      drivers/serial_pl010.c
  43. 86 88
      drivers/serial_pl011.c
  44. 10 10
      drivers/serial_pl011.h
  45. 37 37
      drivers/smc91111.c
  46. 1 1
      drivers/usbtty.c
  47. 1 1
      include/ata.h
  48. 2 2
      include/common.h
  49. 2 2
      include/configs/MPC8266ADS.h
  50. 31 31
      include/configs/OCOTEA.h
  51. 1 1
      include/configs/TOP860.h
  52. 2 2
      include/configs/gcplus.h
  53. 26 25
      include/configs/integratorap.h
  54. 2 1
      include/configs/integratorcp.h
  55. 2 2
      include/configs/ppmc8260.h
  56. 2 2
      include/configs/sacsng.h
  57. 2 2
      include/configs/sbc8260.h
  58. 7 6
      include/configs/versatile.h
  59. 1 1
      include/ide.h
  60. 27 24
      include/part.h
  61. 4 4
      lib_generic/vsprintf.c
  62. 1 1
      lib_i386/board.c
  63. 1 1
      lib_m68k/board.c
  64. 1 1
      lib_ppc/board.c

+ 1 - 1
CHANGELOG

@@ -14,7 +14,7 @@ Changes for U-Boot 1.0.2:
 
 * Patch by Leon Kukovec, 12 Mar 2004:
   Fix get_dentfromdir() to correctly handle deleted dentries
-  
+
 * Patch by George G. Davis, 11 Mar 2004:
   Remove hard coded network settings in TI OMAP1610 H2
   default board config

+ 9 - 9
Makefile

@@ -1144,17 +1144,17 @@ ADNPESC1_base_32_config		\
 ADNPESC1_config: unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _DNPEVA2,$@)" ] || \
-                { echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
-                  echo "... DNP/EVA2 configuration" ; \
-                }
+		{ echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
+		  echo "... DNP/EVA2 configuration" ; \
+		}
 	@[ -z "$(findstring _base_32,$@)" ] || \
-                { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
-                  echo "... NIOS 'base_32' configuration" ; \
-                }
+		{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+		  echo "... NIOS 'base_32' configuration" ; \
+		}
 	@[ -z "$(findstring ADNPESC1_config,$@)" ] || \
-                { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
-                  echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
-                }
+		{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+		  echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
+		}
 	@./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
 
 

+ 1 - 1
board/cogent/mb.c

@@ -235,7 +235,7 @@ int misc_init_f (void)
 
 long int initdram (int board_type)
 {
-#if CONFIG_CMA111
+#ifdef CONFIG_CMA111
 	return (32L * 1024L * 1024L);
 #else
 	unsigned char dipsw_val;

+ 0 - 1
board/csb272/csb272.c

@@ -171,4 +171,3 @@ int last_stage_init(void)
 
 	return 0; /* success */
 }
-

+ 0 - 3
board/dave/B2/flash.c

@@ -45,9 +45,6 @@ unsigned long flash_init (void)
 #else
 	unsigned long size_b0;
 	int i;
-	uint pbcr;
-	unsigned long base_b0;
-	int size_val = 0;
 
 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {

+ 2 - 2
board/dave/B2/u-boot.lds

@@ -51,7 +51,7 @@ SECTIONS
 	armboot_end_data = .;
 
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-
-	armboot_end = .;
+	_end = .;
 }

+ 1 - 1
board/emk/common/flash.c

@@ -353,7 +353,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 			}
 			break;
 		}
-		
+
 		/* fall thru to here ! */
 	default:
 		printf ("unknown AMD device=%x %x %x",

+ 1 - 1
board/emk/top5200/top5200.c

@@ -57,7 +57,7 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
 	/* precharge all banks */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-#if CFG_DRAM_DDR
+#ifdef CFG_DRAM_DDR
 	/* set extended mode register */
 	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
 #endif

+ 1 - 1
board/gcplus/flash.c

@@ -404,7 +404,7 @@ write_data(flash_info_t * info, ulong dest, FPW data)
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) {
-		printf("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr);
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */

+ 1 - 1
board/icecube/icecube.c

@@ -215,7 +215,7 @@ void pci_init_board(void)
 void init_ide_reset (void)
 {
 	debug ("init_ide_reset\n");
-    
+
     	/* Configure PSC1_4 as GPIO output for ATA reset */
 	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;

+ 1 - 1
board/integratorap/config.mk

@@ -1,5 +1,5 @@
 #
-# image should be loaded at 0x01000000 
+# image should be loaded at 0x01000000
 #
 
 TEXT_BASE = 0x01000000

+ 245 - 223
board/integratorap/integratorap.c

@@ -105,146 +105,161 @@ static struct pci_config_table pci_integrator_config_table[] = {
 };
 #endif
 
-// V3 access routines
+/* V3 access routines */
 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
 #define _V3Read16(o)    (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
 
 #define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
 #define _V3Read32(o)    (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
 
-// Compute address necessary to access PCI config space for the given
-// bus and device.
-#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
-    ({                                                                   		\
-    unsigned int __address, __devicebit;							\
-    unsigned short __mapaddress;								\
-    unsigned int __dev = PCI_DEV(__devfn);	/* FIXME to check!! (slot?) */	\
+/* Compute address necessary to access PCI config space for the given */
+/* bus and device. */
+#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({				\
+	unsigned int __address, __devicebit;						\
+	unsigned short __mapaddress;							\
+	unsigned int __dev = PCI_DEV (__devfn);	/* FIXME to check!! (slot?) */		\
 											\
-    if (__bus == 0) {									\
-	/* local bus segment so need a type 0 config cycle */				\
-        /* build the PCI configuration "address" with one-hot in A31-A11 */		\
-        __address = PCI_CONFIG_BASE;							\
-        __address |= ((__devfn & 0x07) << 8);						\
-        __address |= __offset & 0xFF;							\
-        __mapaddress = 0x000A;    /* 101=>config cycle, 0=>A1=A0=0 */			\
-        __devicebit = (1 << (__dev + 11));						\
+	if (__bus == 0) {								\
+		/* local bus segment so need a type 0 config cycle */			\
+		/* build the PCI configuration "address" with one-hot in A31-A11 */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__devfn & 0x07) << 8);					\
+		__address |= __offset & 0xFF;						\
+		__mapaddress = 0x000A;	/* 101=>config cycle, 0=>A1=A0=0 */		\
+		__devicebit = (1 << (__dev + 11));					\
 											\
-        if ((__devicebit & 0xFF000000) != 0) {						\
-            /* high order bits are handled by the MAP register */			\
-            __mapaddress |= (__devicebit >> 16);					\
-        } else {									\
-            /* low order bits handled directly in the address */			\
-            __address |= __devicebit;							\
-        }										\
-    } else {	/* bus !=0 */								\
-        /* not the local bus segment so need a type 1 config cycle */			\
-        /* A31-A24 are don't care (so clear to 0) */					\
-        __mapaddress = 0x000B;    /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
-        __address = PCI_CONFIG_BASE;							\
-        __address |= ((__bus & 0xFF) << 16);  	/* bits 23..16 = bus number 	*/	\
-        __address |= ((__dev & 0x1F) << 11);  	/* bits 15..11 = device number  */	\
-        __address |= ((__devfn & 0x07) << 8);  	/* bits 10..8  = function number*/	\
-        __address |= __offset & 0xFF;  		/* bits  7..0  = register number*/	\
-    }											\
-    _V3Write16(V3_LB_MAP1, __mapaddress);						\
+		if ((__devicebit & 0xFF000000) != 0) {					\
+			/* high order bits are handled by the MAP register */		\
+			__mapaddress |= (__devicebit >> 16);				\
+		} else {								\
+			/* low order bits handled directly in the address */		\
+			__address |= __devicebit;					\
+		}									\
+	} else {		/* bus !=0 */						\
+		/* not the local bus segment so need a type 1 config cycle */		\
+		/* A31-A24 are don't care (so clear to 0) */				\
+		__mapaddress = 0x000B;	/* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__bus & 0xFF) << 16);	/* bits 23..16 = bus number     */  \
+		__address |= ((__dev & 0x1F) << 11);	/* bits 15..11 = device number  */  \
+		__address |= ((__devfn & 0x07) << 8);	/* bits 10..8  = function number */ \
+		__address |= __offset & 0xFF;	/* bits  7..0  = register number */	\
+	}										\
+	_V3Write16 (V3_LB_MAP1, __mapaddress);						\
+	__address;									\
+})
+
+/* _V3OpenConfigWindow - open V3 configuration window */
+#define _V3OpenConfigWindow() {								\
+	/* Set up base0 to see all 512Mbytes of memory space (not	     */		\
+	/* prefetchable), this frees up base1 for re-use by configuration*/		\
+	/* memory */									\
 											\
-    __address;										\
-    })
-
-// _V3OpenConfigWindow - open V3 configuration window
-#define _V3OpenConfigWindow() 							\
-    {										\
-    /* Set up base0 to see all 512Mbytes of memory space (not	     */		\
-    /* prefetchable), this frees up base1 for re-use by configuration*/		\
-    /* memory */								\
-										\
-    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
-			     0x90 | V3_LB_BASE_M_ENABLE));			\
-    /* Set up base1 to point into configuration space, note that MAP1 */	\
-    /* register is set up by pciMakeConfigAddress(). */				\
-										\
-    _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |		\
-			     0x40 | V3_LB_BASE_M_ENABLE));			\
-    }
-
-// _V3CloseConfigWindow - close V3 configuration window
-#define _V3CloseConfigWindow()							\
-    {										\
-    /* Reassign base1 for use by prefetchable PCI memory */			\
-    _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
-					| 0x84 | V3_LB_BASE_M_ENABLE));		\
-    _V3Write16 (V3_LB_MAP1,							\
-	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
-										\
-    /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
-										\
-    _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |		\
-			     0x80 | V3_LB_BASE_M_ENABLE));			\
-    }
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+				     0x90 | V3_LB_BASE_M_ENABLE));			\
+	/* Set up base1 to point into configuration space, note that MAP1 */		\
+	/* register is set up by pciMakeConfigAddress(). */				\
+											\
+	_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |			\
+				     0x40 | V3_LB_BASE_M_ENABLE));			\
+}
 
+/* _V3CloseConfigWindow - close V3 configuration window */
+#define _V3CloseConfigWindow() {							\
+    /* Reassign base1 for use by prefetchable PCI memory */				\
+	_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
+					| 0x84 | V3_LB_BASE_M_ENABLE));			\
+	_V3Write16 (V3_LB_MAP1,								\
+	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
+											\
+	/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
+											\
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+			     0x80 | V3_LB_BASE_M_ENABLE));				\
+}
 
-static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t dev,
-				    int offset, unsigned char *val)
+static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned char *val)
 {
-    _V3OpenConfigWindow();
-    *val = *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							       PCI_FUNC (dev),
+							       offset);
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev,
-				     int offset, unsigned short *val)
+static int pci_integrator_read__word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short *val)
 {
-    _V3OpenConfigWindow();
-    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev,
-				     int offset, unsigned int *val)
+static int pci_integrator_read_dword (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned int *val)
 {
-    _V3OpenConfigWindow();
-    *val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset);
-    *val |= (*(volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16;
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	*val |= (*(volatile unsigned int *)
+		 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
+				     (offset + 2))) << 16;
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev,
-				     int offset, unsigned char val)
+static int pci_integrator_write_byte (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned char val)
 {
-    _V3OpenConfigWindow();
-    *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							PCI_FUNC (dev),
+							offset) = val;
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev,
-				     int offset,unsigned short val)
+static int pci_integrator_write_word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short val)
 {
-    _V3OpenConfigWindow();
-    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val;
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = val;
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
 
-static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev,
-				      int offset, unsigned int val)
+static int pci_integrator_write_dword (struct pci_controller *hose,
+				       pci_dev_t dev, int offset,
+				       unsigned int val)
 {
-    _V3OpenConfigWindow();
-    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF);
-    *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF);
-    _V3CloseConfigWindow();
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = (val & 0xFFFF);
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 (offset + 2)) = ((val >> 16) & 0xFFFF);
+	_V3CloseConfigWindow ();
 
-    return 0;
+	return 0;
 }
-
 /******************************
  * PCI initialisation
  ******************************/
@@ -255,176 +270,184 @@ struct pci_controller integrator_hose = {
 #endif
 };
 
-void pci_init_board(void)
+void pci_init_board (void)
 {
-    volatile int i, j;
-    struct pci_controller *hose = &integrator_hose;
+	volatile int i, j;
+	struct pci_controller *hose = &integrator_hose;
 
-    /* setting this register will take the V3 out of reset */
+	/* setting this register will take the V3 out of reset */
 
-    *(volatile unsigned int *)(INTEGRATOR_SC_PCIENABLE) = 1;
+	*(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
 
-    /* wait a few usecs to settle the device and the PCI bus */
+	/* wait a few usecs to settle the device and the PCI bus */
 
-    for (i = 0; i < 100 ; i++)
-	   j = i + 1;
+	for (i = 0; i < 100; i++)
+		j = i + 1;
 
-    /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
+	/* Now write the Base I/O Address Word to V3_BASE + 0x6C */
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16);
+	*(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
+		(unsigned short) (V3_BASE >> 16);
 
-    do {
-        *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
-	*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
-    } while (*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
-	     *(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
+	do {
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
+			0x55;
+	} while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
+		 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
+						 4) != 0x55);
 
-    /* Make sure that V3 register access is not locked, if it is, unlock it */
+	/* Make sure that V3 register access is not locked, if it is, unlock it */
 
-    if ((*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
-				== V3_SYSTEM_M_LOCK)
-	*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = 0xA05F;
+	if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
+	     V3_SYSTEM_M_LOCK)
+	    == V3_SYSTEM_M_LOCK)
+		*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
 
-    /* Ensure that the slave accesses from PCI are disabled while we */
-    /* setup windows */
+	/* Ensure that the slave accesses from PCI are disabled while we */
+	/* setup windows */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) &=
-				~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
+		~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
 
-    /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+	/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
 
-    *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
+		~V3_SYSTEM_M_RST_OUT;
 
-    /* Make all accesses from PCI space retry until we're ready for them */
+	/* Make all accesses from PCI space retry until we're ready for them */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
+		V3_PCI_CFG_M_RETRY_EN;
 
-    /* Set up any V3 PCI Configuration Registers that we absolutely have to */
-    /* LB_CFG controls Local Bus protocol. */
-    /* Enable LocalBus byte strobes for READ accesses too. */
-    /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
+	/* Set up any V3 PCI Configuration Registers that we absolutely have to */
+	/* LB_CFG controls Local Bus protocol. */
+	/* Enable LocalBus byte strobes for READ accesses too. */
+	/* set bit 7 BE_IMODE and bit 6 BE_OMODE */
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_CFG) |= 0x0C0;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
 
-    /* PCI_CMD controls overall PCI operation. */
-    /* Enable PCI bus master. */
+	/* PCI_CMD controls overall PCI operation. */
+	/* Enable PCI bus master. */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) |= 0x04;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
 
-    /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/
+	/* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
-					(V3_PCI_MAP_M_ADR_SIZE_512M |
-					V3_PCI_MAP_M_REG_EN |
-					V3_PCI_MAP_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
+		(INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
+					      V3_PCI_MAP_M_REG_EN |
+					      V3_PCI_MAP_M_ENABLE);
 
-    /* PCI_BASE0 is the PCI address of the start of the window */
+	/* PCI_BASE0 is the PCI address of the start of the window */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
+		INTEGRATOR_BOOT_ROM_BASE;
 
-    /* PCI_MAP1 is LOCAL address of the start of the window */
+	/* PCI_MAP1 is LOCAL address of the start of the window */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
-			(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
-			 V3_PCI_MAP_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
+		(INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
+						V3_PCI_MAP_M_REG_EN |
+						V3_PCI_MAP_M_ENABLE);
 
-    /* PCI_BASE1 is the PCI address of the start of the window */
+	/* PCI_BASE1 is the PCI address of the start of the window */
 
-    *(volatile unsigned int *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
+		INTEGRATOR_HDR0_SDRAM_BASE;
 
-    /* Set up the windows from local bus memory into PCI configuration, */
-    /* I/O and Memory. */
-    /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
+	/* Set up the windows from local bus memory into PCI configuration, */
+	/* I/O and Memory. */
+	/* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
 
-    *(volatile unsigned short *)(V3_BASE +V3_LB_BASE2) =
-			((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
-    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP2) = 0;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
+		((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
 
-    /* PCI Configuration, use LB_BASE1/LB_MAP1. */
+	/* PCI Configuration, use LB_BASE1/LB_MAP1. */
 
-    /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
-    /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
-    /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
+	/* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
+	/* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
+	/* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
 
-    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE0) =
-			INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
+		INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP0) =
-			((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
+		((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
 
-    /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+	/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
 
-    *(volatile unsigned int *)(V3_BASE + V3_LB_BASE1) =
-			INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
+		INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
 
-    *(volatile unsigned short *)(V3_BASE + V3_LB_MAP1) =
-			(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
+		(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
 
-    /* Allow accesses to PCI Configuration space */
-    /* and set up A1, A0 for type 1 config cycles */
+	/* Allow accesses to PCI Configuration space */
+	/* and set up A1, A0 for type 1 config cycles */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) =
-			((*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG)) &
-			   ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
-			   V3_PCI_CFG_M_AD_LOW0;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
+		((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
+		 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
+		V3_PCI_CFG_M_AD_LOW0;
 
-    /* now we can allow in PCI MEMORY accesses */
+	/* now we can allow in PCI MEMORY accesses */
 
-    *(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) =
-		(*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
+		(*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
+		V3_COMMAND_M_MEM_EN;
 
-    /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
-    /* initialise and lock the V3 system register so that no one else */
-    /* can play with it */
+	/* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
+	/* initialise and lock the V3 system register so that no one else */
+	/* can play with it */
 
-   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
-		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_RST_OUT;
 
-   *(volatile unsigned short *)(V3_BASE + V3_SYSTEM) =
-		(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_LOCK;
 
-     /*
-      * Register the hose
-      */
-   hose->first_busno = 0;
-   hose->last_busno = 0xff;
+	/*
+	 * Register the hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
 
-   /* System memory space */
-   pci_set_region(hose->regions + 0,
-		  0x00000000, 0x40000000, 0x01000000,
-		  PCI_REGION_MEM | PCI_REGION_MEMORY);
+	/* System memory space */
+	pci_set_region (hose->regions + 0,
+			0x00000000, 0x40000000, 0x01000000,
+			PCI_REGION_MEM | PCI_REGION_MEMORY);
 
-   /* PCI Memory - config space */
-   pci_set_region(hose->regions + 1,
-		  0x00000000, 0x62000000, 0x01000000,
-		  PCI_REGION_MEM);
+	/* PCI Memory - config space */
+	pci_set_region (hose->regions + 1,
+			0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
 
-   /* PCI V3 regs */
-   pci_set_region(hose->regions + 2,
-		  0x00000000, 0x61000000, 0x00080000,
-		  PCI_REGION_MEM);
+	/* PCI V3 regs */
+	pci_set_region (hose->regions + 2,
+			0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
 
-   /* PCI I/O space */
-   pci_set_region(hose->regions + 3,
-		  0x00000000, 0x60000000, 0x00010000,
-		  PCI_REGION_IO);
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 3,
+			0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
 
-   pci_set_ops(hose,
-	       pci_integrator_read_byte,
-	       pci_integrator_read__word,
-	       pci_integrator_read_dword,
-	       pci_integrator_write_byte,
-	       pci_integrator_write_word,
-	       pci_integrator_write_dword);
+	pci_set_ops (hose,
+		     pci_integrator_read_byte,
+		     pci_integrator_read__word,
+		     pci_integrator_read_dword,
+		     pci_integrator_write_byte,
+		     pci_integrator_write_word, pci_integrator_write_dword);
 
-   hose->region_count = 4;
+	hose->region_count = 4;
 
-   pci_register_hose(hose);
+	pci_register_hose (hose);
 
-   pciauto_config_init(hose);
-   pciauto_config_device(hose, 0);
+	pciauto_config_init (hose);
+	pciauto_config_device (hose, 0);
 
-   hose->last_busno = pci_hose_scan(hose);
+	hose->last_busno = pci_hose_scan (hose);
 }
 #endif
 
@@ -452,4 +475,3 @@ int dram_init (void)
 {
 	return 0;
 }
-

+ 2 - 2
board/integratorap/u-boot.lds

@@ -43,8 +43,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
-	armboot_end_data = .;
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-	armboot_end = .;
+	_end = .;
 }

+ 1 - 1
board/integratorcp/config.mk

@@ -1,5 +1,5 @@
 #
-# image should be loaded at 0x01000000 
+# image should be loaded at 0x01000000
 #
 
 TEXT_BASE = 0x01000000

+ 0 - 1
board/integratorcp/integratorcp.c

@@ -107,4 +107,3 @@ int dram_init (void)
 {
 	return 0;
 }
-

+ 2 - 2
board/integratorcp/u-boot.lds

@@ -43,8 +43,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
-	armboot_end_data = .;
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-	armboot_end = .;
+	_end = .;
 }

+ 1 - 1
board/mpl/common/common_util.c

@@ -232,7 +232,7 @@ mpl_prg_image(uchar *ld_addr)
 			}
 			puts("OK\n");
 			break;
-#if CONFIG_BZIP2
+#ifdef CONFIG_BZIP2
 		case IH_COMP_BZIP2:
 			puts("Uncompressing (BZIP2) ... ");
 			{

+ 0 - 1
board/ocotea/ocotea.c

@@ -474,4 +474,3 @@ int post_hotkeys_pressed(void)
 	return (ctrlc());
 }
 #endif
-

+ 4 - 4
board/siemens/CCM/ccm.c

@@ -351,7 +351,7 @@ void	reset_phy(void)
 	ulong value;
 
 	/* Configure all needed port pins for GPIO */
-#if CFG_ETH_MDDIS_VALUE
+#ifdef CFG_ETH_MDDIS_VALUE
 	immr->im_ioport.iop_padat |=   CFG_PA_ETH_MDDIS;
 #else
 	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* Set low */
@@ -369,17 +369,17 @@ void	reset_phy(void)
 	value |=  CFG_PB_ETH_POWERDOWN;
 
 	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
-#if CFG_ETH_CFG1_VALUE
+#ifdef CFG_ETH_CFG1_VALUE
 	value |=   CFG_PB_ETH_CFG1;
 #else
 	value &= ~(CFG_PB_ETH_CFG1);
 #endif
-#if CFG_ETH_CFG2_VALUE
+#ifdef CFG_ETH_CFG2_VALUE
 	value |=   CFG_PB_ETH_CFG2;
 #else
 	value &= ~(CFG_PB_ETH_CFG2);
 #endif
-#if CFG_ETH_CFG3_VALUE
+#ifdef CFG_ETH_CFG3_VALUE
 	value |=   CFG_PB_ETH_CFG3;
 #else
 	value &= ~(CFG_PB_ETH_CFG3);

+ 5 - 5
board/siemens/pcu_e/pcu_e.c

@@ -309,7 +309,7 @@ void reset_phy (void)
 
 	/* Configure all needed port pins for GPIO */
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
-# if CFG_ETH_MDDIS_VALUE
+# ifdef CFG_ETH_MDDIS_VALUE
 	immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
 # else
 	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS);	/* Set low */
@@ -329,23 +329,23 @@ void reset_phy (void)
 
 	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
 #if !PCU_E_WITH_SWAPPED_CS
-# if CFG_ETH_MDDIS_VALUE
+# ifdef CFG_ETH_MDDIS_VALUE
 	value |= CFG_PB_ETH_MDDIS;
 # else
 	value &= ~(CFG_PB_ETH_MDDIS);
 # endif
 #endif
-#if CFG_ETH_CFG1_VALUE
+#ifdef CFG_ETH_CFG1_VALUE
 	value |= CFG_PB_ETH_CFG1;
 #else
 	value &= ~(CFG_PB_ETH_CFG1);
 #endif
-#if CFG_ETH_CFG2_VALUE
+#ifdef CFG_ETH_CFG2_VALUE
 	value |= CFG_PB_ETH_CFG2;
 #else
 	value &= ~(CFG_PB_ETH_CFG2);
 #endif
-#if CFG_ETH_CFG3_VALUE
+#ifdef CFG_ETH_CFG3_VALUE
 	value |= CFG_PB_ETH_CFG3;
 #else
 	value &= ~(CFG_PB_ETH_CFG3);

+ 16 - 16
board/ssv/common/cmd_sled.c

@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -28,20 +28,20 @@
 #if	defined(CONFIG_STATUS_LED)
 
 /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- * !!!!!       Q u i c k   &   D i r t y   H a c k       !!!!!
+ * !!!!!       Q u i c k   &   D i r t y   H a c k	 !!!!!
  * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- * !!!!!                                                 !!!!!
- * !!!!! Next type definition was coming from original   !!!!!
- * !!!!! status LED driver drivers/status_led.c and      !!!!!
- * !!!!! should exported for using here.                 !!!!!
- * !!!!!                                                 !!!!!
+ * !!!!!						 !!!!!
+ * !!!!! Next type definition was coming from original	 !!!!!
+ * !!!!! status LED driver drivers/status_led.c and	 !!!!!
+ * !!!!! should exported for using here.		 !!!!!
+ * !!!!!						 !!!!!
  * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
 
 typedef struct {
-        led_id_t mask;
-        int state;
-        int period;
-        int cnt;
+	led_id_t mask;
+	int state;
+	int period;
+	int cnt;
 } led_dev_t;
 
 extern led_dev_t led_dev[];
@@ -141,18 +141,18 @@ int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #ifdef	STATUS_LED_RED
 #ifdef	STATUS_LED_YELLOW
 #ifdef	STATUS_LED_GREEN
-#define	__NAME_STR		"    - name: boot|red|yellow|green\n"
+#define __NAME_STR		"    - name: boot|red|yellow|green\n"
 #else
-#define	__NAME_STR		"    - name: boot|red|yellow\n"
+#define __NAME_STR		"    - name: boot|red|yellow\n"
 #endif
 #else
-#define	__NAME_STR		"    - name: boot|red\n"
+#define __NAME_STR		"    - name: boot|red\n"
 #endif
 #else
-#define	__NAME_STR		"    - name: boot\n"
+#define __NAME_STR		"    - name: boot\n"
 #endif
 #else
-#define	__NAME_STR		"    - name: (no such defined)\n"
+#define __NAME_STR		"    - name: (no such defined)\n"
 #endif
 
 U_BOOT_CMD (sled, 3, 0, do_sled,

+ 2 - 2
board/trab/trab_fkt.c

@@ -890,7 +890,7 @@ int do_touch (char **argv)
 	int     x, y;
 
 	if (strcmp (argv[2], "tl") == 0) {
-#if CONFIG_TOUCH_WAIT_PRESSED
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
 		touch_wait_pressed();
 #else
 		{
@@ -915,7 +915,7 @@ int do_touch (char **argv)
 		return touch_write_clibration_values (CALIB_TL, x, y);
 	}
 	else if (strcmp (argv[2], "dr") == 0) {
-#if CONFIG_TOUCH_WAIT_PRESSED
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
 		touch_wait_pressed();
 #else
 		{

+ 1 - 1
board/versatile/config.mk

@@ -1,5 +1,5 @@
 #
-# image should be loaded at 0x01000000 
+# image should be loaded at 0x01000000
 #
 
 TEXT_BASE = 0x01000000

+ 2 - 2
board/versatile/u-boot.lds

@@ -43,8 +43,8 @@ SECTIONS
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 
-	armboot_end_data = .;
 	. = ALIGN(4);
+	__bss_start = .;
 	.bss : { *(.bss) }
-	armboot_end = .;
+	_end = .;
 }

+ 0 - 1
board/versatile/versatile.c

@@ -117,4 +117,3 @@ int dram_init (void)
 {
 	return 0;
 }
-

+ 27 - 19
common/cmd_ide.c

@@ -303,16 +303,19 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	if (strcmp(argv[1],"read") == 0) {
 		ulong addr = simple_strtoul(argv[2], NULL, 16);
-#if CFG_64BIT_STRTOUL
-		lbaint_t blk  = simple_strtoull(argv[3], NULL, 16);
-#else
-		lbaint_t blk  = simple_strtoul(argv[3], NULL, 16);
-#endif
 		ulong cnt  = simple_strtoul(argv[4], NULL, 16);
 		ulong n;
+#ifdef CFG_64BIT_STRTOUL
+		lbaint_t blk  = simple_strtoull(argv[3], NULL, 16);
 
 		printf ("\nIDE read: device %d block # %qd, count %ld ... ",
 			curr_device, blk, cnt);
+#else
+		lbaint_t blk  = simple_strtoul(argv[3], NULL, 16);
+
+		printf ("\nIDE read: device %d block # %ld, count %ld ... ",
+			curr_device, blk, cnt);
+#endif
 
 		n = ide_dev_desc[curr_device].block_read (curr_device,
 							  blk, cnt,
@@ -329,16 +332,19 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 	} else if (strcmp(argv[1],"write") == 0) {
 		ulong addr = simple_strtoul(argv[2], NULL, 16);
-#if CFG_64BIT_STRTOUL
-		lbaint_t blk  = simple_strtoull(argv[3], NULL, 16);
-#else
-		lbaint_t blk  = simple_strtoul(argv[3], NULL, 16);
-#endif
 		ulong cnt  = simple_strtoul(argv[4], NULL, 16);
 		ulong n;
+#ifdef CFG_64BIT_STRTOUL
+		lbaint_t blk  = simple_strtoull(argv[3], NULL, 16);
 
 		printf ("\nIDE write: device %d block # %qd, count %ld ... ",
 			curr_device, blk, cnt);
+#else
+		lbaint_t blk  = simple_strtoul(argv[3], NULL, 16);
+
+		printf ("\nIDE write: device %d block # %ld, count %ld ... ",
+			curr_device, blk, cnt);
+#endif
 
 		n = ide_write (curr_device, blk, cnt, (ulong *)addr);
 
@@ -1161,7 +1167,7 @@ static void ide_ident (block_dev_desc_t *dev_desc)
 	dev_desc->lba = iop->lba_capacity;
 #endif	/* __BIG_ENDIAN */
 
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 	if (iop->command_set_2 & 0x0400) { /* LBA 48 support */
 		dev_desc->lba48support = 1;
 		dev_desc->lba48 = (unsigned long long)iop->lba48_capacity[0] |
@@ -1203,7 +1209,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 	ulong n = 0;
 	unsigned char c;
 	unsigned char pwrsave=0; /* power save */
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 	unsigned char lba48 = 0;
 
 	if (blknr & 0x0000fffff0000000) {
@@ -1255,7 +1261,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 			printf ("IDE read: device %d not ready\n", device);
 			break;
 		}
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 		if (lba48) {
 			/* write high bits */
 			ide_outb (device, ATA_SECT_CNT, 0);
@@ -1269,7 +1275,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 		ide_outb (device, ATA_LBA_MID,  (blknr >>  8) & 0xFF);
 		ide_outb (device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
 
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 		if (lba48) {
 			ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) );
 			ide_outb (device, ATA_COMMAND, ATA_CMD_READ_EXT);
@@ -1293,7 +1299,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 		}
 
 		if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
-#if CFG_64BIT_LBA && CFG_64BIT_VSPRINTF
+#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF)
 			printf ("Error (no IRQ) dev %d blk %qd: status 0x%02x\n",
 				device, blknr, c);
 #else
@@ -1322,7 +1328,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 {
 	ulong n = 0;
 	unsigned char c;
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 	unsigned char lba48 = 0;
 
 	if (blknr & 0x0000fffff0000000) {
@@ -1345,7 +1351,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 			printf ("IDE read: device %d not ready\n", device);
 			goto WR_OUT;
 		}
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 		if (lba48) {
 			/* write high bits */
 			ide_outb (device, ATA_SECT_CNT, 0);
@@ -1359,7 +1365,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 		ide_outb (device, ATA_LBA_MID,  (blknr >>  8) & 0xFF);
 		ide_outb (device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
 
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 		if (lba48) {
 			ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) );
 			ide_outb (device, ATA_COMMAND,	ATA_CMD_WRITE_EXT);
@@ -1378,7 +1384,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
 		c = ide_wait (device, IDE_TIME_OUT);	/* can't take over 500 ms */
 
 		if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
-#if CFG_64BIT_LBA && CFG_64BIT_VSPRINTF
+#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF)
 			printf ("Error (no IRQ) dev %d blk %qd: status 0x%02x\n",
 				device, blknr, c);
 #else
@@ -1959,7 +1965,9 @@ static void	atapi_inquiry(block_dev_desc_t * dev_desc)
 			((unsigned long)iobuf[5]<<16) +
 			((unsigned long)iobuf[6]<< 8) +
 			((unsigned long)iobuf[7]);
+#ifdef CONFIG_LBA48
 	dev_desc->lba48 = 0; /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
+#endif
 	return;
 }
 

+ 1 - 1
common/devices.c

@@ -73,7 +73,7 @@ static void drv_system_init (void)
 
 	strcpy (dev.name, "serial");
 	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 	dev.putc = serial_buffered_putc;
 	dev.puts = serial_buffered_puts;
 	dev.getc = serial_buffered_getc;

+ 17 - 17
cpu/arm920t/serial.c

@@ -1,18 +1,18 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
+	/*
+	 * (C) Copyright 2002
+	 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+	 *
+	 * This program is free software; you can redistribute it and/or modify
+	 * it under the terms of the GNU General Public License as published by
+	 * the Free Software Foundation; either version 2 of the License, or
+	 * (at your option) any later version.
+	 *
+	 * This program is distributed in the hope that it will be useful,
+	 * but WITHOUT ANY WARRANTY; without even the implied warranty of
+	 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	 * GNU General Public License for more details.
+	 *
+	 * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  *
@@ -28,13 +28,13 @@
 #ifdef CONFIG_SERIAL1
 #define UART_NR	S3C24X0_UART0
 
-#elif CONFIG_SERIAL2
+#elif defined(CONFIG_SERIAL2)
 # if defined(CONFIG_TRAB)
 #  error "TRAB supports only CONFIG_SERIAL1"
 # endif
 #define UART_NR	S3C24X0_UART1
 
-#elif CONFIG_SERIAL3
+#elif defined(CONFIG_SERIAL3)
 # if defined(CONFIG_TRAB)
 #  #error "TRAB supports only CONFIG_SERIAL1"
 # endif

+ 1 - 1
cpu/arm926ejs/interrupts.c

@@ -293,7 +293,7 @@ ulong get_timer_masked (void)
 /* waits specified delay value and resets timestamp */
 void udelay_masked (unsigned long usec)
 {
-	ulong tmo, tmp;
+	ulong tmo;
 
 	if(usec >= 1000){               /* if "big" number, spread normalization to seconds */
 		tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */

+ 5 - 5
cpu/i386/serial.c

@@ -51,7 +51,7 @@
 #include <asm/io.h>
 #include <asm/ibmpc.h>
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 #include <malloc.h>
 #endif
 
@@ -81,7 +81,7 @@
 #define asyncLSRRxFifoError1          0x80
 
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 /*-----------------------------------------------------------------------------+
   | Fifo
   +-----------------------------------------------------------------------------*/
@@ -193,7 +193,7 @@ int serial_getc(void)
 {
 	unsigned char status = 0;
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 	if (serial_buffer_active) {
 		return serial_buffered_getc();
 	}
@@ -225,7 +225,7 @@ int serial_tstc(void)
 {
 	unsigned char status;
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 	if (serial_buffer_active) {
 		return serial_buffered_tstc();
 	}
@@ -248,7 +248,7 @@ int serial_tstc(void)
 }
 
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 
 void serial_isr(void *arg)
 {

+ 1 - 1
cpu/mpc5xxx/ide.c

@@ -73,7 +73,7 @@ int ide_preinit (void)
 	*(vu_long *) MPC5XXX_ATA_PIO2 = reg;
 
 #ifdef CONFIG_IDE_RESET
-        init_ide_reset ();
+	init_ide_reset ();
 #endif /* CONFIG_IDE_RESET */
 
 	return (0);

+ 1 - 1
cpu/ppc4xx/405gp_pci.c

@@ -364,7 +364,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
  */
 static struct pci_config_table pci_405gp_config_table[] = {
 /*if VendID is 0 it terminates the table search (ie Walnut)*/
-#if CFG_PCI_SUBSYS_VENDORID
+#ifdef CFG_PCI_SUBSYS_VENDORID
 	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 #endif

+ 5 - 5
cpu/ppc4xx/cpu.c

@@ -70,17 +70,17 @@ int checkcpu (void)
 
 	get_sys_info(&sys_info);
 
-#if CONFIG_405GP
+#ifdef CONFIG_405GP
 	puts ("IBM PowerPC 405GP");
 	if (pvr == PVR_405GPR_RB) {
 		putc('r');
 	}
 	puts (" Rev. ");
 #endif
-#if CONFIG_405CR
+#ifdef CONFIG_405CR
 	puts ("IBM PowerPC 405CR Rev. ");
 #endif
-#if CONFIG_405EP
+#ifdef CONFIG_405EP
 	puts ("IBM PowerPC 405EP Rev. ");
 #endif
 	switch (pvr) {
@@ -89,7 +89,7 @@ int checkcpu (void)
 		putc('B');
 		break;
 	case PVR_405GP_RC:
-#if CONFIG_405CR
+#ifdef CONFIG_405CR
 	case PVR_405CR_RC:
 #endif
 		putc('C');
@@ -97,7 +97,7 @@ int checkcpu (void)
 	case PVR_405GP_RD:
 		putc('D');
 		break;
-#if CONFIG_405GP
+#ifdef CONFIG_405GP
 	case PVR_405GP_RE:
 		putc('E');
 		break;

+ 3 - 3
cpu/ppc4xx/serial.c

@@ -48,7 +48,7 @@
 #include <watchdog.h>
 #include "vecnum.h"
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 #include <malloc.h>
 #endif
 
@@ -351,7 +351,7 @@ int serial_tstc ()
 /*#define asyncRxBufferport1      ACTING_UART0_BASE+0x00 */
 
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 /*-----------------------------------------------------------------------------+
   | Fifo
   +-----------------------------------------------------------------------------*/
@@ -637,7 +637,7 @@ int serial_tstc ()
 }
 
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 
 void serial_isr (void *arg)
 {

+ 1 - 1
cpu/ppc4xx/speed.c

@@ -247,7 +247,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	unsigned long temp1;
 	unsigned long lfdiv;
 	unsigned long m;
-	unsigned long prbdv0;    
+	unsigned long prbdv0;
 
 	/* Extract configured divisors */
 	mfsdr( sdr_sdstp0,strp0 );

+ 9 - 10
cpu/s3c44b0/start.S

@@ -71,16 +71,15 @@ _armboot_start:
 	.word _start
 
 /*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
+ * These are defined in the board-specific linker script.
  */
-.globl _armboot_end_data
-_armboot_end_data:
-	.word armboot_end_data
-.globl _armboot_end
-_armboot_end:
-	.word armboot_end
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -130,7 +129,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq     stack_setup
 
 	ldr	r2, _armboot_start
-	ldr	r3, _armboot_end
+	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 

+ 4 - 4
cpu/sa1100/serial.c

@@ -66,7 +66,7 @@ void serial_setbrg (void)
 	Ser1UTCR1 = 0;
 	Ser1UTCR2 = (u32)reg;
 	Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE );
-#elif CONFIG_SERIAL3
+#elif defined(CONFIG_SERIAL3)
 	/* Wait until port is ready ... */
 	while (Ser3UTSR1 & UTSR1_TBY) {
 	}
@@ -107,7 +107,7 @@ void serial_putc (const char c)
 	while ((Ser1UTSR0 & UTSR0_TFS) == 0);
 
 	Ser1UTDR = c;
-#elif CONFIG_SERIAL3
+#elif defined(CONFIG_SERIAL3)
 	/* wait for room in the tx FIFO on SERIAL3 */
 	while ((Ser3UTSR0 & UTSR0_TFS) == 0);
 
@@ -128,7 +128,7 @@ int serial_tstc (void)
 {
 #ifdef CONFIG_SERIAL1
 	return Ser1UTSR1 & UTSR1_RNE;
-#elif CONFIG_SERIAL3
+#elif defined(CONFIG_SERIAL3)
 	return Ser3UTSR1 & UTSR1_RNE;
 #endif
 }
@@ -144,7 +144,7 @@ int serial_getc (void)
 	while (!(Ser1UTSR1 & UTSR1_RNE));
 
 	return (char) Ser1UTDR & 0xff;
-#elif CONFIG_SERIAL3
+#elif defined(CONFIG_SERIAL3)
 	while (!(Ser3UTSR1 & UTSR1_RNE));
 
 	return (char) Ser3UTDR & 0xff;

+ 4 - 4
disk/part.c

@@ -44,7 +44,7 @@
  */
 void dev_print (block_dev_desc_t *dev_desc)
 {
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 	uint64_t lba512; /* number of blocks if 512bytes block size */
 #else
 	lbaint_t lba512;
@@ -87,7 +87,7 @@ void dev_print (block_dev_desc_t *dev_desc)
 	if ((dev_desc->lba * dev_desc->blksz)>0L) {
 		ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem;
 		lbaint_t lba;
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 		if (dev_desc->lba48support)
 			lba = dev_desc->lba48;
 		else
@@ -103,11 +103,11 @@ void dev_print (block_dev_desc_t *dev_desc)
 		gb = mb / 1024;
 		gb_quot	= gb / 10;
 		gb_rem	= gb - (10 * gb_quot);
-#if CONFIG_LBA48
+#ifdef CONFIG_LBA48
 		if (dev_desc->lba48support)
 			printf ("            Supports 48-bit addressing\n");
 #endif
-#if CFG_64BIT_LBA && CFG_64BIT_VSPRINTF
+#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF)
 		printf ("            Capacity: %ld.%ld MB = %ld.%ld GB (%qd x %ld)\n",
 			mb_quot, mb_rem,
 			gb_quot, gb_rem,

+ 2 - 2
doc/README.adnpesc1

@@ -43,7 +43,7 @@ choices & assume that the monitor is placed at the end of a memory
 resource. So you must make sure TEXT_BASE is chosen appropriately.
 This is very important if you plan to move your memory to another
 place as configured at this time!
- 
+
 	-The heap is placed below the monitor (U-Boot code).
 	-Global data is placed below the heap.
 	-The stack is placed below global data (&grows down).
@@ -190,7 +190,7 @@ you have to check-up the next environment variables:
 2. appl_entry_addr
 
 	- Nios application area start address (usually in Flash)
-	- this is the startup address for autoboot 
+	- this is the startup address for autoboot
 	- each Nios application code we want to update will be copied
 	  to this address
 	- default is CFG_ADNPESC1_NIOS_APPL_ENTRY

+ 1 - 1
drivers/cs8900.h

@@ -47,7 +47,7 @@
   #define CS8900_OFF 0x02
   #define CS8900_BUS16_0  *(volatile u8 *)(CS8900_BASE+0x00)
   #define CS8900_BUS16_1  *(volatile u8 *)(CS8900_BASE+0x01)
-#elif  CS8900_BUS32
+#elif  defined(CS8900_BUS32)
   /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
   #define CS8900_REG u32
   #define CS8900_OFF 0x04

+ 1 - 1
drivers/pci.c

@@ -163,7 +163,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 
 	for (hose = hose_head; hose; hose = hose->next)
 	{
-#if CFG_SCSI_SCAN_BUS_REVERSE
+#ifdef CFG_SCSI_SCAN_BUS_REVERSE
 		for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 #else
 		for (bus = hose->first_busno; bus <= hose->last_busno; bus++)

+ 93 - 96
drivers/serial_pl010.c

@@ -41,137 +41,134 @@
 #define NUM_PORTS 2
 #define CONSOLE_PORT CONFIG_CONS_INDEX
 #define baudRate CONFIG_BAUDRATE
-static volatile unsigned char * const port[NUM_PORTS] = {(void*)(CFG_SERIAL0),
-                                                         (void*)(CFG_SERIAL1)};
+static volatile unsigned char *const port[NUM_PORTS] = {
+	(void *) (CFG_SERIAL0),
+	(void *) (CFG_SERIAL1)
+};
 
 
-static void pl010_putc(int portnum, char c);
-static int pl010_getc(int portnum);
-static int pl010_tstc(int portnum);
+static void pl010_putc (int portnum, char c);
+static int pl010_getc (int portnum);
+static int pl010_tstc (int portnum);
 
 
 int serial_init (void)
 {
-    unsigned int temp;
-    unsigned int divisor;
-
-    /*
-    ** First, disable everything.
-    */
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
-
-    /*
-    ** Set baud rate
-    **
-    */
-    switch (baudRate) {
-    case 9600:
-      divisor = UART_PL010_BAUD_9600;
-      break;
-
-    case 19200:
-      divisor = UART_PL010_BAUD_9600;
-      break;
-
-    case 38400:
-      divisor = UART_PL010_BAUD_38400;
-      break;
-
-    case 57600:
-      divisor = UART_PL010_BAUD_57600;
-      break;
-
-    case 115200:
-      divisor = UART_PL010_BAUD_115200;
-      break;
-
-    default:
-      divisor = UART_PL010_BAUD_38400;
-    }
- 
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRM, ((divisor & 0xf00) >> 8));
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
-
-    /*
-    ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
-    */
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRH,
-        (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
-
-    /*
-    ** Finally, enable the UART
-    */
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
-
-    return (0);
+	unsigned int divisor;
+
+	/*
+	 ** First, disable everything.
+	 */
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
+
+	/*
+	 ** Set baud rate
+	 **
+	 */
+	switch (baudRate) {
+	case 9600:
+		divisor = UART_PL010_BAUD_9600;
+		break;
+
+	case 19200:
+		divisor = UART_PL010_BAUD_9600;
+		break;
+
+	case 38400:
+		divisor = UART_PL010_BAUD_38400;
+		break;
+
+	case 57600:
+		divisor = UART_PL010_BAUD_57600;
+		break;
+
+	case 115200:
+		divisor = UART_PL010_BAUD_115200;
+		break;
+
+	default:
+		divisor = UART_PL010_BAUD_38400;
+	}
+
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM,
+		  ((divisor & 0xf00) >> 8));
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
+
+	/*
+	 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
+	 */
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH,
+		  (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
+
+	/*
+	 ** Finally, enable the UART
+	 */
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
+
+	return (0);
 }
 
-void
-serial_putc(const char c)
+void serial_putc (const char c)
 {
 	if (c == '\n')
-		pl010_putc(CONSOLE_PORT, '\r');
+		pl010_putc (CONSOLE_PORT, '\r');
 
-	pl010_putc(CONSOLE_PORT, c);
+	pl010_putc (CONSOLE_PORT, c);
 }
 
-void
-serial_puts (const char *s)
+void serial_puts (const char *s)
 {
 	while (*s) {
 		serial_putc (*s++);
 	}
 }
 
-int
-serial_getc(void)
+int serial_getc (void)
 {
-	return pl010_getc(CONSOLE_PORT);
+	return pl010_getc (CONSOLE_PORT);
 }
 
-int
-serial_tstc(void)
+int serial_tstc (void)
 {
-	return pl010_tstc(CONSOLE_PORT);
+	return pl010_tstc (CONSOLE_PORT);
 }
 
-void
-serial_setbrg (void)
+void serial_setbrg (void)
 {
 }
 
-static void pl010_putc(int portnum, char c)
+static void pl010_putc (int portnum, char c)
 {
-    /* Wait until there is space in the FIFO */
-    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
-    
-    /* Send the character */
-    IO_WRITE(port[portnum] + UART_PL01x_DR, c);
+	/* Wait until there is space in the FIFO */
+	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
+
+	/* Send the character */
+	IO_WRITE (port[portnum] + UART_PL01x_DR, c);
 }
 
-static int pl010_getc(int portnum)
+static int pl010_getc (int portnum)
 {
-    unsigned int data;
-
-    /* Wait until there is data in the FIFO */
-    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
-    
-    data = IO_READ(port[portnum] + UART_PL01x_DR);
-    
-    /* Check for an error flag */
-    if (data & 0xFFFFFF00)
-    {
-        /* Clear the error */
-        IO_WRITE(port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
-        return -1;
-    }
-    
-    return (int)data;
+	unsigned int data;
+
+	/* Wait until there is data in the FIFO */
+	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+
+	data = IO_READ (port[portnum] + UART_PL01x_DR);
+
+	/* Check for an error flag */
+	if (data & 0xFFFFFF00) {
+		/* Clear the error */
+		IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
+		return -1;
+	}
+
+	return (int) data;
 }
 
-static int pl010_tstc(int portnum)
+static int pl010_tstc (int portnum)
 {
-    return !(IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+	return !(IO_READ (port[portnum] + UART_PL01x_FR) &
+		 UART_PL01x_FR_RXFE);
 }
 
 #endif

+ 86 - 88
drivers/serial_pl011.c

@@ -38,138 +38,136 @@
 #define IO_READ(addr) (*(volatile unsigned int *)(addr))
 
 /*
- * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 
+ * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1
  * Versatile PB has four UARTs.
  */
 #define NUM_PORTS 2
 #define CONSOLE_PORT CONFIG_CONS_INDEX
 #define baudRate CONFIG_BAUDRATE
-static volatile unsigned char * const port[NUM_PORTS] = {(void*)(CFG_SERIAL0),
-                                                         (void*)(CFG_SERIAL1)};
+static volatile unsigned char *const port[NUM_PORTS] = {
+	(void *) (CFG_SERIAL0),
+	(void *) (CFG_SERIAL1)
+};
 
 
-static void pl011_putc(int portnum, char c);
-static int pl011_getc(int portnum);
-static int pl011_tstc(int portnum);
+static void pl011_putc (int portnum, char c);
+static int pl011_getc (int portnum);
+static int pl011_tstc (int portnum);
 
 
 int serial_init (void)
 {
-    unsigned int temp;
-    unsigned int divider;
-    unsigned int remainder;
-    unsigned int fraction;
-
-    /*
-    ** First, disable everything.
-    */
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
-
-    /*
-    ** Set baud rate
-    **
-    ** IBRD = UART_CLK / (16 * BAUD_RATE)
-    ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
-    */
+	unsigned int temp;
+	unsigned int divider;
+	unsigned int remainder;
+	unsigned int fraction;
+
+	/*
+	 ** First, disable everything.
+	 */
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
+
+	/*
+	 ** Set baud rate
+	 **
+	 ** IBRD = UART_CLK / (16 * BAUD_RATE)
+	 ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
+	 */
 #ifdef CONFIG_VERSATILE
-    temp      = 16 * baudRate;
-    divider   = 24000000 / temp;
-    remainder = 24000000 % temp;
-    temp      = (8 * remainder) / baudRate;
-    fraction  = (temp >> 1) + (temp & 1);
+	temp = 16 * baudRate;
+	divider = 24000000 / temp;
+	remainder = 24000000 % temp;
+	temp = (8 * remainder) / baudRate;
+	fraction = (temp >> 1) + (temp & 1);
 #endif
 #ifdef CONFIG_INTEGRATOR
-    temp      = 16 * baudRate;
-    divider   = 14745600 / temp;
-    remainder = 14745600 % temp;
-    temp      = (8 * remainder) / baudRate;
-    fraction  = (temp >> 1) + (temp & 1);
+	temp = 16 * baudRate;
+	divider = 14745600 / temp;
+	remainder = 14745600 % temp;
+	temp = (8 * remainder) / baudRate;
+	fraction = (temp >> 1) + (temp & 1);
 #endif
- 
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
-
-    /*
-    ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
-    */
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_LCRH,
-        (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
-
-    /*
-    ** Finally, enable the UART
-    */
-    IO_WRITE(port[CONSOLE_PORT] + UART_PL011_CR,
-        (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE));
-
-    return (0);
+
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
+
+	/*
+	 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
+	 */
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
+		  (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
+
+	/*
+	 ** Finally, enable the UART
+	 */
+	IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR,
+		  (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
+		   UART_PL011_CR_RXE));
+
+	return (0);
 }
 
-void
-serial_putc(const char c)
+void serial_putc (const char c)
 {
 	if (c == '\n')
-		pl011_putc(CONSOLE_PORT, '\r');
+		pl011_putc (CONSOLE_PORT, '\r');
 
-	pl011_putc(CONSOLE_PORT, c);
+	pl011_putc (CONSOLE_PORT, c);
 }
 
-void
-serial_puts (const char *s)
+void serial_puts (const char *s)
 {
 	while (*s) {
 		serial_putc (*s++);
 	}
 }
 
-int
-serial_getc(void)
+int serial_getc (void)
 {
-	return pl011_getc(CONSOLE_PORT);
+	return pl011_getc (CONSOLE_PORT);
 }
 
-int
-serial_tstc(void)
+int serial_tstc (void)
 {
-	return pl011_tstc(CONSOLE_PORT);
+	return pl011_tstc (CONSOLE_PORT);
 }
 
-void
-serial_setbrg (void)
+void serial_setbrg (void)
 {
 }
 
-static void pl011_putc(int portnum, char c)
+static void pl011_putc (int portnum, char c)
 {
-    /* Wait until there is space in the FIFO */
-    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
-    
-    /* Send the character */
-    IO_WRITE(port[portnum] + UART_PL01x_DR, c);
+	/* Wait until there is space in the FIFO */
+	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
+
+	/* Send the character */
+	IO_WRITE (port[portnum] + UART_PL01x_DR, c);
 }
 
-static int pl011_getc(int portnum)
+static int pl011_getc (int portnum)
 {
-    unsigned int data;
-
-    /* Wait until there is data in the FIFO */
-    while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
-    
-    data = IO_READ(port[portnum] + UART_PL01x_DR);
-    
-    /* Check for an error flag */
-    if (data & 0xFFFFFF00)
-    {
-        /* Clear the error */
-        IO_WRITE(port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
-        return -1;
-    }
-    
-    return (int)data;
+	unsigned int data;
+
+	/* Wait until there is data in the FIFO */
+	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+
+	data = IO_READ (port[portnum] + UART_PL01x_DR);
+
+	/* Check for an error flag */
+	if (data & 0xFFFFFF00) {
+		/* Clear the error */
+		IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
+		return -1;
+	}
+
+	return (int) data;
 }
 
-static int pl011_tstc(int portnum)
+static int pl011_tstc (int portnum)
 {
-    return !(IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+	return !(IO_READ (port[portnum] + UART_PL01x_FR) &
+		 UART_PL01x_FR_RXFE);
 }
 
 #endif

+ 10 - 10
drivers/serial_pl011.h

@@ -23,11 +23,11 @@
  */
 
 /*
- * ARM PrimeCell UART's (PL010 & PL011) 
+ * ARM PrimeCell UART's (PL010 & PL011)
  * ------------------------------------
- *  
+ *
  *  Definitions common to both PL010 & PL011
- * 
+ *
  */
 #define UART_PL01x_DR                   0x00	 /*  Data read or written from the interface. */
 #define UART_PL01x_RSR                  0x04	 /*  Receive status register (Read). */
@@ -46,9 +46,9 @@
 #define UART_PL01x_FR_BUSY              0x08
 #define UART_PL01x_FR_TMSK              (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
 
-/* 
+/*
  *  PL010 definitions
- * 
+ *
  */
 #define UART_PL010_LCRH                 0x08	 /*  Line control register, high byte. */
 #define UART_PL010_LCRM                 0x0C	 /*  Line control register, middle byte. */
@@ -57,7 +57,7 @@
 #define UART_PL010_IIR                  0x1C	 /*  Interrupt indentification register (Read). */
 #define UART_PL010_ICR                  0x1C	 /*  Interrupt clear register (Write). */
 #define UART_PL010_ILPR                 0x20	 /*  IrDA low power counter register. */
- 
+
 #define UART_PL010_CR_LPE               (1 << 7)
 #define UART_PL010_CR_RTIE              (1 << 6)
 #define UART_PL010_CR_TIE               (1 << 5)
@@ -66,7 +66,7 @@
 #define UART_PL010_CR_IIRLP             (1 << 2)
 #define UART_PL010_CR_SIREN             (1 << 1)
 #define UART_PL010_CR_UARTEN            (1 << 0)
- 
+
 #define UART_PL010_LCRH_WLEN_8          (3 << 5)
 #define UART_PL010_LCRH_WLEN_7          (2 << 5)
 #define UART_PL010_LCRH_WLEN_6          (1 << 5)
@@ -89,9 +89,9 @@
 #define UART_PL010_BAUD_4800              191
 #define UART_PL010_BAUD_2400              383
 #define UART_PL010_BAUD_1200              767
-/* 
+/*
  *  PL011 definitions
- * 
+ *
  */
 #define UART_PL011_IBRD                 0x24
 #define UART_PL011_FBRD                 0x28
@@ -99,7 +99,7 @@
 #define UART_PL011_CR                   0x30
 #define UART_PL011_IMSC                 0x38
 #define UART_PL011_PERIPH_ID0           0xFE0
- 
+
 #define UART_PL011_LCRH_SPS             (1 << 7)
 #define UART_PL011_LCRH_WLEN_8          (3 << 5)
 #define UART_PL011_LCRH_WLEN_7          (2 << 5)

+ 37 - 37
drivers/smc91111.c

@@ -7,7 +7,7 @@
  . Rolf Offermanns <rof@sysgo.de>
  .
  . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- .       Developed by Simple Network Magic Corporation (SNMC)
+ .	 Developed by Simple Network Magic Corporation (SNMC)
  . Copyright (C) 1996 by Erik Stahlman (ES)
  .
  . This program is free software; you can redistribute it and/or modify
@@ -17,12 +17,12 @@
  .
  . This program is distributed in the hope that it will be useful,
  . but WITHOUT ANY WARRANTY; without even the implied warranty of
- . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  . GNU General Public License for more details.
  .
  . You should have received a copy of the GNU General Public License
  . along with this program; if not, write to the Free Software
- . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
  .
  . Information contained in this file was obtained from the LAN91C111
  . manual from SMC.  To get a copy, if you really want one, you can find
@@ -36,27 +36,27 @@
  .   EEPROM interface for configuration
  .
  . Arguments:
- . 	io	= for the base address
+ .	io	= for the base address
  .	irq	= for the IRQ
  .
  . author:
- . 	Erik Stahlman				( erik@vt.edu )
- . 	Daris A Nevil				( dnevil@snmc.com )
+ .	Erik Stahlman				( erik@vt.edu )
+ .	Daris A Nevil				( dnevil@snmc.com )
  .
  .
  . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
  .
  . Sources:
- .    o   SMSC LAN91C111 databook (www.smsc.com)
- .    o   smc9194.c by Erik Stahlman
- .    o   skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
+ .    o	  SMSC LAN91C111 databook (www.smsc.com)
+ .    o	  smc9194.c by Erik Stahlman
+ .    o	  skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
  .
  . History:
- .      06/19/03  Richard Woodruff Made u-boot environment aware and added mac addr checks.
+ .	06/19/03  Richard Woodruff Made u-boot environment aware and added mac addr checks.
  .	10/17/01  Marco Hasewinkel Modify for DNP/1110
- .	07/25/01  Woojung Huh      Modify for ADS Bitsy
- .	04/25/01  Daris A Nevil    Initial public release through SMSC
- .	03/16/01  Daris A Nevil    Modified smc9194.c for use with LAN91C111
+ .	07/25/01  Woojung Huh	   Modify for ADS Bitsy
+ .	04/25/01  Daris A Nevil	   Initial public release through SMSC
+ .	03/16/01  Daris A Nevil	   Modified smc9194.c for use with LAN91C111
  ----------------------------------------------------------------------------*/
 
 #include <common.h>
@@ -113,7 +113,7 @@ static const char version[] =
 
 /*------------------------------------------------------------------------
  .
- . The internal workings of the driver.  If you are changing anything
+ . The internal workings of the driver.	 If you are changing anything
  . here with the SMC stuff, you should have the datasheet and know
  . what you are doing.
  .
@@ -138,7 +138,7 @@ static const char version[] =
 
 #define ETH_ZLEN 60
 
-#ifdef  CONFIG_SMC_USE_32_BIT
+#ifdef	CONFIG_SMC_USE_32_BIT
 #define USE_32_BIT  1
 #else
 #undef USE_32_BIT
@@ -253,7 +253,7 @@ void smc_get_macaddr( byte *addr ) {
 #endif /* 0 */
 
 /***********************************************
- * Show available memory                       *
+ * Show available memory		       *
  ***********************************************/
 void dump_memory_info(void)
 {
@@ -337,8 +337,8 @@ static inline void smc_wait_mmu_release_complete (void)
 /*
  . Function: smc_reset( void )
  . Purpose:
- .  	This sets the SMC91111 chip to its normal state, hopefully from whatever
- . 	mess that any other DOS driver has put it in.
+ .	This sets the SMC91111 chip to its normal state, hopefully from whatever
+ .	mess that any other DOS driver has put it in.
  .
  . Maybe I should reset more registers to defaults in here?  SOFTRST  should
  . do that for me.
@@ -436,7 +436,7 @@ static void smc_enable()
  .   (1) maybe utilize power down mode.
  .	Why not yet?  Because while the chip will go into power down mode,
  .	the manual says that it will wake up in response to any I/O requests
- .	in the register space.   Empirical results do not show this working.
+ .	in the register space.	 Empirical results do not show this working.
 */
 static void smc_shutdown()
 {
@@ -459,7 +459,7 @@ static void smc_shutdown()
  .	This sends the actual packet to the SMC9xxx chip.
  .
  . Algorithm:
- . 	First, see if a saved_skb is available.
+ .	First, see if a saved_skb is available.
  .		( this should NOT be called if there is no 'saved_skb'
  .	Now, find the packet number that the chip allocated
  .	Point the data pointers at it in memory
@@ -467,9 +467,9 @@ static void smc_shutdown()
  .	Dump the packet to chip memory
  .	Check if a last byte is needed ( odd length packet )
  .		if so, set the control flag right
- . 	Tell the card to send it
+ .	Tell the card to send it
  .	Enable the transmit interrupt, so I know if it failed
- . 	Free the kernel data if I actually sent it.
+ .	Free the kernel data if I actually sent it.
 */
 static int smc_send_packet (volatile void *packet, int packet_length)
 {
@@ -512,9 +512,9 @@ static int smc_send_packet (volatile void *packet, int packet_length)
 	SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
 
 	/* FIXME: the ALLOC_INT bit never gets set *
-	 * so the following will always give a     *
-	 * memory allocation error.                *
-	 * same code works in armboot though       *
+	 * so the following will always give a	   *
+	 * memory allocation error.		   *
+	 * same code works in armboot though	   *
 	 * -ro
 	 */
 
@@ -583,7 +583,7 @@ again:
 	/* send the actual data
 	   . I _think_ it's faster to send the longs first, and then
 	   . mop up by sending the last word.  It depends heavily
-	   . on alignment, at least on the 486.  Maybe it would be
+	   . on alignment, at least on the 486.	 Maybe it would be
 	   . a good idea to check which is optimal?  But that could take
 	   . almost as much time as is saved?
 	 */
@@ -596,7 +596,7 @@ again:
 	SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
 #endif /* USE_32_BIT */
 
-	/* Send the last byte, if there is one.   */
+	/* Send the last byte, if there is one.	  */
 	if ((length & 1) == 0) {
 		SMC_outw (0, SMC91111_DATA_REG);
 	} else {
@@ -690,7 +690,7 @@ static int smc_open (bd_t * bd)
 
 	err = smc_get_ethaddr (bd);	/* set smc_mac_addr, and sync it with u-boot globals */
 	if (err < 0) {
-		memset (bd->bi_enetaddr, 0, 6);	/* hack to make error stick! upper code will abort if not set */
+		memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */
 		return (-1);	/* upper code ignores this, but NOT bi_enetaddr */
 	}
 #ifdef USE_32_BIT
@@ -723,10 +723,10 @@ static int smc_open (bd_t * bd)
 */
 static int smc_rcv()
 {
-	int 	packet_number;
+	int	packet_number;
 	word	status;
 	word	packet_length;
-	int     is_error = 0;
+	int	is_error = 0;
 #ifdef USE_32_BIT
 	dword stat_len;
 #endif
@@ -749,8 +749,8 @@ static int smc_rcv()
 	status = stat_len & 0xffff;
 	packet_length = stat_len >> 16;
 #else
-	status 		= SMC_inw( SMC91111_DATA_REG );
-	packet_length 	= SMC_inw( SMC91111_DATA_REG );
+	status		= SMC_inw( SMC91111_DATA_REG );
+	packet_length	= SMC_inw( SMC91111_DATA_REG );
 #endif
 
 	packet_length &= 0x07ff;  /* mask off top bits */
@@ -773,7 +773,7 @@ static int smc_rcv()
 		/* QUESTION:  Like in the TX routine, do I want
 		   to send the DWORDs or the bytes first, or some
 		   mixture.  A mixture might improve already slow PIO
-		   performance  */
+		   performance	*/
 		SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
 		/* read the left over bytes */
 		if (packet_length & 3) {
@@ -825,7 +825,7 @@ static int smc_rcv()
  . smc_close
  .
  . this makes the board clean up everything that it can
- . and not talk to the outside world.   Caused by
+ . and not talk to the outside world.	Caused by
  . an 'ifconfig ethX down'
  .
  -----------------------------------------------------*/
@@ -1380,7 +1380,7 @@ int smc_get_ethaddr (bd_t * bd)
 		s = s_env_mac;
 	}
 
-	for (reg = 0; reg < 6; ++reg) {	/* turn string into mac value */
+	for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
 		v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
 		if (s)
 			s = (*e) ? e + 1 : e;
@@ -1403,7 +1403,7 @@ int smc_get_ethaddr (bd_t * bd)
 		v_mac = v_env_mac;	/* always use a good env over a ROM */
 	}
 
-	if (env_present && rom_valid) {	/* if both env and ROM are good */
+	if (env_present && rom_valid) { /* if both env and ROM are good */
 		if (memcmp (v_env_mac, v_rom_mac, 6) != 0) {
 			printf ("\nWarning: MAC addresses don't match:\n");
 			printf ("\tHW MAC address:  "
@@ -1422,7 +1422,7 @@ int smc_get_ethaddr (bd_t * bd)
 	memcpy (bd->bi_enetaddr, v_mac, 6);	/* update global address to match env (allows env changing) */
 	smc_set_mac_addr (v_mac);	/* use old function to update smc default */
 	PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
-                v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
+		v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
 	return (0);
 }
 

+ 1 - 1
drivers/usbtty.c

@@ -314,7 +314,7 @@ int drv_usbtty_init (void)
 	int rc;
 	char * sn;
 	int snlen;
-	
+
 	if (!(sn = getenv("serial#"))) {
 		sn = "000000000000";
 	}

+ 1 - 1
include/ata.h

@@ -208,7 +208,7 @@ typedef struct hd_driveid {
 	unsigned short	word92;		/* reserved (word 92) */
 	unsigned short	hw_config;	/* hardware config */
 	unsigned short	words94_99[6];/* reserved words 94-99 */
-	//unsigned long long  lba48_capacity; /* 4 16bit values containing lba 48 total number of sectors */
+	/*unsigned long long  lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
 	unsigned short	lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
 	unsigned short	words104_125[22];/* reserved words 104-125 */
 	unsigned short	last_lun;	/* reserved (word 126) */

+ 2 - 2
include/common.h

@@ -134,7 +134,7 @@ typedef void (interrupt_handler_t)(void *);
  * Function Prototypes
  */
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 void	serial_buffered_init (void);
 void	serial_buffered_putc (const char);
 void	serial_buffered_puts (const char *);
@@ -459,7 +459,7 @@ int	init_timebase (void);
 
 /* lib_generic/vsprintf.c */
 ulong	simple_strtoul(const char *cp,char **endp,unsigned int base);
-#if CFG_64BIT_VSPRINTF
+#ifdef CFG_64BIT_VSPRINTF
 unsigned long long	simple_strtoull(const char *cp,char **endp,unsigned int base);
 #endif
 long	simple_strtol(const char *cp,char **endp,unsigned int base);

+ 2 - 2
include/configs/MPC8266ADS.h

@@ -175,7 +175,7 @@
 #define CONFIG_BOOT_ROOT_INITRD 0	/* Use ram disk for the root file system */
 #define CONFIG_BOOT_ROOT_NFS	1	/* Use a NFS mounted root file system */
 
-#if CONFIG_BOOT_ROOT_INITRD
+#ifdef CONFIG_BOOT_ROOT_INITRD
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \
@@ -185,7 +185,7 @@
 	"bootm"
 #endif /* CONFIG_BOOT_ROOT_INITRD */
 
-#if CONFIG_BOOT_ROOT_NFS
+#ifdef CONFIG_BOOT_ROOT_NFS
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \

+ 31 - 31
include/configs/OCOTEA.h

@@ -21,7 +21,7 @@
  */
 
 /************************************************************************
- * 1 March 2004  Travis B. Sawyer <tsawyer@sandburst.com>
+ * 1 March 2004	 Travis B. Sawyer <tsawyer@sandburst.com>
  * Adapted to current Das U-Boot source
  ***********************************************************************/
 
@@ -37,7 +37,7 @@
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
 #define CONFIG_OCOTEA		1	    /* Board is ebony		*/
-#define CONFIG_440_GX           1           /* Specifc GX support       */
+#define CONFIG_440_GX		1	    /* Specifc GX support	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
@@ -68,8 +68,8 @@
 #define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
 
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
 
 #define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
 #define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
@@ -110,8 +110,8 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM       1        /* Use SPD EEPROM for setup     */
-#define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
+#define CONFIG_SPD_EEPROM	1	 /* Use SPD EEPROM for setup	 */
+#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -129,7 +129,7 @@
 #define CFG_ENV_IS_IN_NVRAM	1	    /* Environment uses NVRAM	*/
 #undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
 #undef	CFG_ENV_IS_IN_EEPROM		    /* ... not in EEPROM	*/
-#define CONFIG_ENV_OVERWRITE    1
+#define CONFIG_ENV_OVERWRITE	1
 
 #define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
 #define CFG_ENV_ADDR		\
@@ -146,18 +146,18 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_NET_MULTI	1
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-#define CONFIG_PHY1_ADDR        2
-#define CONFIG_PHY2_ADDR        0x10
-#define CONFIG_PHY3_ADDR        0x18
-#define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR           10.1.2.3
-#define CONFIG_ETHADDR          00:04:AC:E3:28:8A
-#define CONFIG_ETHADDR1         00:04:AC:E3:28:8B
-#define CONFIG_ETHADDR2         00:04:AC:E3:28:8C
-#define CONFIG_ETHADDR3         00:04:AC:E3:28:8D
-#define CFG_RX_ETH_BUFFER       32        /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SERVERIP         10.1.2.2
+#define CONFIG_PHY1_ADDR	2
+#define CONFIG_PHY2_ADDR	0x10
+#define CONFIG_PHY3_ADDR	0x18
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		10.1.2.3
+#define CONFIG_ETHADDR		00:04:AC:E3:28:8A
+#define CONFIG_ETHADDR1		00:04:AC:E3:28:8B
+#define CONFIG_ETHADDR2		00:04:AC:E3:28:8C
+#define CONFIG_ETHADDR3		00:04:AC:E3:28:8D
+#define CFG_RX_ETH_BUFFER	32	  /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SERVERIP		10.1.2.2
 
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -167,10 +167,10 @@
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_BEDBUG	| \
-                                CFG_CMD_PING    | \
-				CFG_CMD_DIAG    | \
-                                CFG_CMD_MII     | \
-                                CFG_CMD_NET     | \
+				CFG_CMD_PING	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
 				CFG_CMD_ELF	)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -206,17 +206,17 @@
  *-----------------------------------------------------------------------
  */
 /* General PCI */
-#define CONFIG_PCI			            /* include pci support	        */
-#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_PCI				    /* include pci support		*/
+#define CONFIG_PCI_PNP				/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
-#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		    /* let board init pci target    */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
 /*
  * For booting Linux, the board info and command line data

+ 1 - 1
include/configs/TOP860.h

@@ -364,7 +364,7 @@
  *	5	0		00000
  */
 #define SCCR_MASK	0
-#if CONFIG_EBDF
+#ifdef CONFIG_EBDF
  #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
 #else
  #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)

+ 2 - 2
include/configs/gcplus.h

@@ -156,14 +156,14 @@
 #define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
 #else
-/* REVISIT: This doesn't work on ADS GCPlus just yet:
+/* REVISIT: This doesn't work on ADS GCPlus just yet: */
 #define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
 #define CFG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
 #define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
 #define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
 #define CFG_MAX_FLASH_SECT      128     /* max # of sectors on one chip */
-//#define CFG_FLASH_PROTECTION    1       /* hardware flash protection    */
+/*#define CFG_FLASH_PROTECTION    1       /--* hardware flash protection    */
 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 #endif
 

+ 26 - 25
include/configs/integratorap.h

@@ -52,6 +52,7 @@
  * Size of malloc() pool
  */
 #define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * PL010 Configuration
@@ -63,9 +64,9 @@
 #define CFG_SERIAL0		0x16000000
 #define CFG_SERIAL1		0x17000000
 
-//#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI)
-//#define CONFIG_NET_MULTI
-//#define CONFIG_BOOTP_MASK       CONFIG_BOOTP_DEFAULT
+/*#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
+/*#define CONFIG_NET_MULTI */
+/*#define CONFIG_BOOTP_MASK       CONFIG_BOOTP_DEFAULT */
 
 #define CONFIG_COMMANDS	(CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
 
@@ -74,7 +75,7 @@
 #include <cmd_confdefs.h>
 
 #define CONFIG_BOOTDELAY        2
-#define CONFIG_BOOTARGS         "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" 
+#define CONFIG_BOOTARGS         "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
 #define CONFIG_BOOTCOMMAND      ""
 
 /*
@@ -129,7 +130,7 @@
  * PCI definitions
  */
 
-//#define CONFIG_PCI			/* include pci support			*/
+/*#define CONFIG_PCI			/--* include pci support			*/
 #undef CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 #define DEBUG
@@ -141,28 +142,28 @@
 #define INTEGRATOR_BOOT_ROM_BASE	0x20000000
 #define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
 
-// PCI Base area
+/* PCI Base area */
 #define INTEGRATOR_PCI_BASE		0x40000000
 #define INTEGRATOR_PCI_SIZE		0x3FFFFFFF
 
-// memory map as seen by the CPU on the local bus
-#define CPU_PCI_IO_ADRS		0x60000000 	// PCI I/O space base
-#define CPU_PCI_IO_SIZE		0x10000	
+/* memory map as seen by the CPU on the local bus */
+#define CPU_PCI_IO_ADRS		0x60000000 	/* PCI I/O space base */
+#define CPU_PCI_IO_SIZE		0x10000
 
-#define CPU_PCI_CNFG_ADRS	0x61000000	// PCI config space
+#define CPU_PCI_CNFG_ADRS	0x61000000	/* PCI config space */
 #define CPU_PCI_CNFG_SIZE	0x1000000
 
-#define PCI_MEM_BASE            0x40000000   // 512M to xxx
-//  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
-#define INTEGRATOR_PCI_IO_BASE  0x60000000   // 16M to xxx
-//  unused (128-16)M from B1000000-B7FFFFFF
-#define PCI_CONFIG_BASE         0x61000000   // 16M to xxx
-//  unused ((128-16)M - 64K) from XXX
+#define PCI_MEM_BASE            0x40000000   /* 512M to xxx */
+/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
+#define INTEGRATOR_PCI_IO_BASE  0x60000000   /* 16M to xxx */
+/*  unused (128-16)M from B1000000-B7FFFFFF */
+#define PCI_CONFIG_BASE         0x61000000   /* 16M to xxx */
+/*  unused ((128-16)M - 64K) from XXX */
 
 #define PCI_V3_BASE             0x62000000
 
-// V3 PCI bridge controller
-#define V3_BASE			0x62000000    // V360EPC registers
+/* V3 PCI bridge controller */
+#define V3_BASE			0x62000000    /* V360EPC registers */
 
 #define PCI_ENET0_IOADDR	(CPU_PCI_IO_ADRS)
 #define PCI_ENET0_MEMADDR	(PCI_MEM_BASE)
@@ -221,16 +222,16 @@
 #define V3_MAIL_RD_STAT         0x000000DA
 #define V3_QBA_MAP              0x000000DC
 
-// SYSTEM register bits
+/* SYSTEM register bits */
 #define V3_SYSTEM_M_RST_OUT             (1 << 15)
 #define V3_SYSTEM_M_LOCK                (1 << 14)
 
-//  PCI_CFG bits
+/*  PCI_CFG bits */
 #define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
 #define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
 #define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
 
-// PCI MAP register bits (PCI -> Local bus)
+/* PCI MAP register bits (PCI -> Local bus) */
 #define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
 #define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
 #define V3_PCI_MAP_M_ROM_SIZE           (1 << 11 | 1 << 10)
@@ -239,20 +240,20 @@
 #define V3_PCI_MAP_M_REG_EN             (1 << 1)
 #define V3_PCI_MAP_M_ENABLE             (1 << 0)
 
-// 9 => 512M window size
+/* 9 => 512M window size */
 #define V3_PCI_MAP_M_ADR_SIZE_512M      0x00000090
 
-// A => 1024M window size
+/* A => 1024M window size */
 #define V3_PCI_MAP_M_ADR_SIZE_1024M     0x000000A0
 
-// LB_BASE register bits (Local bus -> PCI)
+/* LB_BASE register bits (Local bus -> PCI) */
 #define V3_LB_BASE_M_MAP_ADR            0xFFF00000
 #define V3_LB_BASE_M_SWAP               (1 << 8 | 1 << 9)
 #define V3_LB_BASE_M_ADR_SIZE           0x000000F0
 #define V3_LB_BASE_M_PREFETCH           (1 << 3)
 #define V3_LB_BASE_M_ENABLE             (1 << 0)
 
-// PCI COMMAND REGISTER bits
+/* PCI COMMAND REGISTER bits */
 #define V3_COMMAND_M_FBB_EN             (1 << 9)
 #define V3_COMMAND_M_SERR_EN            (1 << 8)
 #define V3_COMMAND_M_PAR_EN             (1 << 6)

+ 2 - 1
include/configs/integratorcp.h

@@ -52,6 +52,7 @@
  * Size of malloc() pool
  */
 #define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -78,7 +79,7 @@
 #include <cmd_confdefs.h>
 
 #define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0" 
+#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
 #define CONFIG_BOOTCOMMAND "bootp ; bootm"
 
 /*

+ 2 - 2
include/configs/ppmc8260.h

@@ -241,7 +241,7 @@
 #define CONFIG_BOOT_ROOT_INITRD 0	/* Use ram disk for the root file system */
 #define CONFIG_BOOT_ROOT_NFS	1	/* Use a NFS mounted root file system */
 
-#if CONFIG_BOOT_ROOT_INITRD
+#ifdef CONFIG_BOOT_ROOT_INITRD
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \
@@ -251,7 +251,7 @@
 	"bootm"
 #endif /* CONFIG_BOOT_ROOT_INITRD */
 
-#if CONFIG_BOOT_ROOT_NFS
+#ifdef CONFIG_BOOT_ROOT_NFS
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \

+ 2 - 2
include/configs/sacsng.h

@@ -446,7 +446,7 @@
 #define CONFIG_BOOT_ROOT_INITRD 0	/* Use ram disk for the root file system */
 #define CONFIG_BOOT_ROOT_NFS	1	/* Use a NFS mounted root file system */
 
-#if CONFIG_BOOT_ROOT_INITRD
+#ifdef CONFIG_BOOT_ROOT_INITRD
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \
@@ -457,7 +457,7 @@
 	"bootm"
 #endif /* CONFIG_BOOT_ROOT_INITRD */
 
-#if CONFIG_BOOT_ROOT_NFS
+#ifdef CONFIG_BOOT_ROOT_NFS
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \

+ 2 - 2
include/configs/sbc8260.h

@@ -392,7 +392,7 @@
 #define CONFIG_BOOT_ROOT_INITRD 0	/* Use ram disk for the root file system */
 #define CONFIG_BOOT_ROOT_NFS	1	/* Use a NFS mounted root file system */
 
-#if CONFIG_BOOT_ROOT_INITRD
+#ifdef CONFIG_BOOT_ROOT_INITRD
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \
@@ -402,7 +402,7 @@
 	"bootm"
 #endif /* CONFIG_BOOT_ROOT_INITRD */
 
-#if CONFIG_BOOT_ROOT_NFS
+#ifdef CONFIG_BOOT_ROOT_NFS
 #define CONFIG_BOOTCOMMAND \
 	"version;" \
 	"echo;" \

+ 7 - 6
include/configs/versatile.h

@@ -72,6 +72,7 @@
  * Size of malloc() pool
  */
 #define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -94,7 +95,7 @@
 
 #define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY)
 
-//#define CONFIG_COMMANDS	(CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+/*#define CONFIG_COMMANDS	(CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */
 
 #define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
 
@@ -102,15 +103,15 @@
 #include <cmd_confdefs.h>
 
 #define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0" 
-//#define CONFIG_BOOTCOMMAND "bootp ; bootm"
+#define CONFIG_BOOTARGS	"root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
+/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */
 
 /*
  * Static configuration when assigning fixed address
  */
-//#define CONFIG_NETMASK	255.255.255.0	/* talk on MY local net */
-//#define CONFIG_IPADDR		xx.xx.xx.xx	/* static IP I currently own */
-//#define CONFIG_SERVERIP	xx.xx.xx.xx	/* current IP of my dev pc */
+/*#define CONFIG_NETMASK	255.255.255.0	/--* talk on MY local net */
+/*#define CONFIG_IPADDR		xx.xx.xx.xx	/--* static IP I currently own */
+/*#define CONFIG_SERVERIP	xx.xx.xx.xx	/--* current IP of my dev pc */
 #define CONFIG_BOOTFILE	    "/tftpboot/uImage" /* file to load */
 
 

+ 1 - 1
include/ide.h

@@ -38,7 +38,7 @@
 
 #endif /* CONFIG_IDE_LED */
 
-#if CFG_64BIT_LBA
+#ifdef CFG_64BIT_LBA
 typedef uint64_t lbaint_t;
 #else
 typedef ulong lbaint_t;

+ 27 - 24
include/part.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -25,22 +25,25 @@
 
 
 typedef struct block_dev_desc {
-	int           if_type;    /* type of the interface */
-	int           dev;        /* device number */
-	unsigned char part_type;  /* partition type */
-	unsigned char target;			/* target SCSI ID */
-	unsigned char lun;				/* target LUN */
-	unsigned char type;				/* device type */
-	unsigned long lba;        /* number of blocks */
-	unsigned long blksz;			/* block size */
-	unsigned char vendor[40]; /* IDE model, SCSI Vendor */
-	unsigned char product[20];/* IDE Serial no, SCSI product */
-	unsigned char revision[8];/* firmware revision */
-	unsigned char removable;	/* removable device */
-	unsigned long (*block_read)(int dev,
-				    unsigned long start,
-				    unsigned long blkcnt,
-				    unsigned long *buffer);
+	int		if_type;	/* type of the interface */
+	int	        dev;	  	/* device number */
+	unsigned char	part_type;  	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
+#endif
+	unsigned long	lba;	  	/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	unsigned char	vendor[40]; 	/* IDE model, SCSI Vendor */
+	unsigned char	product[20];	/* IDE Serial no, SCSI product */
+	unsigned char	revision[8];	/* firmware revision */
+	unsigned long	(*block_read)(int dev,
+				      unsigned long start,
+				      unsigned long blkcnt,
+				      unsigned long *buffer);
 }block_dev_desc_t;
 
 /* Interface types: */
@@ -53,11 +56,11 @@ typedef struct block_dev_desc {
 #define IF_TYPE_MMC		6
 
 /* Part types */
-#define	PART_TYPE_UNKNOWN	0x00
+#define PART_TYPE_UNKNOWN	0x00
 #define PART_TYPE_MAC		0x01
 #define PART_TYPE_DOS		0x02
 #define PART_TYPE_ISO		0x03
-#define PART_TYPE_AMIGA         0x04
+#define PART_TYPE_AMIGA		0x04
 
 /*
  * Type string for U-Boot bootable partitions
@@ -68,11 +71,11 @@ typedef struct block_dev_desc {
 /* device types */
 #define DEV_TYPE_UNKNOWN	0xff	/* not connected */
 #define DEV_TYPE_HARDDISK	0x00	/* harddisk */
-#define DEV_TYPE_TAPE 		0x01	/* Tape */
-#define DEV_TYPE_CDROM 		0x05	/* CD-ROM */
-#define DEV_TYPE_OPDISK 	0x07	/* optical disk */
+#define DEV_TYPE_TAPE		0x01	/* Tape */
+#define DEV_TYPE_CDROM		0x05	/* CD-ROM */
+#define DEV_TYPE_OPDISK		0x07	/* optical disk */
 
-typedef	struct disk_partition {
+typedef struct disk_partition {
 	ulong	start;		/* # of first block in partition	*/
 	ulong	size;		/* number of blocks in partition	*/
 	ulong	blksz;		/* block size in bytes			*/

+ 4 - 4
lib_generic/vsprintf.c

@@ -55,7 +55,7 @@ long simple_strtol(const char *cp,char **endp,unsigned int base)
 	return simple_strtoul(cp,endp,base);
 }
 
-#if CFG_64BIT_STRTOUL
+#ifdef CFG_64BIT_STRTOUL
 unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base)
 {
 	unsigned long long result = 0, value;
@@ -112,7 +112,7 @@ static int skip_atoi(const char **s)
 	__res; \
 })
 
-#if CFG_64BIT_VSPRINTF
+#ifdef CFG_64BIT_VSPRINTF
 static char * number(char * str, long long num, int base, int size, int precision ,int type)
 #else
 static char * number(char * str, long num, int base, int size, int precision ,int type)
@@ -188,7 +188,7 @@ int sprintf(char * buf, const char *fmt, ...);
 int vsprintf(char *buf, const char *fmt, va_list args)
 {
 	int len;
-#if CFG_64BIT_VSPRINTF
+#ifdef CFG_64BIT_VSPRINTF
 	unsigned long long num;
 #else
 	unsigned long num;
@@ -337,7 +337,7 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 				--fmt;
 			continue;
 		}
-#if CFG_64BIT_VSPRINTF
+#ifdef CFG_64BIT_VSPRINTF
 		if (qualifier == 'q')  /* "quad" for 64 bit variables */
 			num = va_arg(args, unsigned long long);
 		else

+ 1 - 1
lib_i386/board.c

@@ -343,7 +343,7 @@ void start_i386boot (void)
 	/* Must happen after interrupts are initialized since
 	 * an irq handler gets installed
 	 */
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 	serial_buffered_init();
 #endif
 

+ 1 - 1
lib_m68k/board.c

@@ -577,7 +577,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	 */
 	timer_init();
 
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 	serial_buffered_init();
 #endif
 

+ 1 - 1
lib_ppc/board.c

@@ -874,7 +874,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/* Must happen after interrupts are initialized since
 	 * an irq handler gets installed
 	 */
-#if CONFIG_SERIAL_SOFTWARE_FIFO
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 	serial_buffered_init();
 #endif