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@@ -0,0 +1,148 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2019 DEIF A/S
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+ *
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+ * GPIO driver to set/clear SPISEL_BOOT pin on mpc83xx.
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <mapmem.h>
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+#include <asm/gpio.h>
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+
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+struct mpc83xx_spisel_boot {
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+ u32 __iomem *spi_cs;
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+ ulong addr;
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+ uint gpio_count;
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+ ulong type;
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+};
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+
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+static u32 gpio_mask(uint gpio)
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+{
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+ return (1U << (31 - (gpio)));
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+}
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+
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+static int mpc83xx_spisel_boot_direction_input(struct udevice *dev, uint gpio)
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+{
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+ return -EINVAL;
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+}
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+
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+static int mpc83xx_spisel_boot_set_value(struct udevice *dev, uint gpio, int value)
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+{
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+ struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
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+
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+ debug("%s: gpio=%d, value=%u, gpio_mask=0x%08x\n", __func__,
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+ gpio, value, gpio_mask(gpio));
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+
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+ if (value)
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+ setbits_be32(data->spi_cs, gpio_mask(gpio));
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+ else
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+ clrbits_be32(data->spi_cs, gpio_mask(gpio));
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+
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+ return 0;
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+}
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+
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+static int mpc83xx_spisel_boot_direction_output(struct udevice *dev, uint gpio, int value)
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+{
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+ return 0;
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+}
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+
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+static int mpc83xx_spisel_boot_get_value(struct udevice *dev, uint gpio)
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+{
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+ struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
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+
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+ return !!(in_be32(data->spi_cs) & gpio_mask(gpio));
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+}
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+
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+static int mpc83xx_spisel_boot_get_function(struct udevice *dev, uint gpio)
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+{
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+ return GPIOF_OUTPUT;
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+}
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+
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+#if CONFIG_IS_ENABLED(OF_CONTROL)
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+static int mpc83xx_spisel_boot_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
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+ fdt_addr_t addr;
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+ u32 reg[2];
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+
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+ dev_read_u32_array(dev, "reg", reg, 2);
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+ addr = dev_translate_address(dev, reg);
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+
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+ plat->addr = addr;
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+ plat->size = reg[1];
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+ plat->ngpios = dev_read_u32_default(dev, "ngpios", 1);
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+
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+ return 0;
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+}
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+#endif
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+
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+static int mpc83xx_spisel_boot_platdata_to_priv(struct udevice *dev)
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+{
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+ struct mpc83xx_spisel_boot *priv = dev_get_priv(dev);
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+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
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+ unsigned long size = plat->size;
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+ ulong driver_data = dev_get_driver_data(dev);
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+
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+ if (size == 0)
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+ size = 0x04;
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+
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+ priv->addr = plat->addr;
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+ priv->spi_cs = map_sysmem(plat->addr, size);
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+
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+ if (!priv->spi_cs)
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+ return -ENOMEM;
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+
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+ priv->gpio_count = plat->ngpios;
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+
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+ priv->type = driver_data;
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+
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+ return 0;
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+}
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+
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+static int mpc83xx_spisel_boot_probe(struct udevice *dev)
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+{
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+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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+ struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
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+ char name[32], *str;
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+
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+ mpc83xx_spisel_boot_platdata_to_priv(dev);
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+
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+ snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
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+ str = strdup(name);
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+
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+ if (!str)
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+ return -ENOMEM;
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+
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+ uc_priv->bank_name = str;
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+ uc_priv->gpio_count = data->gpio_count;
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+
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+ return 0;
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+}
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+
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+static const struct dm_gpio_ops mpc83xx_spisel_boot_ops = {
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+ .direction_input = mpc83xx_spisel_boot_direction_input,
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+ .direction_output = mpc83xx_spisel_boot_direction_output,
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+ .get_value = mpc83xx_spisel_boot_get_value,
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+ .set_value = mpc83xx_spisel_boot_set_value,
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+ .get_function = mpc83xx_spisel_boot_get_function,
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+};
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+
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+static const struct udevice_id mpc83xx_spisel_boot_ids[] = {
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+ { .compatible = "fsl,mpc8309-spisel-boot" },
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+ { .compatible = "fsl,mpc83xx-spisel-boot" },
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+ { /* sentinel */ }
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+};
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+
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+U_BOOT_DRIVER(spisel_boot_mpc83xx) = {
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+ .name = "spisel_boot_mpc83xx",
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+ .id = UCLASS_GPIO,
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+ .ops = &mpc83xx_spisel_boot_ops,
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+#if CONFIG_IS_ENABLED(OF_CONTROL)
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+ .ofdata_to_platdata = mpc83xx_spisel_boot_ofdata_to_platdata,
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+ .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
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+ .of_match = mpc83xx_spisel_boot_ids,
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+#endif
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+ .probe = mpc83xx_spisel_boot_probe,
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+ .priv_auto_alloc_size = sizeof(struct mpc83xx_spisel_boot),
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+};
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