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@@ -6,6 +6,20 @@
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*/
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&cbass_mcu {
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+ mcu_conf: scm_conf@40f00000 {
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+ compatible = "syscon", "simple-mfd";
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+ reg = <0x0 0x40f00000 0x0 0x20000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0x0 0x40f00000 0x20000>;
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+
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+ phy_gmii_sel: phy@4040 {
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+ compatible = "ti,am654-phy-gmii-sel";
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+ reg = <0x4040 0x4>;
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+ #phy-cells = <1>;
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+ };
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+ };
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+
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mcu_uart0: serial@40a00000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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@@ -146,4 +160,74 @@
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ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
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};
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};
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+
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+ mcu_cpsw: ethernet@46000000 {
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+ compatible = "ti,am654-cpsw-nuss";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ reg = <0x0 0x46000000 0x0 0x200000>;
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+ reg-names = "cpsw_nuss";
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+ ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
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+ dma-coherent;
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+ clocks = <&k3_clks 5 10>;
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+ clock-names = "fck";
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+ power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
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+
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+ dmas = <&mcu_udmap 0xf000>,
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+ <&mcu_udmap 0xf001>,
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+ <&mcu_udmap 0xf002>,
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+ <&mcu_udmap 0xf003>,
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+ <&mcu_udmap 0xf004>,
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+ <&mcu_udmap 0xf005>,
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+ <&mcu_udmap 0xf006>,
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+ <&mcu_udmap 0xf007>,
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+ <&mcu_udmap 0x7000>;
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+ dma-names = "tx0", "tx1", "tx2", "tx3",
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+ "tx4", "tx5", "tx6", "tx7",
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+ "rx";
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+
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+ ethernet-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpsw_port1: port@1 {
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+ reg = <1>;
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+ ti,mac-only;
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+ label = "port1";
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+ ti,syscon-efuse = <&mcu_conf 0x200>;
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+ phys = <&phy_gmii_sel 1>;
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+ };
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+ };
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+
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+ davinci_mdio: mdio@f00 {
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+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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+ reg = <0x0 0xf00 0x0 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&k3_clks 5 10>;
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+ clock-names = "fck";
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+ bus_freq = <1000000>;
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+ };
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+
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+ cpts@3d000 {
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+ compatible = "ti,am65-cpts";
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+ reg = <0x0 0x3d000 0x0 0x400>;
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+ clocks = <&mcu_cpsw_cpts_mux>;
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+ clock-names = "cpts";
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+ interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "cpts";
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+ ti,cpts-ext-ts-inputs = <4>;
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+ ti,cpts-periodic-outputs = <2>;
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+
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+ mcu_cpsw_cpts_mux: refclk-mux {
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+ #clock-cells = <0>;
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+ clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
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+ <&k3_clks 118 6>, <&k3_clks 118 3>,
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+ <&k3_clks 118 8>, <&k3_clks 118 14>,
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+ <&k3_clks 120 3>, <&k3_clks 121 3>;
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+ assigned-clocks = <&mcu_cpsw_cpts_mux>;
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+ assigned-clock-parents = <&k3_clks 118 5>;
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+ };
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+ };
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+ };
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};
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