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@@ -0,0 +1,348 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * NXP C45 PHY driver
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+ *
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+ * Copyright 2021 NXP
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+ * Author: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
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+ */
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+#include <common.h>
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+#include <dm.h>
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+#include <dm/devres.h>
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+#include <linux/delay.h>
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+#include <linux/math64.h>
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+#include <linux/mdio.h>
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+#include <phy.h>
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+
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+#define PHY_ID_TJA_1103 0x001BB010
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+
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+#define VEND1_DEVICE_CONTROL 0x0040
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+#define DEVICE_CONTROL_RESET BIT(15)
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+#define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14)
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+#define DEVICE_CONTROL_CONFIG_ALL_EN BIT(13)
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+
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+#define VEND1_PORT_CONTROL 0x8040
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+#define PORT_CONTROL_EN BIT(14)
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+
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+#define VEND1_PHY_CONTROL 0x8100
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+#define PHY_CONFIG_EN BIT(14)
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+#define PHY_START_OP BIT(0)
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+
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+#define VEND1_PHY_CONFIG 0x8108
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+#define PHY_CONFIG_AUTO BIT(0)
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+
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+#define VEND1_PORT_INFRA_CONTROL 0xAC00
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+#define PORT_INFRA_CONTROL_EN BIT(14)
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+
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+#define VEND1_RXID 0xAFCC
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+#define VEND1_TXID 0xAFCD
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+#define ID_ENABLE BIT(15)
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+
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+#define VEND1_ABILITIES 0xAFC4
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+#define RGMII_ID_ABILITY BIT(15)
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+#define RGMII_ABILITY BIT(14)
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+#define RMII_ABILITY BIT(10)
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+#define REVMII_ABILITY BIT(9)
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+#define MII_ABILITY BIT(8)
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+#define SGMII_ABILITY BIT(0)
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+
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+#define VEND1_MII_BASIC_CONFIG 0xAFC6
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+#define MII_BASIC_CONFIG_REV BIT(8)
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+#define MII_BASIC_CONFIG_SGMII 0x9
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+#define MII_BASIC_CONFIG_RGMII 0x7
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+#define MII_BASIC_CONFIG_RMII 0x5
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+#define MII_BASIC_CONFIG_MII 0x4
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+
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+#define RGMII_PERIOD_PS 8000U
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+#define PS_PER_DEGREE div_u64(RGMII_PERIOD_PS, 360)
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+#define MIN_ID_PS 1644U
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+#define MAX_ID_PS 2260U
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+#define DEFAULT_ID_PS 2000U
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+
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+#define RESET_DELAY_MS 25
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+#define CONF_EN_DELAY_US 450
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+
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+struct nxp_c45_phy {
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+ u32 tx_delay;
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+ u32 rx_delay;
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+};
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+
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+static int nxp_c45_soft_reset(struct phy_device *phydev)
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+{
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+ int tries = 10, ret;
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+
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+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
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+ DEVICE_CONTROL_RESET);
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+ if (ret)
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+ return ret;
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+
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+ do {
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
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+ VEND1_DEVICE_CONTROL);
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+ if (!(ret & DEVICE_CONTROL_RESET))
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+ return 0;
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+ mdelay(RESET_DELAY_MS);
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+ } while (tries--);
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+
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+ return -EIO;
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+}
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+
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+static int nxp_c45_start_op(struct phy_device *phydev)
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+{
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+ return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
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+ PHY_START_OP);
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+}
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+
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+static int nxp_c45_config_enable(struct phy_device *phydev)
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+{
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
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+ DEVICE_CONTROL_CONFIG_GLOBAL_EN |
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+ DEVICE_CONTROL_CONFIG_ALL_EN);
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+ udelay(CONF_EN_DELAY_US);
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+
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL,
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+ PORT_CONTROL_EN);
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
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+ PHY_CONFIG_EN);
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL,
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+ PORT_INFRA_CONTROL_EN);
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+
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+ return 0;
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+}
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+
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+static u64 nxp_c45_get_phase_shift(u64 phase_offset_raw)
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+{
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+ /* The delay in degree phase is 73.8 + phase_offset_raw * 0.9.
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+ * To avoid floating point operations we'll multiply by 10
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+ * and get 1 decimal point precision.
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+ */
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+ phase_offset_raw *= 10;
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+ phase_offset_raw -= 738;
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+ return div_u64(phase_offset_raw, 9);
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+}
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+
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+static void nxp_c45_disable_delays(struct phy_device *phydev)
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+{
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0);
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0);
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+}
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+
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+static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay)
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+{
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+ if (delay < MIN_ID_PS) {
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+ pr_err("%s: delay value smaller than %u\n",
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+ phydev->drv->name, MIN_ID_PS);
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+ return -EINVAL;
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+ }
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+
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+ if (delay > MAX_ID_PS) {
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+ pr_err("%s: delay value higher than %u\n",
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+ phydev->drv->name, MAX_ID_PS);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int nxp_c45_get_delays(struct phy_device *phydev)
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+{
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+ struct nxp_c45_phy *priv = phydev->priv;
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+ int ret;
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+
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+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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+ ret = dev_read_u32(phydev->dev, "tx-internal-delay-ps",
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+ &priv->tx_delay);
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+ if (ret)
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+ priv->tx_delay = DEFAULT_ID_PS;
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+
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+ ret = nxp_c45_check_delay(phydev, priv->tx_delay);
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+ if (ret) {
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+ pr_err("%s: tx-internal-delay-ps invalid value\n",
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+ phydev->drv->name);
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+ return ret;
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+ }
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+ }
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+
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+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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+ ret = dev_read_u32(phydev->dev, "rx-internal-delay-ps",
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+ &priv->rx_delay);
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+ if (ret)
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+ priv->rx_delay = DEFAULT_ID_PS;
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+
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+ ret = nxp_c45_check_delay(phydev, priv->rx_delay);
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+ if (ret) {
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+ pr_err("%s: rx-internal-delay-ps invalid value\n",
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+ phydev->drv->name);
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+ return ret;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static void nxp_c45_set_delays(struct phy_device *phydev)
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+{
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+ struct nxp_c45_phy *priv = phydev->priv;
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+ u64 tx_delay = priv->tx_delay;
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+ u64 rx_delay = priv->rx_delay;
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+ u64 degree;
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+
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+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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+ degree = div_u64(tx_delay, PS_PER_DEGREE);
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
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+ ID_ENABLE | nxp_c45_get_phase_shift(degree));
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+ } else {
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0);
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+ }
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+
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+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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+ degree = div_u64(rx_delay, PS_PER_DEGREE);
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
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+ ID_ENABLE | nxp_c45_get_phase_shift(degree));
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+ } else {
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0);
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+ }
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+}
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+
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+static int nxp_c45_set_phy_mode(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES);
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+ pr_debug("%s: Clause 45 managed PHY abilities 0x%x\n",
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+ phydev->drv->name, ret);
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+
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+ switch (phydev->interface) {
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+ case PHY_INTERFACE_MODE_RGMII:
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+ if (!(ret & RGMII_ABILITY)) {
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+ pr_err("%s: rgmii mode not supported\n",
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+ phydev->drv->name);
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+ return -EINVAL;
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+ }
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
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+ MII_BASIC_CONFIG_RGMII);
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+ nxp_c45_disable_delays(phydev);
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+ break;
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ if (!(ret & RGMII_ID_ABILITY)) {
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+ pr_err("%s: rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n",
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+ phydev->drv->name);
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+ return -EINVAL;
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+ }
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
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+ MII_BASIC_CONFIG_RGMII);
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+ ret = nxp_c45_get_delays(phydev);
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+ if (ret)
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+ return ret;
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+
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+ nxp_c45_set_delays(phydev);
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+ break;
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+ case PHY_INTERFACE_MODE_MII:
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+ if (!(ret & MII_ABILITY)) {
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+ pr_err("%s: mii mode not supported\n",
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+ phydev->drv->name);
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+ return -EINVAL;
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+ }
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
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+ MII_BASIC_CONFIG_MII);
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+ break;
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+ case PHY_INTERFACE_MODE_RMII:
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+ if (!(ret & RMII_ABILITY)) {
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+ pr_err("%s: rmii mode not supported\n",
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+ phydev->drv->name);
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+ return -EINVAL;
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+ }
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
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+ MII_BASIC_CONFIG_RMII);
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+ break;
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+ case PHY_INTERFACE_MODE_SGMII:
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+ if (!(ret & SGMII_ABILITY)) {
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+ pr_err("%s: sgmii mode not supported\n",
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+ phydev->drv->name);
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+ return -EINVAL;
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+ }
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
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+ MII_BASIC_CONFIG_SGMII);
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+ break;
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+ case PHY_INTERFACE_MODE_INTERNAL:
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int nxp_c45_config(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = nxp_c45_soft_reset(phydev);
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+ if (ret)
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+ return ret;
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+
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+ ret = nxp_c45_config_enable(phydev);
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+ if (ret) {
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+ pr_err("%s: Failed to enable config\n", phydev->drv->name);
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+ return ret;
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+ }
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+
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
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+ PHY_CONFIG_AUTO);
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+
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+ ret = nxp_c45_set_phy_mode(phydev);
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+ if (ret) {
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+ pr_err("%s: Failed to set phy mode\n", phydev->drv->name);
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+ return ret;
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+ }
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+
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+ phydev->autoneg = AUTONEG_DISABLE;
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+
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+ return nxp_c45_start_op(phydev);
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+}
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+
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+static int nxp_c45_startup(struct phy_device *phydev)
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+{
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+ u32 reg;
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+
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+ reg = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
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+ phydev->link = !!(reg & MDIO_STAT1_LSTATUS);
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+ phydev->speed = SPEED_100;
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+ phydev->duplex = DUPLEX_FULL;
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+ return 0;
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+}
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+
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+static int nxp_c45_probe(struct phy_device *phydev)
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+{
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+ struct nxp_c45_phy *priv;
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+
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+ priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ phydev->priv = priv;
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+
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+ return 0;
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+}
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+
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+static struct phy_driver nxp_tja11xx = {
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+ .name = "NXP C45 TJA1103",
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+ .uid = PHY_ID_TJA_1103,
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+ .mask = 0xfffff0,
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+ .features = PHY_100BT1_FEATURES,
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+ .probe = &nxp_c45_probe,
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+ .config = &nxp_c45_config,
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+ .startup = &nxp_c45_startup,
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+ .shutdown = &genphy_shutdown,
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+};
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+
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+int phy_nxp_tja11xx_init(void)
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+{
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+ phy_register(&nxp_tja11xx);
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+ return 0;
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+}
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