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@@ -241,6 +241,72 @@ static inline void sync(void)
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#define __iormb() dmb()
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#define __iowmb() dmb()
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+/*
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+ * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
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+ * access or a MMIO access, these functions don't care. The info is
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+ * encoded in the hardware mapping set up by the mapping functions
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+ * (or the cookie itself, depending on implementation and hw).
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+ *
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+ * The generic routines don't assume any hardware mappings, and just
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+ * encode the PIO/MMIO as part of the cookie. They coldly assume that
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+ * the MMIO IO mappings are not in the low address range.
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+ *
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+ * Architectures for which this is not true can't use this generic
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+ * implementation and should do their own copy.
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+ */
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+
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+/*
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+ * We assume that all the low physical PIO addresses (0-0xffff) always
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+ * PIO. That means we can do some sanity checks on the low bits, and
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+ * don't need to just take things for granted.
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+ */
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+#define PIO_RESERVED 0x10000UL
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+
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+/*
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+ * Ugly macros are a way of life.
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+ */
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+#define IO_COND(addr, is_pio, is_mmio) do { \
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+ unsigned long port = (unsigned long __force)addr; \
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+ if (port >= PIO_RESERVED) { \
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+ is_mmio; \
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+ } else { \
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+ is_pio; \
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+ } \
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+} while (0)
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+
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+static inline u8 ioread8(const volatile void __iomem *addr)
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+{
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+ IO_COND(addr, return inb(port), return readb(addr));
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+ return 0xff;
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+}
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+
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+static inline u16 ioread16(const volatile void __iomem *addr)
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+{
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+ IO_COND(addr, return inw(port), return readw(addr));
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+ return 0xffff;
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+}
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+
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+static inline u32 ioread32(const volatile void __iomem *addr)
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+{
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+ IO_COND(addr, return inl(port), return readl(addr));
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+ return 0xffffffff;
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+}
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+
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+static inline void iowrite8(u8 value, volatile void __iomem *addr)
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+{
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+ IO_COND(addr, outb(value, port), writeb(value, addr));
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+}
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+
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+static inline void iowrite16(u16 value, volatile void __iomem *addr)
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+{
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+ IO_COND(addr, outw(value, port), writew(value, addr));
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+}
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+
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+static inline void iowrite32(u32 value, volatile void __iomem *addr)
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+{
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+ IO_COND(addr, outl(value, port), writel(value, addr));
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+}
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+
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#include <asm-generic/io.h>
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#endif /* _ASM_IO_H */
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