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@@ -0,0 +1,246 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * PCI emulation device for an x86 Power-Management Controller (PMC)
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+ *
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+ * Copyright 2019 Google LLC
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+ * Written by Simon Glass <sjg@chromium.org>
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <pci.h>
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+#include <asm/test.h>
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+#include <power/acpi_pmc.h>
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+
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+/**
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+ * struct pmc_emul_platdata - platform data for this device
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+ *
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+ * @command: Current PCI command value
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+ * @bar: Current base address values
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+ */
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+struct pmc_emul_platdata {
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+ u16 command;
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+ u32 bar[6];
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+};
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+
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+enum {
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+ MEMMAP_SIZE = 0x80,
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+};
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+
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+static struct pci_bar {
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+ int type;
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+ u32 size;
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+} barinfo[] = {
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+ { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE },
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+ { 0, 0 },
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+ { 0, 0 },
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+ { 0, 0 },
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+ { PCI_BASE_ADDRESS_SPACE_IO, 256 },
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+};
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+
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+struct pmc_emul_priv {
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+ u8 regs[MEMMAP_SIZE];
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+};
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+
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+static int sandbox_pmc_emul_read_config(struct udevice *emul, uint offset,
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+ ulong *valuep, enum pci_size_t size)
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+{
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+ struct pmc_emul_platdata *plat = dev_get_platdata(emul);
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+
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+ switch (offset) {
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+ case PCI_COMMAND:
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+ *valuep = plat->command;
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+ break;
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+ case PCI_HEADER_TYPE:
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+ *valuep = 0;
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+ break;
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+ case PCI_VENDOR_ID:
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+ *valuep = SANDBOX_PCI_VENDOR_ID;
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+ break;
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+ case PCI_DEVICE_ID:
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+ *valuep = SANDBOX_PCI_PMC_EMUL_ID;
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+ break;
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+ case PCI_CLASS_DEVICE:
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+ if (size == PCI_SIZE_8) {
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+ *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
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+ } else {
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+ *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
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+ SANDBOX_PCI_CLASS_SUB_CODE;
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+ }
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+ break;
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+ case PCI_CLASS_CODE:
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+ *valuep = SANDBOX_PCI_CLASS_CODE;
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+ break;
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+ case PCI_BASE_ADDRESS_0:
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+ case PCI_BASE_ADDRESS_1:
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+ case PCI_BASE_ADDRESS_2:
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+ case PCI_BASE_ADDRESS_3:
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+ case PCI_BASE_ADDRESS_4:
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+ case PCI_BASE_ADDRESS_5: {
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+ int barnum;
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+ u32 *bar;
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+
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+ barnum = pci_offset_to_barnum(offset);
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+ bar = &plat->bar[barnum];
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+
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+ *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
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+ barinfo[barnum].size);
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+ break;
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+ }
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+ case PCI_CAPABILITY_LIST:
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+ *valuep = PCI_CAP_ID_PM_OFFSET;
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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+static int sandbox_pmc_emul_write_config(struct udevice *emul, uint offset,
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+ ulong value, enum pci_size_t size)
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+{
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+ struct pmc_emul_platdata *plat = dev_get_platdata(emul);
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+
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+ switch (offset) {
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+ case PCI_COMMAND:
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+ plat->command = value;
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+ break;
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+ case PCI_BASE_ADDRESS_0:
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+ case PCI_BASE_ADDRESS_1: {
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+ int barnum;
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+ u32 *bar;
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+
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+ barnum = pci_offset_to_barnum(offset);
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+ bar = &plat->bar[barnum];
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+
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+ debug("w bar %d=%lx\n", barnum, value);
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+ *bar = value;
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+ /* space indicator (bit#0) is read-only */
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+ *bar |= barinfo[barnum].type;
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+ break;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static int sandbox_pmc_emul_find_bar(struct udevice *emul, unsigned int addr,
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+ int *barnump, unsigned int *offsetp)
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+{
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+ struct pmc_emul_platdata *plat = dev_get_platdata(emul);
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+ int barnum;
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+
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+ for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
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+ unsigned int size = barinfo[barnum].size;
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+ u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
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+
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+ if (addr >= base && addr < base + size) {
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+ *barnump = barnum;
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+ *offsetp = addr - base;
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+ return 0;
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+ }
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+ }
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+ *barnump = -1;
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+
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+ return -ENOENT;
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+}
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+
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+static int sandbox_pmc_emul_read_io(struct udevice *dev, unsigned int addr,
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+ ulong *valuep, enum pci_size_t size)
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+{
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+ unsigned int offset;
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+ int barnum;
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+ int ret;
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+
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+ ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset);
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+ if (ret)
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+ return ret;
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+
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+ if (barnum == 4)
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+ *valuep = offset;
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+ else if (barnum == 0)
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+ *valuep = offset;
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+
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+ return 0;
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+}
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+
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+static int sandbox_pmc_emul_write_io(struct udevice *dev, unsigned int addr,
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+ ulong value, enum pci_size_t size)
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+{
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+ unsigned int offset;
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+ int barnum;
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+ int ret;
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+
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+ ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int sandbox_pmc_emul_map_physmem(struct udevice *dev,
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+ phys_addr_t addr, unsigned long *lenp,
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+ void **ptrp)
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+{
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+ struct pmc_emul_priv *priv = dev_get_priv(dev);
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+ unsigned int offset, avail;
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+ int barnum;
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+ int ret;
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+
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+ ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset);
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+ if (ret)
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+ return ret;
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+
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+ if (barnum == 0) {
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+ *ptrp = priv->regs + offset;
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+ avail = barinfo[0].size - offset;
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+ if (avail > barinfo[0].size)
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+ *lenp = 0;
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+ else
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+ *lenp = min(*lenp, (ulong)avail);
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+
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+ return 0;
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+ }
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+
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+ return -ENOENT;
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+}
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+
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+static int sandbox_pmc_probe(struct udevice *dev)
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+{
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+ struct pmc_emul_priv *priv = dev_get_priv(dev);
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+ int i;
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+
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+ for (i = 0; i < MEMMAP_SIZE; i++)
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+ priv->regs[i] = i;
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+
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+ return 0;
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+}
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+
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+static struct dm_pci_emul_ops sandbox_pmc_emul_emul_ops = {
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+ .read_config = sandbox_pmc_emul_read_config,
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+ .write_config = sandbox_pmc_emul_write_config,
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+ .read_io = sandbox_pmc_emul_read_io,
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+ .write_io = sandbox_pmc_emul_write_io,
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+ .map_physmem = sandbox_pmc_emul_map_physmem,
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+};
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+
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+static const struct udevice_id sandbox_pmc_emul_ids[] = {
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+ { .compatible = "sandbox,pmc-emul" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(sandbox_pmc_emul_emul) = {
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+ .name = "sandbox_pmc_emul_emul",
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+ .id = UCLASS_PCI_EMUL,
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+ .of_match = sandbox_pmc_emul_ids,
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+ .ops = &sandbox_pmc_emul_emul_ops,
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+ .probe = sandbox_pmc_probe,
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+ .priv_auto_alloc_size = sizeof(struct pmc_emul_priv),
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+ .platdata_auto_alloc_size = sizeof(struct pmc_emul_platdata),
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+};
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+
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+static struct pci_device_id sandbox_pmc_emul_supported[] = {
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+ { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) },
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+ {},
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+};
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+
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+U_BOOT_PCI_DEVICE(sandbox_pmc_emul_emul, sandbox_pmc_emul_supported);
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