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@@ -208,6 +208,35 @@ config ARCH_LS2080A
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imply DISTRO_DEFAULTS
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imply PANIC_HANG
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+config ARCH_LX2162A
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+ bool
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+ select ARMV8_SET_SMPEN
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+ select FSL_LSCH3
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+ select NXP_LSCH3_2
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+ select SYS_HAS_SERDES
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+ select SYS_FSL_SRDS_1
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+ select SYS_FSL_SRDS_2
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+ select SYS_FSL_DDR
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+ select SYS_FSL_DDR_LE
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+ select SYS_FSL_DDR_VER_50
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+ select SYS_FSL_EC1
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+ select SYS_FSL_EC2
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+ select SYS_FSL_ERRATUM_A050106
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+ select SYS_FSL_HAS_RGMII
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+ select SYS_FSL_HAS_SEC
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+ select SYS_FSL_HAS_CCN508
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+ select SYS_FSL_HAS_DDR4
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+ select SYS_FSL_SEC_COMPAT_5
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+ select SYS_FSL_SEC_LE
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+ select ARCH_EARLY_INIT_R
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+ select BOARD_EARLY_INIT_F
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+ select SYS_I2C_MXC
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+ select RESV_RAM if GIC_V3_ITS
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+ imply DISTRO_DEFAULTS
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+ imply PANIC_HANG
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+ imply SCSI
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+ imply SCSI_AHCI
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+
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config ARCH_LX2160A
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bool
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select ARMV8_SET_SMPEN
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@@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106
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help
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USB3.0 Receiver needs to enable fixed equalization
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for each of PHY instances in an SOC. This is similar
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- to erratum A-009007, but this one is for LX2160A,
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+ to erratum A-009007, but this one is for LX2160A and LX2162A,
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and the register value is different.
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config SYS_FSL_ERRATUM_A010315
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@@ -362,6 +391,7 @@ config MAX_CPUS
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default 16 if ARCH_LS2080A
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default 8 if ARCH_LS1088A
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default 16 if ARCH_LX2160A
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+ default 16 if ARCH_LX2162A
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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@@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
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int "DUART clock divider"
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default 1 if ARCH_LS1043A
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default 4 if ARCH_LX2160A
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+ default 4 if ARCH_LX2162A
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default 2
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help
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This is the divider that is used to derive DUART clock from Platform
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@@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV
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default 4 if ARCH_LS1012A
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default 4 if ARCH_LS1028A
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default 8 if ARCH_LX2160A
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+ default 8 if ARCH_LX2162A
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default 8 if ARCH_LS1088A
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default 2
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help
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@@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV
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default 4 if ARCH_LS1012A
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default 4 if ARCH_LS1028A
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default 8 if ARCH_LX2160A
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+ default 8 if ARCH_LX2162A
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default 8 if ARCH_LS1088A
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default 2
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help
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@@ -560,14 +593,14 @@ config SYS_FSL_EC1
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bool
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help
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Ethernet controller 1, this is connected to
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- MAC17 for LX2160A or to MAC3 for other SoCs
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+ MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
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Provides DPAA2 capabilities
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config SYS_FSL_EC2
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bool
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help
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Ethernet controller 2, this is connected to
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- MAC18 for LX2160A or to MAC4 for other SoCs
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+ MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
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Provides DPAA2 capabilities
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config SYS_FSL_ERRATUM_A008336
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