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@@ -1,5 +1,6 @@
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/*
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* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
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+ *
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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@@ -37,6 +38,90 @@ DECLARE_GLOBAL_DATA_PTR;
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void get_sys_info (sys_info_t * sysInfo)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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+#ifdef CONFIG_FSL_CORENET
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+ volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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+
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+ const u8 core_cplx_PLL[16] = {
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+ [ 0] = 0, /* CC1 PPL / 1 */
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+ [ 1] = 0, /* CC1 PPL / 2 */
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+ [ 2] = 0, /* CC1 PPL / 4 */
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+ [ 4] = 1, /* CC2 PPL / 1 */
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+ [ 5] = 1, /* CC2 PPL / 2 */
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+ [ 6] = 1, /* CC2 PPL / 4 */
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+ [ 8] = 2, /* CC3 PPL / 1 */
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+ [ 9] = 2, /* CC3 PPL / 2 */
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+ [10] = 2, /* CC3 PPL / 4 */
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+ [12] = 3, /* CC4 PPL / 1 */
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+ [13] = 3, /* CC4 PPL / 2 */
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+ [14] = 3, /* CC4 PPL / 4 */
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+ };
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+
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+ const u8 core_cplx_PLL_div[16] = {
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+ [ 0] = 1, /* CC1 PPL / 1 */
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+ [ 1] = 2, /* CC1 PPL / 2 */
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+ [ 2] = 4, /* CC1 PPL / 4 */
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+ [ 4] = 1, /* CC2 PPL / 1 */
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+ [ 5] = 2, /* CC2 PPL / 2 */
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+ [ 6] = 4, /* CC2 PPL / 4 */
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+ [ 8] = 1, /* CC3 PPL / 1 */
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+ [ 9] = 2, /* CC3 PPL / 2 */
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+ [10] = 4, /* CC3 PPL / 4 */
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+ [12] = 1, /* CC4 PPL / 1 */
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+ [13] = 2, /* CC4 PPL / 2 */
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+ [14] = 4, /* CC4 PPL / 4 */
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+ };
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+ uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
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+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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+
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+ sysInfo->freqSystemBus = sysclk;
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+ sysInfo->freqDDRBus = sysclk;
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+ freqCC_PLL[0] = sysclk;
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+ freqCC_PLL[1] = sysclk;
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+ freqCC_PLL[2] = sysclk;
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+ freqCC_PLL[3] = sysclk;
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+
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+ sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
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+ sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
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+ freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
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+ freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
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+ freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
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+ freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
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+
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+ rcw_tmp = in_be32(&gur->rcwsr[3]);
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+ for (i = 0; i < cpu_numcores(); i++) {
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+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
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+ u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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+
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+ sysInfo->freqProcessor[i] =
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+ freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
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+ }
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+
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+#define PME_CLK_SEL 0x80000000
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+#define FM1_CLK_SEL 0x40000000
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+#define FM2_CLK_SEL 0x20000000
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+ rcw_tmp = in_be32(&gur->rcwsr[7]);
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+
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+#ifdef CONFIG_SYS_DPAA_PME
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+ if (rcw_tmp & PME_CLK_SEL)
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+ sysInfo->freqPME = freqCC_PLL[2] / 2;
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+ else
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+ sysInfo->freqPME = sysInfo->freqSystemBus / 2;
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+#endif
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+
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+#ifdef CONFIG_SYS_DPAA_FMAN
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+ if (rcw_tmp & FM1_CLK_SEL)
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+ sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
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+ else
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+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
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+#if (CONFIG_SYS_NUM_FMAN) == 2
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+ if (rcw_tmp & FM2_CLK_SEL)
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+ sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
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+ else
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+ sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
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+#endif
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+#endif
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+
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+#else
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uint plat_ratio,e500_ratio,half_freqSystemBus;
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uint lcrr_div;
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int i;
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@@ -67,6 +152,7 @@ void get_sys_info (sys_info_t * sysInfo)
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sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
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}
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#endif
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+#endif
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#ifdef CONFIG_QE
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qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
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