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@@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008-2016 Freescale Semiconductor, Inc.
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- * Copyright 2017-2018 NXP Semiconductor
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+ * Copyright 2017-2021 NXP Semiconductor
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*/
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#include <common.h>
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@@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num,
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unsigned int caslat_actual;
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unsigned int retry = 16;
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unsigned int tmp = ~0;
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- const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
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+ unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
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#ifdef CONFIG_SYS_FSL_DDR3
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const unsigned int taamax = 20000;
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#else
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@@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num,
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}
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common_caslat = tmp;
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+ if (!mclk_ps) {
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+ printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n",
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+ outpdimm->tckmin_x_ps);
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+ mclk_ps = outpdimm->tckmin_x_ps;
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+ }
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+
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/* validate if the memory clk is in the range of dimms */
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if (mclk_ps < outpdimm->tckmin_x_ps) {
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printf("DDR clock (MCLK cycle %u ps) is faster than "
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