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@@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
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#endif
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#endif
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+ /* The freq_systembus is used to record frequency of platform PLL */
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sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
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- /* Platform clock is half of platform PLL */
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- sys_info->freq_systembus /= 2;
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sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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@@ -142,13 +141,13 @@ int get_clocks(void)
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struct sys_info sys_info;
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get_sys_info(&sys_info);
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gd->cpu_clk = sys_info.freq_processor[0];
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- gd->bus_clk = sys_info.freq_systembus;
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+ gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
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gd->mem_clk = sys_info.freq_ddrbus;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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gd->arch.mem2_clk = sys_info.freq_ddrbus2;
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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- gd->arch.sdhc_clk = gd->bus_clk / 2;
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+ gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
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#endif /* defined(CONFIG_FSL_ESDHC) */
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if (gd->cpu_clk != 0)
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@@ -159,7 +158,7 @@ int get_clocks(void)
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/********************************************
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* get_bus_freq
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- * return system bus freq in Hz
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+ * return platform clock in Hz
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*********************************************/
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ulong get_bus_freq(ulong dummy)
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{
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@@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
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return gd->mem_clk;
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}
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+int get_i2c_freq(ulong dummy)
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+{
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+ return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
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+}
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+
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+int get_dspi_freq(ulong dummy)
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+{
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+ return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
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+}
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+
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+int get_serial_clock(void)
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+{
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+ return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
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+}
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+
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_I2C_CLK:
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- return get_bus_freq(0) / 2;
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+ return get_i2c_freq(0);
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case MXC_DSPI_CLK:
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- return get_bus_freq(0) / 2;
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+ return get_dspi_freq(0);
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default:
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printf("Unsupported clock\n");
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}
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