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@@ -12,21 +12,14 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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- compatible = "starfive,dubhe0", "riscv";
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- d-cache-block-size = <64>;
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- d-cache-sets = <128>;
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- d-cache-size = <65536>;
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+ cpu0: cpu@0 {
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+ compatible = "starfive,dubhe", "riscv";
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device_type = "cpu";
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- i-cache-block-size = <64>;
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- i-cache-sets = <512>;
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- i-cache-size = <65536>;
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- i-tlb-sets = <1>;
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- i-tlb-size = <32>;
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mmu-type = "riscv,sv48";
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reg = <0x0>;
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- riscv,isa = "rv64imafdcbhnv";
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+ riscv,isa = "rv64imafdcbh_sscofpmf";
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tlb-split;
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+
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -34,21 +27,14 @@
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};
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};
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- cpu@1 {
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+ cpu1: cpu@1 {
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compatible = "starfive,dubhe", "riscv";
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- d-cache-block-size = <64>;
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- d-cache-sets = <128>;
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- d-cache-size = <65536>;
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device_type = "cpu";
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- i-cache-block-size = <64>;
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- i-cache-sets = <512>;
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- i-cache-size = <65536>;
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- i-tlb-sets = <1>;
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- i-tlb-size = <32>;
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mmu-type = "riscv,sv48";
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reg = <0x1>;
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- riscv,isa = "rv64imafdcbhnv";
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+ riscv,isa = "rv64imafdcbh_sscofpmf";
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tlb-split;
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+
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -61,6 +47,7 @@
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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+ dma-noncoherent;
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ranges;
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clint: clint@2000000 {
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@@ -68,7 +55,9 @@
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compatible = "riscv,clint0";
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts-extended = <&cpu0_intc 3>,
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- <&cpu0_intc 7>;
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+ <&cpu0_intc 7>,
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+ <&cpu1_intc 3>,
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+ <&cpu1_intc 7>;
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};
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pbus_clk: subsystem_pbus_clock {
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@@ -86,7 +75,9 @@
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riscv,ndev = <25>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11>,
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- <&cpu0_intc 9>;
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+ <&cpu0_intc 9>,
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+ <&cpu1_intc 11>,
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+ <&cpu1_intc 9>;
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};
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spi0: spi@10000000 {
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@@ -154,6 +145,47 @@
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snps,txpbl = <4>;
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snps,rxpbl = <4>;
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status = "disabled";
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- };
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+ };
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+
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+ pmu {
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+ compatible = "riscv,pmu";
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+ interrupts-extended = <&cpu0_intc 13>,
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+ <&cpu1_intc 13>;
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+ riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
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+ <0x00006 0x0000 0xB>,
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+ <0x00008 0x0000 0x10>,
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+ <0x00009 0x0000 0xF>,
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+ <0x10000 0x0000 0x19>,
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+ <0x10001 0x0000 0x1A>,
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+ <0x10002 0x0000 0x1B>,
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+ <0x10003 0x0000 0x1C>,
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+ <0x10008 0x0000 0x8>,
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+ <0x10009 0x0000 0x9>,
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+ <0x1000C 0x0000 0x9E>,
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+ <0x1000D 0x0000 0x9F>,
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+ <0x10010 0x0000 0x1D>,
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+ <0x10011 0x0000 0x1E>,
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+ <0x10012 0x0000 0x1F>,
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+ <0x10013 0x0000 0x20>,
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+ <0x10014 0x0000 0x21>,
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+ <0x10018 0x0000 0x17>,
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+ <0x10019 0x0000 0x18>,
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+ <0x10020 0x0000 0x8>,
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+ <0x10021 0x0000 0x7>;
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+
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+ riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
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+ <0x00008 0x00009 0x00007FF8>,
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+ <0x10000 0x10003 0x00007FF8>,
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+ <0x10008 0x10009 0x00007FF8>,
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+ <0x1000C 0x1000D 0x00007FF8>,
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+ <0x10010 0x10014 0x00007FF8>,
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+ <0x10018 0x10019 0x00007FF8>,
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+ <0x10020 0x10021 0x00007FF8>;
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+
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+ riscv,raw-event-to-mhpmcounters =
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+ <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 1-31 */
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+ <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 32-33 */
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+ <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
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+ };
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};
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};
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