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@@ -25,7 +25,14 @@
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#include <common.h>
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#include <asm/io.h>
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+#include <div64.h>
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#include <asm/arch/imx-regs.h>
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+#include <asm/arch/clock.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define timestamp (gd->tbl)
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+#define lastinc (gd->lastinc)
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1<<15) /* Software reset */
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@@ -33,7 +40,24 @@
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#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
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#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
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#define GPTCR_TEN (1) /* Timer enable */
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-#define GPTPR_VAL (66)
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+
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+#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK)
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+
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+static inline unsigned long long tick_to_time(unsigned long long tick)
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+{
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+ tick *= CONFIG_SYS_HZ;
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+ do_div(tick, TIMER_FREQ_HZ);
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+
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+ return tick;
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+}
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+
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+static inline unsigned long long us_to_tick(unsigned long long usec)
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+{
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+ usec *= TIMER_FREQ_HZ;
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+ do_div(usec, 1000000);
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+
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+ return usec;
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+}
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int timer_init(void)
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{
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@@ -45,7 +69,7 @@ int timer_init(void)
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for (i = 0; i < 100; i++)
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writel(0, &gpt->ctrl); /* We have no udelay by now */
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- writel(GPTPR_VAL, &gpt->pre);
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+ writel(0, &gpt->pre);
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/* Freerun Mode, PERCLK1 input */
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writel(readl(&gpt->ctrl) |
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GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
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@@ -54,58 +78,59 @@ int timer_init(void)
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return 0;
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}
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-void reset_timer_masked(void)
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+unsigned long long get_ticks(void)
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{
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struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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-
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- writel(0, &gpt->ctrl);
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- /* Freerun Mode, PERCLK1 input */
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- writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
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- &gpt->ctrl);
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+ ulong now = readl(&gpt->counter); /* current tick value */
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+
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+ if (now >= lastinc) {
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+ /*
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+ * normal mode (non roll)
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+ * move stamp forward with absolut diff ticks
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+ */
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+ timestamp += (now - lastinc);
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+ } else {
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+ /* we have rollover of incrementer */
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+ timestamp += (0xFFFFFFFF - lastinc) + now;
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+ }
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+ lastinc = now;
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+ return timestamp;
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}
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-inline ulong get_timer_masked(void)
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+ulong get_timer_masked(void)
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{
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-
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- struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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- ulong val = readl(&gpt->counter);
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-
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- return val;
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+ /*
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+ * get_ticks() returns a long long (64 bit), it wraps in
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+ * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
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+ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
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+ * 5 * 10^6 days - long enough.
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+ */
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+ return tick_to_time(get_ticks());
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}
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ulong get_timer(ulong base)
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{
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- ulong tmp;
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+ return get_timer_masked() - base;
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+}
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- tmp = get_timer_masked();
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+/* delay x useconds AND preserve advance timstamp value */
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+void __udelay(unsigned long usec)
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+{
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+ unsigned long long tmp;
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+ ulong tmo;
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- if (tmp <= (base * 1000)) {
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- /* Overflow */
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- tmp += (0xffffffff - base);
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- }
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+ tmo = us_to_tick(usec);
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+ tmp = get_ticks() + tmo; /* get current timestamp */
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- return (tmp / 1000) - base;
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+ while (get_ticks() < tmp) /* loop till event */
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+ /*NOP*/;
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}
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/*
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- * delay x useconds AND preserve advance timstamp value
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- * GPTCNT is now supposed to tick 1 by 1 us.
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+ * This function is derived from PowerPC code (timebase clock frequency).
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+ * On ARM it returns the number of timer ticks per second.
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*/
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-void __udelay(unsigned long usec)
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+ulong get_tbclk(void)
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{
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- ulong tmp;
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-
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- tmp = get_timer_masked(); /* get current timestamp */
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-
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- /* if setting this forward will roll time stamp */
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- if ((usec + tmp + 1) < tmp) {
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- /* reset "advancing" timestamp to 0, set lastinc value */
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- reset_timer_masked();
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- } else {
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- /* else, set advancing stamp wake up time */
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- tmp += usec;
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- }
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-
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- while (get_timer_masked() < tmp) /* loop till event */
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- /*NOP*/;
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+ return TIMER_FREQ_HZ;
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}
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