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@@ -32,39 +32,4 @@
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#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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-/* Peripherals registers */
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-#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
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-
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-#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
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-#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
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-
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-#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
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-#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
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-#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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-#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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-#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
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-#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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-#define G12A_ETH_REG_0_CLK_EN BIT(12)
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-
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-#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
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-#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
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-#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
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-#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
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-#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
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-#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
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-#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
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-#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
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-#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
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-#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
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-#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
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-#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
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-
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-/* HIU registers */
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-#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
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-
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-#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
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-
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-/* Ethernet memory power domain */
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-#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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-
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#endif /* __G12A_H__ */
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