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@@ -1,34 +1,262 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
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+ * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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+#include <dm/devres.h>
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#include <dm/pinctrl.h>
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#include <linux/libfdt.h>
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+#include <linux/list.h>
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#include <asm/io.h>
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+#include <sort.h>
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+/**
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+ * struct single_pdata - platform data
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+ * @base: first configuration register
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+ * @offset: index of last configuration register
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+ * @mask: configuration-value mask bits
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+ * @width: configuration register bit width
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+ * @bits_per_mux: true if one register controls more than one pin
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+ */
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struct single_pdata {
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- fdt_addr_t base; /* first configuration register */
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- int offset; /* index of last configuration register */
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- u32 mask; /* configuration-value mask bits */
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- int width; /* configuration register bit width */
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+ fdt_addr_t base;
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+ int offset;
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+ u32 mask;
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+ u32 width;
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bool bits_per_mux;
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};
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+/**
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+ * struct single_func - pinctrl function
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+ * @node: list node
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+ * @name: pinctrl function name
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+ * @npins: number of entries in pins array
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+ * @pins: pins array
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+ */
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+struct single_func {
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+ struct list_head node;
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+ const char *name;
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+ unsigned int npins;
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+ unsigned int *pins;
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+};
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+
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+/**
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+ * struct single_priv - private data
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+ * @bits_per_pin: number of bits per pin
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+ * @npins: number of selectable pins
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+ * @pin_name: temporary buffer to store the pin name
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+ */
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+struct single_priv {
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+#if (IS_ENABLED(CONFIG_SANDBOX))
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+ u32 *sandbox_regs;
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+#endif
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+ unsigned int bits_per_pin;
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+ unsigned int npins;
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+ char pin_name[PINNAME_SIZE];
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+ struct list_head functions;
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+};
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+
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+/**
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+ * struct single_fdt_pin_cfg - pin configuration
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+ *
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+ * This structure is used for the pin configuration parameters in case
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+ * the register controls only one pin.
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+ *
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+ * @reg: configuration register offset
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+ * @val: configuration register value
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+ */
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struct single_fdt_pin_cfg {
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- fdt32_t reg; /* configuration register offset */
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- fdt32_t val; /* configuration register value */
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+ fdt32_t reg;
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+ fdt32_t val;
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};
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+/**
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+ * struct single_fdt_bits_cfg - pin configuration
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+ *
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+ * This structure is used for the pin configuration parameters in case
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+ * the register controls more than one pin.
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+ *
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+ * @reg: configuration register offset
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+ * @val: configuration register value
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+ * @mask: configuration register mask
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+ */
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struct single_fdt_bits_cfg {
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- fdt32_t reg; /* configuration register offset */
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- fdt32_t val; /* configuration register value */
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- fdt32_t mask; /* configuration register mask */
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+ fdt32_t reg;
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+ fdt32_t val;
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+ fdt32_t mask;
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};
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+#if (!IS_ENABLED(CONFIG_SANDBOX))
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+
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+static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
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+{
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+ struct single_pdata *pdata = dev_get_plat(dev);
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+
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+ switch (pdata->width) {
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+ case 8:
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+ return readb(reg);
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+ case 16:
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+ return readw(reg);
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+ default: /* 32 bits */
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+ return readl(reg);
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+ }
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+
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+ return readb(reg);
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+}
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+
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+static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
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+{
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+ struct single_pdata *pdata = dev_get_plat(dev);
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+
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+ switch (pdata->width) {
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+ case 8:
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+ writeb(val, reg);
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+ break;
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+ case 16:
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+ writew(val, reg);
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+ break;
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+ default: /* 32 bits */
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+ writel(val, reg);
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+ }
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+}
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+
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+#else /* CONFIG_SANDBOX */
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+
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+static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
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+{
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+ struct single_priv *priv = dev_get_priv(dev);
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+
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+ return priv->sandbox_regs[reg];
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+}
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+
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+static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
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+{
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+ struct single_priv *priv = dev_get_priv(dev);
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+
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+ priv->sandbox_regs[reg] = val;
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+}
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+
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+#endif /* CONFIG_SANDBOX */
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+
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+/**
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+ * single_get_pin_by_offset() - get a pin based on the register offset
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+ * @dev: single driver instance
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+ * @offset: register offset from the base
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+ */
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+static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset)
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+{
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+ struct single_pdata *pdata = dev_get_plat(dev);
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+ struct single_priv *priv = dev_get_priv(dev);
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+
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+ if (offset > pdata->offset) {
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+ dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n",
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+ offset, pdata->offset);
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+ return -EINVAL;
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+ }
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+
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+ if (pdata->bits_per_mux)
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+ return (offset * BITS_PER_BYTE) / priv->bits_per_pin;
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+
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+ return offset / (pdata->width / BITS_PER_BYTE);
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+}
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+
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+static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin)
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+{
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+ struct single_pdata *pdata = dev_get_plat(dev);
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+ struct single_priv *priv = dev_get_priv(dev);
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+ unsigned int mux_bytes;
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+
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+ if (pin >= priv->npins)
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+ return -EINVAL;
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+
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+ mux_bytes = pdata->width / BITS_PER_BYTE;
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+ if (pdata->bits_per_mux) {
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+ int byte_num;
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+
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+ byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE;
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+ return (byte_num / mux_bytes) * mux_bytes;
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+ }
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+
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+ return pin * mux_bytes;
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+}
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+
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+static const char *single_get_pin_function(struct udevice *dev,
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+ unsigned int pin)
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+{
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+ struct single_priv *priv = dev_get_priv(dev);
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+ struct single_func *func;
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+ int i;
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+
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+ list_for_each_entry(func, &priv->functions, node) {
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+ for (i = 0; i < func->npins; i++) {
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+ if (pin == func->pins[i])
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+ return func->name;
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+
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+ if (pin < func->pins[i])
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+ break;
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+ }
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+ }
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+
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+ return NULL;
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+}
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+
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+static int single_get_pin_muxing(struct udevice *dev, unsigned int pin,
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+ char *buf, int size)
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+{
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+ struct single_pdata *pdata = dev_get_plat(dev);
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+ struct single_priv *priv = dev_get_priv(dev);
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+ fdt_addr_t reg;
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+ const char *fname;
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+ unsigned int val;
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+ int offset, pin_shift = 0;
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+
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+ offset = single_get_offset_by_pin(dev, pin);
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+ if (offset < 0)
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+ return offset;
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+
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+ reg = pdata->base + offset;
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+ val = single_read(dev, reg);
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+
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+ if (pdata->bits_per_mux)
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+ pin_shift = pin % (pdata->width / priv->bits_per_pin) *
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+ priv->bits_per_pin;
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+
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+ val &= (pdata->mask << pin_shift);
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+ fname = single_get_pin_function(dev, pin);
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+ snprintf(buf, size, "%pa 0x%08x %s", ®, val,
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+ fname ? fname : "UNCLAIMED");
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+ return 0;
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+}
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+
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+static struct single_func *single_allocate_function(struct udevice *dev,
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+ unsigned int group_pins)
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+{
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+ struct single_func *func;
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+
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+ func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL);
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+ if (!func)
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+ return ERR_PTR(-ENOMEM);
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+
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+ func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins,
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+ GFP_KERNEL);
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+ if (!func->pins)
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+ return ERR_PTR(-ENOMEM);
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+
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+ return func;
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+}
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+
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+static int single_pin_compare(const void *s1, const void *s2)
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+{
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+ int pin1 = *(const unsigned int *)s1;
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+ int pin2 = *(const unsigned int *)s2;
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+
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+ return pin1 - pin2;
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+}
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+
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/**
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* single_configure_pins() - Configure pins based on FDT data
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*
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@@ -42,75 +270,129 @@ struct single_fdt_bits_cfg {
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* @size: Size of the 'pins' array in bytes.
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* The number of register/value pairs in the 'pins' array therefore
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* equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
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+ * @fname: Function name.
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*/
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static int single_configure_pins(struct udevice *dev,
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const struct single_fdt_pin_cfg *pins,
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- int size)
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+ int size, const char *fname)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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- int count = size / sizeof(struct single_fdt_pin_cfg);
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- phys_addr_t n, reg;
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- u32 val;
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+ struct single_priv *priv = dev_get_priv(dev);
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+ int n, pin, count = size / sizeof(struct single_fdt_pin_cfg);
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+ struct single_func *func;
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+ phys_addr_t reg;
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+ u32 offset, val;
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+ /* If function mask is null, needn't enable it. */
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+ if (!pdata->mask)
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+ return 0;
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+
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+ func = single_allocate_function(dev, count);
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+ if (IS_ERR(func))
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+ return PTR_ERR(func);
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+
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+ func->name = fname;
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+ func->npins = 0;
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for (n = 0; n < count; n++, pins++) {
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- reg = fdt32_to_cpu(pins->reg);
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- if ((reg < 0) || (reg > pdata->offset)) {
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- dev_dbg(dev, " invalid register offset 0x%pa\n", ®);
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+ offset = fdt32_to_cpu(pins->reg);
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+ if (offset < 0 || offset > pdata->offset) {
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+ dev_err(dev, " invalid register offset 0x%x\n",
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+ offset);
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continue;
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}
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- reg += pdata->base;
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+
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+ reg = pdata->base + offset;
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val = fdt32_to_cpu(pins->val) & pdata->mask;
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- switch (pdata->width) {
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- case 16:
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- writew((readw(reg) & ~pdata->mask) | val, reg);
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- break;
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- case 32:
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- writel((readl(reg) & ~pdata->mask) | val, reg);
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- break;
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- default:
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- dev_warn(dev, "unsupported register width %i\n",
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- pdata->width);
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+ pin = single_get_pin_by_offset(dev, offset);
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+ if (pin < 0) {
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+ dev_err(dev, " failed to get pin by offset %x\n",
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+ offset);
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continue;
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}
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- dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val);
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+
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+ single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val,
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+ reg);
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+ dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
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+ func->pins[func->npins] = pin;
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+ func->npins++;
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}
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+
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+ qsort(func->pins, func->npins, sizeof(func->pins[0]),
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+ single_pin_compare);
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+ list_add(&func->node, &priv->functions);
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return 0;
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}
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static int single_configure_bits(struct udevice *dev,
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const struct single_fdt_bits_cfg *pins,
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- int size)
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+ int size, const char *fname)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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- int count = size / sizeof(struct single_fdt_bits_cfg);
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- phys_addr_t n, reg;
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- u32 val, mask;
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+ struct single_priv *priv = dev_get_priv(dev);
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+ int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
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+ int npins_in_reg, pin_num_from_lsb;
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+ struct single_func *func;
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+ phys_addr_t reg;
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+ u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
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+ npins_in_reg = pdata->width / priv->bits_per_pin;
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+ func = single_allocate_function(dev, count * npins_in_reg);
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+ if (IS_ERR(func))
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+ return PTR_ERR(func);
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+
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+ func->name = fname;
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+ func->npins = 0;
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for (n = 0; n < count; n++, pins++) {
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- reg = fdt32_to_cpu(pins->reg);
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- if ((reg < 0) || (reg > pdata->offset)) {
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- dev_dbg(dev, " invalid register offset 0x%pa\n", ®);
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+ offset = fdt32_to_cpu(pins->reg);
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+ if (offset < 0 || offset > pdata->offset) {
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+ dev_dbg(dev, " invalid register offset 0x%x\n",
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+ offset);
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+ continue;
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+ }
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+
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+ reg = pdata->base + offset;
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+
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+ pin = single_get_pin_by_offset(dev, offset);
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+ if (pin < 0) {
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+ dev_err(dev, " failed to get pin by offset 0x%pa\n",
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+ ®);
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continue;
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}
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- reg += pdata->base;
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mask = fdt32_to_cpu(pins->mask);
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val = fdt32_to_cpu(pins->val) & mask;
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+ single_write(dev, (single_read(dev, reg) & ~mask) | val, reg);
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+ dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
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- switch (pdata->width) {
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- case 16:
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- writew((readw(reg) & ~mask) | val, reg);
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- break;
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- case 32:
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- writel((readl(reg) & ~mask) | val, reg);
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- break;
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- default:
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- dev_warn(dev, "unsupported register width %i\n",
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- pdata->width);
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- continue;
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+ while (mask) {
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+ bit_pos = __ffs(mask);
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+ pin_num_from_lsb = bit_pos / priv->bits_per_pin;
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+ mask_pos = pdata->mask << bit_pos;
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+ val_pos = val & mask_pos;
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+ submask = mask & mask_pos;
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+
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+ if ((mask & mask_pos) == 0) {
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+ dev_err(dev, "Invalid mask at 0x%x\n", offset);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ mask &= ~mask_pos;
|
|
|
+
|
|
|
+ if (submask != mask_pos) {
|
|
|
+ dev_warn(dev,
|
|
|
+ "Invalid submask 0x%x at 0x%x\n",
|
|
|
+ submask, offset);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ func->pins[func->npins] = pin + pin_num_from_lsb;
|
|
|
+ func->npins++;
|
|
|
}
|
|
|
- dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val);
|
|
|
}
|
|
|
+
|
|
|
+ qsort(func->pins, func->npins, sizeof(func->pins[0]),
|
|
|
+ single_pin_compare);
|
|
|
+ list_add(&func->node, &priv->functions);
|
|
|
return 0;
|
|
|
}
|
|
|
static int single_set_state(struct udevice *dev,
|
|
@@ -128,7 +410,7 @@ static int single_set_state(struct udevice *dev,
|
|
|
dev_dbg(dev, " invalid pin configuration in fdt\n");
|
|
|
return -FDT_ERR_BADSTRUCTURE;
|
|
|
}
|
|
|
- single_configure_pins(dev, prop, len);
|
|
|
+ single_configure_pins(dev, prop, len, config->name);
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
@@ -140,7 +422,7 @@ static int single_set_state(struct udevice *dev,
|
|
|
dev_dbg(dev, " invalid bits configuration in fdt\n");
|
|
|
return -FDT_ERR_BADSTRUCTURE;
|
|
|
}
|
|
|
- single_configure_bits(dev, prop_bits, len);
|
|
|
+ single_configure_bits(dev, prop_bits, len, config->name);
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
@@ -148,20 +430,83 @@ static int single_set_state(struct udevice *dev,
|
|
|
return len;
|
|
|
}
|
|
|
|
|
|
+static const char *single_get_pin_name(struct udevice *dev,
|
|
|
+ unsigned int selector)
|
|
|
+{
|
|
|
+ struct single_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ if (selector >= priv->npins)
|
|
|
+ snprintf(priv->pin_name, PINNAME_SIZE, "Error");
|
|
|
+ else
|
|
|
+ snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector);
|
|
|
+
|
|
|
+ return priv->pin_name;
|
|
|
+}
|
|
|
+
|
|
|
+static int single_get_pins_count(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct single_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ return priv->npins;
|
|
|
+}
|
|
|
+
|
|
|
+static int single_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct single_pdata *pdata = dev_get_plat(dev);
|
|
|
+ struct single_priv *priv = dev_get_priv(dev);
|
|
|
+ u32 size;
|
|
|
+
|
|
|
+ INIT_LIST_HEAD(&priv->functions);
|
|
|
+
|
|
|
+ size = pdata->offset + pdata->width / BITS_PER_BYTE;
|
|
|
+ #if (CONFIG_IS_ENABLED(SANDBOX))
|
|
|
+ priv->sandbox_regs =
|
|
|
+ devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs),
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!priv->sandbox_regs)
|
|
|
+ return -ENOMEM;
|
|
|
+ #endif
|
|
|
+
|
|
|
+ priv->npins = size / (pdata->width / BITS_PER_BYTE);
|
|
|
+ if (pdata->bits_per_mux) {
|
|
|
+ priv->bits_per_pin = fls(pdata->mask);
|
|
|
+ priv->npins *= (pdata->width / priv->bits_per_pin);
|
|
|
+ }
|
|
|
+
|
|
|
+ dev_dbg(dev, "%d pins\n", priv->npins);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
static int single_of_to_plat(struct udevice *dev)
|
|
|
{
|
|
|
fdt_addr_t addr;
|
|
|
- u32 of_reg[2];
|
|
|
- int res;
|
|
|
+ fdt_size_t size;
|
|
|
struct single_pdata *pdata = dev_get_plat(dev);
|
|
|
+ int ret;
|
|
|
|
|
|
- pdata->width =
|
|
|
- dev_read_u32_default(dev, "pinctrl-single,register-width", 0);
|
|
|
+ ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "missing register width\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
|
|
|
- res = dev_read_u32_array(dev, "reg", of_reg, 2);
|
|
|
- if (res)
|
|
|
- return res;
|
|
|
- pdata->offset = of_reg[1] - pdata->width / 8;
|
|
|
+ switch (pdata->width) {
|
|
|
+ case 8:
|
|
|
+ case 16:
|
|
|
+ case 32:
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ dev_err(dev, "wrong register width\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ addr = dev_read_addr_size(dev, "reg", &size);
|
|
|
+ if (addr == FDT_ADDR_T_NONE) {
|
|
|
+ dev_err(dev, "failed to get base register size\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ pdata->offset = size - pdata->width / BITS_PER_BYTE;
|
|
|
|
|
|
addr = dev_read_addr(dev);
|
|
|
if (addr == FDT_ADDR_T_NONE) {
|
|
@@ -170,15 +515,22 @@ static int single_of_to_plat(struct udevice *dev)
|
|
|
}
|
|
|
pdata->base = addr;
|
|
|
|
|
|
- pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask",
|
|
|
- 0xffffffff);
|
|
|
+ ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask);
|
|
|
+ if (ret) {
|
|
|
+ pdata->mask = 0;
|
|
|
+ dev_warn(dev, "missing function register mask\n");
|
|
|
+ }
|
|
|
+
|
|
|
pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux");
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
const struct pinctrl_ops single_pinctrl_ops = {
|
|
|
+ .get_pins_count = single_get_pins_count,
|
|
|
+ .get_pin_name = single_get_pin_name,
|
|
|
.set_state = single_set_state,
|
|
|
+ .get_pin_muxing = single_get_pin_muxing,
|
|
|
};
|
|
|
|
|
|
static const struct udevice_id single_pinctrl_match[] = {
|
|
@@ -192,5 +544,7 @@ U_BOOT_DRIVER(single_pinctrl) = {
|
|
|
.of_match = single_pinctrl_match,
|
|
|
.ops = &single_pinctrl_ops,
|
|
|
.plat_auto = sizeof(struct single_pdata),
|
|
|
+ .priv_auto = sizeof(struct single_priv),
|
|
|
.of_to_plat = single_of_to_plat,
|
|
|
+ .probe = single_probe,
|
|
|
};
|