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@@ -74,35 +74,47 @@ struct utmi_phy_data {
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* Eth_port_0 that include (SGMII0, RXAUI0, SFI)
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*/
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struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
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- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
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- {PHY_TYPE_SATA1, 0x4} } },
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- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
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- {PHY_TYPE_SATA0, 0x4} } },
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- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
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- {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
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- {PHY_TYPE_SATA0, 0x4} } },
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- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
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- {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
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- {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
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- {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
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- {PHY_TYPE_SGMII1, 0x1} } },
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- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
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- {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
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+ /* Lane 0 */
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+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},
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+ {COMPHY_TYPE_SATA1, 0x4} } },
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+ /* Lane 1 */
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+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
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+ {COMPHY_TYPE_SATA0, 0x4} } },
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+ /* Lane 2 */
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+ {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},
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+ {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},
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+ {COMPHY_TYPE_SATA0, 0x4} } },
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+ /* Lane 3 */
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+ {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},
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+ {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } },
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+ /* Lane 4 */
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+ {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},
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+ {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},
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+ {COMPHY_TYPE_SGMII1, 0x1} } },
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+ /* Lane 5 */
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+ {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
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+ {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } },
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};
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struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
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- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
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- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
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- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
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- {PHY_TYPE_PEX0, 0x4} } },
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- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
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- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
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- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
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- {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
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- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
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- {PHY_TYPE_USB3_HOST1, 0x1},
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- {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
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- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
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+ /* Lane 0 */
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+ {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } },
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+ /* Lane 1 */
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+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0},
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+ {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2},
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+ {COMPHY_TYPE_PEX0, 0x4} } },
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+ /* Lane 2 */
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+ {3, {{COMPHY_TYPE_UNCONNECTED, 0x0},
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+ {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } },
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+ /* Lane 3 */
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+ {3, {{COMPHY_TYPE_UNCONNECTED, 0x0},
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+ {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } },
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+ /* Lane 4 */
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+ {4, {{COMPHY_TYPE_UNCONNECTED, 0x0},
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+ {COMPHY_TYPE_USB3_HOST1, 0x1},
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+ {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } },
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+ /* Lane 5 */
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+ {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } },
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};
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static u32 polling_with_timeout(void __iomem *addr, u32 val,
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@@ -868,9 +880,9 @@ static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
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/* Fix the type after check the PHY and PIPE configuration */
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for (lane = 0; lane < comphy_max_count; lane++) {
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- if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
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- (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
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- serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
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+ if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) &&
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+ (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED))
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+ serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED;
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}
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}
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@@ -895,7 +907,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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/* Check if the first 4 lanes configured as By-4 */
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for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
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lane++, ptr_comphy_map++) {
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- if (ptr_comphy_map->type != PHY_TYPE_PEX0)
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+ if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
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break;
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pcie_width++;
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}
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@@ -912,14 +924,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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pcie_width = 1;
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}
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switch (ptr_comphy_map->type) {
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- case PHY_TYPE_UNCONNECTED:
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- case PHY_TYPE_IGNORE:
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+ case COMPHY_TYPE_UNCONNECTED:
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+ case COMPHY_TYPE_IGNORE:
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continue;
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break;
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- case PHY_TYPE_PEX0:
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- case PHY_TYPE_PEX1:
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- case PHY_TYPE_PEX2:
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- case PHY_TYPE_PEX3:
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+ case COMPHY_TYPE_PEX0:
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+ case COMPHY_TYPE_PEX1:
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+ case COMPHY_TYPE_PEX2:
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+ case COMPHY_TYPE_PEX3:
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mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
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ptr_comphy_map->clk_src,
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COMPHY_PCIE_MODE,
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@@ -928,30 +940,30 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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ptr_chip_cfg->comphy_base_addr, lane,
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mode);
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break;
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- case PHY_TYPE_SATA0:
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- case PHY_TYPE_SATA1:
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- case PHY_TYPE_SATA2:
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- case PHY_TYPE_SATA3:
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+ case COMPHY_TYPE_SATA0:
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+ case COMPHY_TYPE_SATA1:
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+ case COMPHY_TYPE_SATA2:
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+ case COMPHY_TYPE_SATA3:
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mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
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ret = comphy_sata_power_up(lane, hpipe_base_addr,
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comphy_base_addr,
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ptr_chip_cfg->cp_index,
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mode);
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break;
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- case PHY_TYPE_USB3_HOST0:
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- case PHY_TYPE_USB3_HOST1:
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- case PHY_TYPE_USB3_DEVICE:
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+ case COMPHY_TYPE_USB3_HOST0:
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+ case COMPHY_TYPE_USB3_HOST1:
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+ case COMPHY_TYPE_USB3_DEVICE:
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ret = comphy_usb3_power_up(lane, hpipe_base_addr,
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comphy_base_addr);
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break;
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- case PHY_TYPE_SGMII0:
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- case PHY_TYPE_SGMII1:
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- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
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+ case COMPHY_TYPE_SGMII0:
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+ case COMPHY_TYPE_SGMII1:
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+ if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
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debug("Warning: ");
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debug("SGMII PHY speed in lane %d is invalid,",
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lane);
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debug(" set PHY speed to 1.25G\n");
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- ptr_comphy_map->speed = PHY_SPEED_1_25G;
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+ ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
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}
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/*
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@@ -965,12 +977,12 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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ptr_chip_cfg->comphy_base_addr, lane,
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mode);
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break;
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- case PHY_TYPE_SGMII2:
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- case PHY_TYPE_SGMII3:
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- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
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+ case COMPHY_TYPE_SGMII2:
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+ case COMPHY_TYPE_SGMII3:
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+ if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
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debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
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lane);
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- ptr_comphy_map->speed = PHY_SPEED_1_25G;
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+ ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
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}
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mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
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@@ -980,7 +992,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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ptr_chip_cfg->comphy_base_addr, lane,
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mode);
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break;
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- case PHY_TYPE_SFI:
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+ case COMPHY_TYPE_SFI:
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mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
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COMPHY_UNIT_ID0,
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ptr_comphy_map->speed);
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@@ -988,8 +1000,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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ptr_chip_cfg->comphy_base_addr, lane,
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mode);
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break;
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- case PHY_TYPE_RXAUI0:
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- case PHY_TYPE_RXAUI1:
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+ case COMPHY_TYPE_RXAUI0:
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+ case COMPHY_TYPE_RXAUI1:
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ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
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comphy_base_addr);
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break;
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@@ -1001,9 +1013,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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if (ret == 0) {
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/*
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* If interface wans't initialized, set the lane to
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- * PHY_TYPE_UNCONNECTED state.
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+ * COMPHY_TYPE_UNCONNECTED state.
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*/
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- ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
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+ ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
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pr_err("PLL is not locked - Failed to initialize lane %d\n",
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lane);
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}
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