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@@ -0,0 +1,325 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright 2017~2020 NXP
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+ *
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+ */
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+
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+#include <config.h>
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+#include <common.h>
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+#include <asm/io.h>
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+#include <asm/arch/clock.h>
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+#include <asm/arch/sys_proto.h>
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+#include <dm.h>
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+#include <dm/device-internal.h>
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+#include <dm/device.h>
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+#include <errno.h>
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+#include <fuse.h>
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+#include <malloc.h>
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+#include <thermal.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define SITES_MAX 16
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+
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+#define TMR_DISABLE 0x0
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+#define TMR_ME 0x80000000
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+#define TMR_ALPF 0x0c000000
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+#define TMTMIR_DEFAULT 0x00000002
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+#define TIER_DISABLE 0x0
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+
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+/*
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+ * i.MX TMU Registers
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+ */
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+struct imx_tmu_site_regs {
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+ u32 tritsr; /* Immediate Temperature Site Register */
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+ u32 tratsr; /* Average Temperature Site Register */
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+ u8 res0[0x8];
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+};
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+
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+struct imx_tmu_regs {
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+ u32 tmr; /* Mode Register */
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+ u32 tsr; /* Status Register */
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+ u32 tmtmir; /* Temperature measurement interval Register */
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+ u8 res0[0x14];
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+ u32 tier; /* Interrupt Enable Register */
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+ u32 tidr; /* Interrupt Detect Register */
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+ u32 tiscr; /* Interrupt Site Capture Register */
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+ u32 ticscr; /* Interrupt Critical Site Capture Register */
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+ u8 res1[0x10];
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+ u32 tmhtcrh; /* High Temperature Capture Register */
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+ u32 tmhtcrl; /* Low Temperature Capture Register */
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+ u8 res2[0x8];
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+ u32 tmhtitr; /* High Temperature Immediate Threshold */
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+ u32 tmhtatr; /* High Temperature Average Threshold */
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+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
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+ u8 res3[0x24];
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+ u32 ttcfgr; /* Temperature Configuration Register */
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+ u32 tscfgr; /* Sensor Configuration Register */
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+ u8 res4[0x78];
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+ struct imx_tmu_site_regs site[SITES_MAX];
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+ u8 res5[0x9f8];
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+ u32 ipbrr0; /* IP Block Revision Register 0 */
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+ u32 ipbrr1; /* IP Block Revision Register 1 */
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+ u8 res6[0x310];
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+ u32 ttr0cr; /* Temperature Range 0 Control Register */
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+ u32 ttr1cr; /* Temperature Range 1 Control Register */
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+ u32 ttr2cr; /* Temperature Range 2 Control Register */
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+ u32 ttr3cr; /* Temperature Range 3 Control Register */
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+};
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+
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+struct imx_tmu_plat {
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+ int critical;
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+ int alert;
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+ int polling_delay;
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+ int id;
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+ bool zone_node;
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+ struct imx_tmu_regs *regs;
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+};
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+
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+static int read_temperature(struct udevice *dev, int *temp)
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+{
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+ struct imx_tmu_plat *pdata = dev_get_platdata(dev);
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+ u32 val;
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+
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+ do {
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+ val = readl(&pdata->regs->site[pdata->id].tritsr);
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+ } while (!(val & 0x80000000));
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+
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+ *temp = (val & 0xff) * 1000;
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+
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+ return 0;
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+}
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+
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+int imx_tmu_get_temp(struct udevice *dev, int *temp)
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+{
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+ struct imx_tmu_plat *pdata = dev_get_platdata(dev);
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+ int cpu_tmp = 0;
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+ int ret;
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+
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+ ret = read_temperature(dev, &cpu_tmp);
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+ if (ret)
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+ return ret;
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+
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+ while (cpu_tmp >= pdata->alert) {
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+ printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", cpu_tmp, pdata->alert, pdata->critical);
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+ puts(" waiting...\n");
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+ mdelay(pdata->polling_delay);
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+ ret = read_temperature(dev, &cpu_tmp);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ *temp = cpu_tmp / 1000;
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+
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+ return 0;
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+}
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+
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+static const struct dm_thermal_ops imx_tmu_ops = {
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+ .get_temp = imx_tmu_get_temp,
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+};
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+
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+static int imx_tmu_calibration(struct udevice *dev)
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+{
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+ int i, val, len, ret;
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+ u32 range[4];
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+ const fdt32_t *calibration;
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+ struct imx_tmu_plat *pdata = dev_get_platdata(dev);
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+
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+ debug("%s\n", __func__);
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+
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+ ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
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+ if (ret) {
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+ printf("TMU: missing calibration range, ret = %d.\n", ret);
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+ return ret;
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+ }
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+
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+ /* Init temperature range registers */
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+ writel(range[0], &pdata->regs->ttr0cr);
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+ writel(range[1], &pdata->regs->ttr1cr);
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+ writel(range[2], &pdata->regs->ttr2cr);
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+ writel(range[3], &pdata->regs->ttr3cr);
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+
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+ calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
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+ if (!calibration || len % 8) {
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+ printf("TMU: invalid calibration data.\n");
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+ return -ENODEV;
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+ }
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+
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+ for (i = 0; i < len; i += 8, calibration += 2) {
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+ val = fdt32_to_cpu(*calibration);
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+ writel(val, &pdata->regs->ttcfgr);
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+ val = fdt32_to_cpu(*(calibration + 1));
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+ writel(val, &pdata->regs->tscfgr);
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+ }
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+
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+ return 0;
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+}
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+
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+static void imx_tmu_init(struct imx_tmu_plat *pdata)
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+{
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+ debug("%s\n", __func__);
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+
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+ /* Disable monitoring */
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+ writel(TMR_DISABLE, &pdata->regs->tmr);
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+
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+ /* Disable interrupt, using polling instead */
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+ writel(TIER_DISABLE, &pdata->regs->tier);
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+
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+ /* Set update_interval */
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+ writel(TMTMIR_DEFAULT, &pdata->regs->tmtmir);
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+}
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+
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+static int imx_tmu_enable_msite(struct udevice *dev)
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+{
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+ struct imx_tmu_plat *pdata = dev_get_platdata(dev);
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+ u32 reg;
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+
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+ debug("%s\n", __func__);
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+
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+ if (!pdata->regs)
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+ return -EIO;
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+
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+ /* Clear the ME before setting MSITE and ALPF*/
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+ reg = readl(&pdata->regs->tmr);
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+ reg &= ~TMR_ME;
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+ writel(reg, &pdata->regs->tmr);
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+
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+ reg |= 1 << (15 - pdata->id);
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+ reg |= TMR_ALPF;
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+ writel(reg, &pdata->regs->tmr);
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+
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+ /* Enable ME */
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+ reg |= TMR_ME;
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+ writel(reg, &pdata->regs->tmr);
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+
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+ return 0;
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+}
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+
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+static int imx_tmu_bind(struct udevice *dev)
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+{
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+ struct imx_tmu_plat *pdata = dev_get_platdata(dev);
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+ int ret;
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+ ofnode node, offset;
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+ const char *name;
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+ const void *prop;
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+
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+ debug("%s dev name %s\n", __func__, dev->name);
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+
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+ prop = dev_read_prop(dev, "compatible", NULL);
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+ if (!prop)
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+ return 0;
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+
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+ pdata->zone_node = 1;
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+
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+ node = ofnode_path("/thermal-zones");
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+ ofnode_for_each_subnode(offset, node) {
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+ /* Bind the subnode to this driver */
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+ name = ofnode_get_name(offset);
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+
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+ ret = device_bind_with_driver_data(dev, dev->driver, name,
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+ dev->driver_data, offset,
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+ NULL);
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+ if (ret)
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+ printf("Error binding driver '%s': %d\n",
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+ dev->driver->name, ret);
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+ }
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+
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+ return 0;
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+}
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+
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+static int imx_tmu_parse_fdt(struct udevice *dev)
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+{
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+ struct imx_tmu_plat *pdata = dev_get_platdata(dev), *p_parent_data;
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+ struct ofnode_phandle_args args;
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+ ofnode trips_np;
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+ int ret;
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+
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+ debug("%s dev name %s\n", __func__, dev->name);
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+
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+ if (pdata->zone_node) {
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+ pdata->regs = (struct imx_tmu_regs *)dev_read_addr_ptr(dev);
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+
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+ if (!pdata->regs)
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+ return -EINVAL;
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+ return 0;
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+ }
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+
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+ p_parent_data = dev_get_platdata(dev->parent);
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+ if (p_parent_data->zone_node)
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+ pdata->regs = p_parent_data->regs;
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+
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+ ret = dev_read_phandle_with_args(dev, "thermal-sensors",
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+ "#thermal-sensor-cells",
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+ 0, 0, &args);
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+ if (ret)
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+ return ret;
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+
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+ if (!ofnode_equal(args.node, dev_ofnode(dev->parent)))
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+ return -EFAULT;
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+
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+ if (args.args_count >= 1)
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+ pdata->id = args.args[0];
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+ else
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+ pdata->id = 0;
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+
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+ debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
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+
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+ pdata->polling_delay = dev_read_u32_default(dev, "polling-delay", 1000);
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+
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+ trips_np = ofnode_path("/thermal-zones/cpu-thermal/trips");
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+ ofnode_for_each_subnode(trips_np, trips_np) {
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+ const char *type;
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+
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+ type = ofnode_get_property(trips_np, "type", NULL);
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+ if (!type)
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+ continue;
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+ if (!strcmp(type, "critical"))
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+ pdata->critical = ofnode_read_u32_default(trips_np, "temperature", 85);
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+ else if (strcmp(type, "passive") == 0)
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+ pdata->alert = ofnode_read_u32_default(trips_np, "temperature", 80);
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+ else
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+ continue;
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+ }
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+
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+ debug("id %d polling_delay %d, critical %d, alert %d\n",
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+ pdata->id, pdata->polling_delay, pdata->critical, pdata->alert);
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+
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+ return 0;
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+}
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+
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+static int imx_tmu_probe(struct udevice *dev)
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+{
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+ struct imx_tmu_plat *pdata = dev_get_platdata(dev);
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+ int ret;
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+
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+ ret = imx_tmu_parse_fdt(dev);
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+ if (ret) {
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+ printf("Error in parsing TMU FDT %d\n", ret);
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+ return ret;
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+ }
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+
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+ if (pdata->zone_node) {
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+ imx_tmu_init(pdata);
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+ imx_tmu_calibration(dev);
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+ } else {
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+ imx_tmu_enable_msite(dev);
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct udevice_id imx_tmu_ids[] = {
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+ { .compatible = "fsl,imx8mq-tmu", },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(imx_tmu) = {
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+ .name = "imx_tmu",
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+ .id = UCLASS_THERMAL,
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+ .ops = &imx_tmu_ops,
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+ .of_match = imx_tmu_ids,
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+ .bind = imx_tmu_bind,
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+ .probe = imx_tmu_probe,
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+ .platdata_auto_alloc_size = sizeof(struct imx_tmu_plat),
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+ .flags = DM_FLAG_PRE_RELOC,
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+};
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