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@@ -94,11 +94,6 @@ static inline u32 sp_readl(void __iomem *addr, unsigned int offset)
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return readl(addr + offset);
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}
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-static inline void sp_writel(void __iomem *addr, unsigned int offset, u32 data)
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-{
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- writel(data, addr + offset);
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-}
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-
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/**
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* k3_sec_proxy_of_xlate() - Translation of phandle to channel
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* @chan: Mailbox channel
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@@ -241,15 +236,20 @@ static int k3_sec_proxy_send(struct mbox_chan *chan, const void *data)
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/* Ensure all unused data is 0 */
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data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
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writel(data_trail, data_reg);
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- data_reg++;
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+ data_reg += sizeof(u32);
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}
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/*
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* 'data_reg' indicates next register to write. If we did not already
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* write on tx complete reg(last reg), we must do so for transmit
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+ * In addition, we also need to make sure all intermediate data
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+ * registers(if any required), are reset to 0 for TISCI backward
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+ * compatibility to be maintained.
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*/
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- if (data_reg <= (spt->data + spm->desc->data_end_offset))
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- sp_writel(spt->data, spm->desc->data_end_offset, 0);
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+ while (data_reg <= (spt->data + spm->desc->data_end_offset)) {
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+ writel(0x0, data_reg);
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+ data_reg += sizeof(u32);
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+ }
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debug("%s: Message successfully sent on thread %ld\n",
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__func__, chan->id);
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