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@@ -54,6 +54,7 @@
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ next-level-cache = <&l2cache>;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -77,6 +78,7 @@
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ next-level-cache = <&l2cache>;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -100,6 +102,7 @@
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ next-level-cache = <&l2cache>;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -123,6 +126,7 @@
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ next-level-cache = <&l2cache>;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -162,6 +166,13 @@
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clocks = <&prci PRCI_CLK_TLCLK>;
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status = "disabled";
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};
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+ dma: dma@3000000 {
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+ compatible = "sifive,fu540-c000-pdma";
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+ reg = <0x0 0x3000000 0x0 0x8000>;
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+ interrupt-parent = <&plic0>;
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+ interrupts = <23 24 25 26 27 28 29 30>;
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+ #dma-cells = <1>;
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+ };
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uart1: serial@10011000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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reg = <0x0 0x10011000 0x0 0x1000>;
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@@ -246,6 +257,30 @@
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#pwm-cells = <3>;
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status = "disabled";
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};
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-
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+ l2cache: cache-controller@2010000 {
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+ compatible = "sifive,fu540-c000-ccache", "cache";
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+ cache-block-size = <64>;
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+ cache-level = <2>;
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+ cache-sets = <1024>;
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+ cache-size = <2097152>;
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+ cache-unified;
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+ interrupt-parent = <&plic0>;
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+ interrupts = <1 2 3>;
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+ reg = <0x0 0x2010000 0x0 0x1000>;
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+ };
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+ gpio: gpio@10060000 {
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+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
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+ interrupt-parent = <&plic0>;
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+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
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+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
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+ <21>, <22>;
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+ reg = <0x0 0x10060000 0x0 0x1000>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ clocks = <&prci PRCI_CLK_TLCLK>;
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+ status = "disabled";
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+ };
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};
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};
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