瀏覽代碼

spl: satrfive: bus_root switch to pll2.

High-speed emmc/sdio support

Signed-off-by: samin <samin.guo@starfivetech.com>
samin 2 年之前
父節點
當前提交
1f6321dbaf
共有 2 個文件被更改,包括 0 次插入9 次删除
  1. 0 5
      arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
  2. 0 4
      board/starfive/evb/spl.c

+ 0 - 5
arch/riscv/include/asm/arch-jh7110/jh7110-regs.h

@@ -82,11 +82,6 @@
 #define CLK_QSPI_REF_SW_SHIFT	24
 #define CLK_QSPI_REF_SW_MASK	0x1000000U
 
-#define CLK_SDIO_SOURCEMUX_OFFSET	0x14
-#define CLK_SDIO_SCLK_SW_SHIFT		24
-#define CLK_SDIO_SCLK_SW_MASK		0x1000000U
-
-
 #define PLL0_DACPD_SHIFT	0x18U
 #define PLL0_DACPD_MASK	0x1000000U
 #define PLL0_DSMPD_SHIFT	0x19U

+ 0 - 4
board/starfive/evb/spl.c

@@ -116,10 +116,6 @@ void board_init_f(ulong dummy)
 		CLK_QSPI_REF_SW_MASK,
 		(0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
 
-	clrsetbits_le32(SYS_CRG_BASE + CLK_SDIO_SOURCEMUX_OFFSET,
-	CLK_SDIO_SCLK_SW_MASK,
-	(0 << CLK_SDIO_SCLK_SW_SHIFT) & CLK_SDIO_SCLK_SW_MASK);
-
 	/*set GPIO to 1.8v*/
 	setbits_le32(SYS_SYSCON_BASE + 0xC, 0xf);