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@@ -82,11 +82,6 @@
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#define CLK_QSPI_REF_SW_SHIFT 24
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#define CLK_QSPI_REF_SW_MASK 0x1000000U
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-#define CLK_SDIO_SOURCEMUX_OFFSET 0x14
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-#define CLK_SDIO_SCLK_SW_SHIFT 24
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-#define CLK_SDIO_SCLK_SW_MASK 0x1000000U
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-
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-
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#define PLL0_DACPD_SHIFT 0x18U
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#define PLL0_DACPD_MASK 0x1000000U
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#define PLL0_DSMPD_SHIFT 0x19U
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