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@@ -0,0 +1,158 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2021, Xilinx, Inc.
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+ */
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+
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+#define LOG_CATEGORY UCLASS_RTC
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <rtc.h>
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+#include <asm/io.h>
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+
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+/* RTC Registers */
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+#define RTC_SET_TM_WR 0x00
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+#define RTC_SET_TM_RD 0x04
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+#define RTC_CALIB_WR 0x08
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+#define RTC_CUR_TM 0x10
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+#define RTC_INT_STS 0x20
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+#define RTC_CTRL 0x40
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+
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+#define RTC_INT_SEC BIT(0)
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+#define RTC_BATT_EN BIT(31)
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+#define RTC_CALIB_DEF 0x198233
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+#define RTC_CALIB_MASK 0x1FFFFF
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+
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+struct zynqmp_rtc_priv {
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+ fdt_addr_t base;
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+ unsigned int calibval;
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+};
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+
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+static int zynqmp_rtc_get(struct udevice *dev, struct rtc_time *tm)
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+{
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+ struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
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+ u32 status;
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+ unsigned long read_time;
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+
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+ status = readl(priv->base + RTC_INT_STS);
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+
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+ if (status & RTC_INT_SEC) {
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+ /*
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+ * RTC has updated the CURRENT_TIME with the time written into
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+ * SET_TIME_WRITE register.
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+ */
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+ read_time = readl(priv->base + RTC_CUR_TM);
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+ } else {
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+ /*
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+ * Time written in SET_TIME_WRITE has not yet updated into
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+ * the seconds read register, so read the time from the
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+ * SET_TIME_WRITE instead of CURRENT_TIME register.
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+ * Since we add +1 sec while writing, we need to -1 sec while
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+ * reading.
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+ */
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+ read_time = readl(priv->base + RTC_SET_TM_RD) - 1;
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+ }
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+
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+ rtc_to_tm(read_time, tm);
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+
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+ return 0;
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+}
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+
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+static int zynqmp_rtc_set(struct udevice *dev, const struct rtc_time *tm)
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+{
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+ struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
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+ unsigned long new_time = 0;
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+
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+ if (tm)
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+ /*
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+ * The value written will be updated after 1 sec into the
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+ * seconds read register, so we need to program time +1 sec
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+ * to get the correct time on read.
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+ */
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+ new_time = rtc_mktime(tm) + 1;
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+
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+ /*
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+ * Writing into calibration register will clear the Tick Counter and
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+ * force the next second to be signaled exactly in 1 second period
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+ */
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+ priv->calibval &= RTC_CALIB_MASK;
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+ writel(priv->calibval, (priv->base + RTC_CALIB_WR));
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+
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+ writel(new_time, priv->base + RTC_SET_TM_WR);
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+
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+ /*
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+ * Clear the rtc interrupt status register after setting the
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+ * time. During a read_time function, the code should read the
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+ * RTC_INT_STATUS register and if bit 0 is still 0, it means
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+ * that one second has not elapsed yet since RTC was set and
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+ * the current time should be read from SET_TIME_READ register;
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+ * otherwise, CURRENT_TIME register is read to report the time
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+ */
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+ writel(RTC_INT_SEC, priv->base + RTC_INT_STS);
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+
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+ return 0;
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+}
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+
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+static int zynqmp_rtc_reset(struct udevice *dev)
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+{
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+ return zynqmp_rtc_set(dev, NULL);
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+}
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+
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+static int zynqmp_rtc_init(struct udevice *dev)
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+{
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+ struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
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+ u32 rtc_ctrl;
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+
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+ /* Enable RTC switch to battery when VCC_PSAUX is not available */
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+ rtc_ctrl = readl(priv->base + RTC_CTRL);
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+ rtc_ctrl |= RTC_BATT_EN;
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+ writel(rtc_ctrl, priv->base + RTC_CTRL);
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+
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+ /*
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+ * Based on crystal freq of 33.330 KHz
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+ * set the seconds counter and enable, set fractions counter
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+ * to default value suggested as per design spec
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+ * to correct RTC delay in frequency over period of time.
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+ */
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+ priv->calibval &= RTC_CALIB_MASK;
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+ writel(priv->calibval, (priv->base + RTC_CALIB_WR));
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+
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+ return 0;
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+}
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+
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+static int zynqmp_rtc_probe(struct udevice *dev)
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+{
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+ struct zynqmp_rtc_priv *priv = dev_get_priv(dev);
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+ int ret;
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+
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+ priv->base = dev_read_addr(dev);
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+ if (priv->base == FDT_ADDR_T_NONE)
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+ return -EINVAL;
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+
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+ priv->calibval = dev_read_u32_default(dev, "calibration",
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+ RTC_CALIB_DEF);
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+
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+ ret = zynqmp_rtc_init(dev);
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+
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+ return ret;
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+}
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+
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+static const struct rtc_ops zynqmp_rtc_ops = {
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+ .get = zynqmp_rtc_get,
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+ .set = zynqmp_rtc_set,
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+ .reset = zynqmp_rtc_reset,
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+};
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+
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+static const struct udevice_id zynqmp_rtc_ids[] = {
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+ { .compatible = "xlnx,zynqmp-rtc" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(rtc_zynqmp) = {
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+ .name = "rtc-zynqmp",
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+ .id = UCLASS_RTC,
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+ .probe = zynqmp_rtc_probe,
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+ .of_match = zynqmp_rtc_ids,
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+ .ops = &zynqmp_rtc_ops,
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+ .priv_auto = sizeof(struct zynqmp_rtc_priv),
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+};
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