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@@ -447,34 +447,34 @@ static u32 decode_fracpll(enum clk_root_src frac_pll)
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}
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/* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
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- if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
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+ if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
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return 0;
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- if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
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+ if ((pll_gnrl_ctl & RST_MASK) == 0)
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return 0;
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/*
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* When BYPASS is equal to 1, PLL enters the bypass mode
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* regardless of the values of RESETB
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*/
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- if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
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+ if (pll_gnrl_ctl & BYPASS_MASK)
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return 24000000u;
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- if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
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+ if (!(pll_gnrl_ctl & LOCK_STATUS)) {
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puts("pll not locked\n");
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return 0;
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}
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- if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
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+ if (!(pll_gnrl_ctl & CLKE_MASK))
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return 0;
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- main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
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- INTPLL_MAIN_DIV_SHIFT;
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- pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
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- INTPLL_PRE_DIV_SHIFT;
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- post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
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- INTPLL_POST_DIV_SHIFT;
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+ main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
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+ MDIV_SHIFT;
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+ pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
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+ PDIV_SHIFT;
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+ post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
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+ SDIV_SHIFT;
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- k = pll_fdiv_ctl1 & GENMASK(15, 0);
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+ k = pll_fdiv_ctl1 & KDIV_MASK;
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return lldiv((main_div * 65536 + k) * 24000000ULL,
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65536 * pre_div * (1 << post_div));
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