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@@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008-2016 Freescale Semiconductor, Inc.
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- * Copyright 2017-2018 NXP Semiconductor
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+ * Copyright 2017-2020 NXP Semiconductor
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*/
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/*
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@@ -2363,38 +2363,6 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
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unsigned int ip_rev = 0;
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unsigned int unq_mrs_en = 0;
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int cs_en = 1;
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-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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- unsigned int ddr_freq;
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-#endif
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-#if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
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- defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
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- defined(CONFIG_SYS_FSL_ERRATUM_A009942)
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- struct ccsr_ddr __iomem *ddrc;
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-
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- switch (ctrl_num) {
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- case 0:
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- ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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- break;
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-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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- case 1:
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- ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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- break;
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-#endif
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-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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- case 2:
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- ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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- break;
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-#endif
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-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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- case 3:
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- ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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- break;
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-#endif
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- default:
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- printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
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- return 1;
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- }
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-#endif
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memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
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@@ -2615,37 +2583,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
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ddr->debug[2] |= 0x00000200; /* set bit 22 */
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#endif
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-#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
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- /* Erratum applies when accumulated ECC is used, or DBI is enabled */
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-#define IS_ACC_ECC_EN(v) ((v) & 0x4)
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-#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
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- if (has_erratum_a008378()) {
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- if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
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- IS_DBI(ddr->ddr_sdram_cfg_3)) {
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- ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
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- ddr->debug[28] |= (0x9 << 20);
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- }
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- }
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-#endif
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-
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-#ifdef CONFIG_SYS_FSL_ERRATUM_A008109
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- ddr->ddr_sdram_cfg_2 = ddr_in32(&ddr->ddr_sdram_cfg_2) | 0x800; /* DDR_SLOW */
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- ddr->debug[18] = ddr_in32(&ddrc->debug[18]) | 0x2;
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- ddr->debug[28] = 0x30000000;
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-#endif
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-
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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- ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
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- ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
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- ddr->debug[28] &= 0xff0fff00;
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- if (ddr_freq <= 1333)
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- ddr->debug[28] |= 0x0080006a;
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- else if (ddr_freq <= 1600)
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- ddr->debug[28] |= 0x0070006f;
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- else if (ddr_freq <= 1867)
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- ddr->debug[28] |= 0x00700076;
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- else if (ddr_freq <= 2133)
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- ddr->debug[28] |= 0x0060007b;
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if (popts->cpo_sample)
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ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
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popts->cpo_sample;
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