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@@ -8,7 +8,6 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3128-cru.h>
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-#include "skeleton.dtsi"
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/ {
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compatible = "rockchip,rk3128";
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@@ -34,11 +33,6 @@
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mmc1 = &sdmmc;
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};
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- memory {
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- device_type = "memory";
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- reg = <0x60000000 0x40000000>;
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- };
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-
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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@@ -52,10 +46,10 @@
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#size-cells = <0>;
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enable-method = "rockchip,rk3128-smp";
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- cpu0:cpu@0x000 {
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+ cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- reg = <0x000>;
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+ reg = <0x0>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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@@ -65,22 +59,22 @@
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clocks = <&cru ARMCLK>;
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};
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- cpu1:cpu@0x001 {
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+ cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- reg = <0x001>;
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+ reg = <0x1>;
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};
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- cpu2:cpu@0x002 {
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+ cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- reg = <0x002>;
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+ reg = <0x2>;
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};
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- cpu3:cpu@0x003 {
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+ cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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- reg = <0x003>;
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+ reg = <0x3>;
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};
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};
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@@ -165,14 +159,14 @@
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interrupt-parent = <&gic>;
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ranges;
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- pdma: pdma@20078000 {
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+ pdma: dma-controller@20078000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20078000 0x4000>;
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arm,pl330-broken-no-flushp;//2
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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- clocks = <&cru ACLK_DMAC2>;
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+ clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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@@ -186,7 +180,6 @@
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xin12m: xin12m {
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compatible = "fixed-clock";
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- clocks = <&xin24m>;
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clock-frequency = <12000000>;
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clock-output-names = "xin12m";
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#clock-cells = <0>;
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@@ -207,10 +200,10 @@
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rockchip,broadcast = <1>;
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};
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- watchdog: wdt@2004c000 {
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- compatible = "rockchip,watch dog";
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+ watchdog: watchdog@2004c000 {
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+ compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
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reg = <0x2004c000 0x100>;
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- clock-names = "pclk_wdt";
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+ clocks = <&cru PCLK_WDT>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,irq = <1>;
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rockchip,timeout = <60>;
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@@ -224,29 +217,21 @@
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#reset-cells = <1>;
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};
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- nandc: nandc@10500000 {
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- compatible = "rockchip,rk-nandc";
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+ nandc: nand-controller@10500000 {
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+ compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
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reg = <0x10500000 0x4000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
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- nandc_id = <0>;
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- clocks = <&cru SCLK_NANDC>,
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- <&cru HCLK_NANDC>,
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- <&cru SRST_NANDC>;
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- clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
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- };
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-
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- dmc: dmc@20004000 {
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- u-boot,dm-pre-reloc;
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- compatible = "rockchip,rk3128-dmc", "syscon";
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- reg = <0x0 0x20004000 0x0 0x1000>;
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+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
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+ clock-names = "ahb", "nfc";
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};
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cru: clock-controller@20000000 {
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- u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3128-cru";
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reg = <0x20000000 0x1000>;
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+ clocks = <&xin24m>;
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+ clock-names = "xin24m";
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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@@ -254,7 +239,7 @@
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assigned-clock-rates = <594000000>;
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};
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- uart0: serial0@20060000 {
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+ uart0: serial@20060000 {
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compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
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reg = <0x20060000 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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@@ -269,7 +254,7 @@
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#dma-cells = <2>;
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};
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- uart1: serial1@20064000 {
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+ uart1: serial@20064000 {
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compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
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reg = <0x20064000 0x100>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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@@ -284,7 +269,7 @@
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#dma-cells = <2>;
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};
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- uart2: serial2@20068000 {
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+ uart2: serial@20068000 {
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compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
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reg = <0x20068000 0x100>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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@@ -311,44 +296,40 @@
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status = "disabled";
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};
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- pwm0: pwm0@20050000 {
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+ pwm0: pwm@20050000 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050000 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&cru PCLK_PWM>;
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- clock-names = "pwm";
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};
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- pwm1: pwm1@20050010 {
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+ pwm1: pwm@20050010 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050010 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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clocks = <&cru PCLK_PWM>;
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- clock-names = "pwm";
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};
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- pwm2: pwm2@20050020 {
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+ pwm2: pwm@20050020 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050020 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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clocks = <&cru PCLK_PWM>;
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- clock-names = "pwm";
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};
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- pwm3: pwm3@20050030 {
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+ pwm3: pwm@20050030 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050030 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
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clocks = <&cru PCLK_PWM>;
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- clock-names = "pwm";
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};
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sram: sram@10080400 {
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@@ -377,7 +358,7 @@
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interrupts = <GIC_PPI 9 0xf04>;
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};
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- u2phy: usb2-phy {
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+ u2phy: usb2phy {
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compatible = "rockchip,rk3128-usb2phy";
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reg = <0x017c 0x0c>;
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rockchip,grf = <&grf>;
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@@ -385,7 +366,6 @@
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clock-names = "phyclk";
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#clock-cells = <0>;
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clock-output-names = "usb480m_phy";
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- #phy-cells = <1>;
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status = "disabled";
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u2phy_otg: otg-port {
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@@ -407,15 +387,14 @@
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};
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usb_otg: usb@10180000 {
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- compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
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- "snps,dwc2";
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+ compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
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reg = <0x10180000 0x40000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_OTG>;
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+ clock-names = "otg";
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dr_mode = "otg";
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- g-use-dma;
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- hnp-srp-disable;
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- phys = <&u2phy 0>;
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- phy-names = "usb";
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+ phys = <&u2phy_otg>;
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+ phy-names = "usb2-phy";
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status = "disabled";
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};
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@@ -423,7 +402,7 @@
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compatible = "generic-ehci";
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reg = <0x101c0000 0x20000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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- phys = <&u2phy 1>;
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+ phys = <&u2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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@@ -432,19 +411,19 @@
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compatible = "generic-ohci";
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reg = <0x101e0000 0x20000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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- phys = <&u2phy 1>;
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+ phys = <&u2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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- sdmmc: dwmmc@10214000 {
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- compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
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+ sdmmc: mmc@10214000 {
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+ compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x10214000 0x4000>;
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max-frequency = <150000000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
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@@ -452,15 +431,14 @@
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status = "disabled";
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};
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- emmc: dwmmc@1021c000 {
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- u-boot,dm-pre-reloc;
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+ emmc: mmc@1021c000 {
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compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x1021c000 0x4000>;
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max-frequency = <150000000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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bus-width = <8>;
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default-sample-phase = <158>;
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num-slots = <1>;
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@@ -472,7 +450,7 @@
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status = "disabled";
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};
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- i2c0: i2c0@20072000 {
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+ i2c0: i2c@20072000 {
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compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
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reg = <20072000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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@@ -484,7 +462,7 @@
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pinctrl-0 = <&i2c0_xfer>;
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};
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- i2c1: i2c1@20056000 {
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+ i2c1: i2c@20056000 {
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compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
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reg = <0x20056000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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@@ -496,7 +474,7 @@
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pinctrl-0 = <&i2c1_xfer>;
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};
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- i2c2: i2c2@2005a000 {
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+ i2c2: i2c@2005a000 {
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compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
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reg = <0x2005a000 0x1000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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@@ -508,7 +486,7 @@
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pinctrl-0 = <&i2c2_xfer>;
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};
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- i2c3: i2c3@2005e000 {
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+ i2c3: i2c@2005e000 {
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compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
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reg = <0x2005e000 0x1000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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@@ -521,7 +499,7 @@
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};
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spi0: spi@20074000 {
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- compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
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+ compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
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reg = <0x20074000 0x1000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@@ -530,15 +508,14 @@
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pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
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rockchip,spi-src-clk = <0>;
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num-cs = <2>;
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- clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>;
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- clock-names = "spi","pclk_spi0";
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+ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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+ clock-names = "spiclk", "apb_pclk";
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dmas = <&pdma 8>, <&pdma 9>;
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#dma-cells = <2>;
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dma-names = "tx", "rx";
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};
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grf: syscon@20008000 {
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- u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3128-grf", "syscon";
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reg = <0x20008000 0x1000>;
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};
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@@ -555,7 +532,7 @@
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#size-cells = <1>;
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ranges;
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- gpio0: gpio0@2007c000 {
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+ gpio0: gpio@2007c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2007c000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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@@ -566,7 +543,7 @@
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#interrupt-cells = <2>;
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};
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- gpio1: gpio1@20080000 {
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+ gpio1: gpio@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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@@ -577,7 +554,7 @@
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#interrupt-cells = <2>;
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};
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- gpio2: gpio2@20084000 {
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+ gpio2: gpio@20084000 {
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compatible = "rockchip,gpio-bank";
|
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|
reg = <0x20084000 0x100>;
|
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|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -588,7 +565,7 @@
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#interrupt-cells = <2>;
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|
};
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|
|
|
- gpio3: gpio2@20088000 {
|
|
|
+ gpio3: gpio@20088000 {
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|
|
compatible = "rockchip,gpio-bank";
|
|
|
reg = <0x20088000 0x100>;
|
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|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -618,85 +595,85 @@
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|
*/
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|
|
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|
|
emmc_clk: emmc-clk {
|
|
|
- rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
|
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
emmc_pwren: emmc-pwren {
|
|
|
- rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
|
- rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
|
|
|
- <1 25 RK_FUNC_2 &pcfg_pull_none>,
|
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|
- <1 26 RK_FUNC_2 &pcfg_pull_none>,
|
|
|
- <1 27 RK_FUNC_2 &pcfg_pull_none>,
|
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|
- <1 28 RK_FUNC_2 &pcfg_pull_none>,
|
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|
- <1 29 RK_FUNC_2 &pcfg_pull_none>,
|
|
|
- <1 30 RK_FUNC_2 &pcfg_pull_none>,
|
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|
- <1 31 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
|
|
|
+ <1 RK_PD1 2 &pcfg_pull_none>,
|
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|
+ <1 RK_PD2 2 &pcfg_pull_none>,
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|
|
+ <1 RK_PD3 2 &pcfg_pull_none>,
|
|
|
+ <1 RK_PD4 2 &pcfg_pull_none>,
|
|
|
+ <1 RK_PD5 2 &pcfg_pull_none>,
|
|
|
+ <1 RK_PD6 2 &pcfg_pull_none>,
|
|
|
+ <1 RK_PD7 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
nandc{
|
|
|
nandc_ale:nandc-ale {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
nandc_cle:nandc-cle {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
nandc_wrn:nandc-wrn {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
nandc_rdn:nandc-rdn {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
nandc_rdy:nandc-rdy {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
nandc_cs0:nandc-cs0 {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
nandc_data: nandc-data {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
uart0 {
|
|
|
uart0_xfer: uart0-xfer {
|
|
|
- rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
|
- <0 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,
|
|
|
+ <0 RK_PC1 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
uart0_cts: uart0-cts {
|
|
|
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
uart0_rts: uart0-rts {
|
|
|
- rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
uart1 {
|
|
|
uart1_xfer: uart1-xfer {
|
|
|
- rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
|
|
|
- <2 23 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,
|
|
|
+ <2 RK_PC7 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
uart2 {
|
|
|
uart2_xfer: uart2-xfer {
|
|
|
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
|
|
|
- <1 19 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,
|
|
|
+ <1 RK_PC3 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
@@ -727,75 +704,75 @@
|
|
|
|
|
|
pwm0 {
|
|
|
pwm0_pin: pwm0-pin {
|
|
|
- rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
pwm1 {
|
|
|
pwm1_pin: pwm1-pin {
|
|
|
- rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
pwm2 {
|
|
|
pwm2_pin: pwm2-pin {
|
|
|
- rockchip,pins = <0 1 2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
pwm3 {
|
|
|
pwm3_pin: pwm3-pin {
|
|
|
- rockchip,pins = <0 27 1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
i2c0 {
|
|
|
i2c0_xfer: i2c0-xfer {
|
|
|
- rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
|
|
|
- <0 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
|
|
|
+ <0 RK_PA1 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
i2c1 {
|
|
|
i2c1_xfer: i2c1-xfer {
|
|
|
- rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
|
|
|
- <0 3 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
|
|
|
+ <0 RK_PA3 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
i2c2 {
|
|
|
i2c2_xfer: i2c2-xfer {
|
|
|
- rockchip,pins = <2 20 3 &pcfg_pull_none>,
|
|
|
- <2 21 3 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
|
|
|
+ <2 RK_PC5 3 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
i2c3 {
|
|
|
i2c3_xfer: i2c3-xfer {
|
|
|
- rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
|
|
|
- <0 7 RK_FUNC_1 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
|
|
|
+ <0 RK_PA7 1 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
spi0 {
|
|
|
spi0_txd_mux0:spi0-txd-mux0 {
|
|
|
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
spi0_rxd_mux0:spi0-rxd-mux0 {
|
|
|
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
spi0_clk_mux0:spi0-clk-mux0 {
|
|
|
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
spi0_cs0_mux0:spi0-cs0-mux0 {
|
|
|
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
|
|
|
spi0_cs1_mux0:spi0-cs1-mux0 {
|
|
|
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
|
|
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
|
|
|
};
|
|
|
};
|
|
|
|