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@@ -0,0 +1,136 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
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+ */
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+
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+#include <common.h>
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+#include <asm/arch/clock_manager.h>
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+#include <asm/global_data.h>
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+#include <asm/io.h>
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+#include "clk-mem-n5x.h"
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+#include <clk-uclass.h>
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+#include <dm.h>
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+#include <dm/lists.h>
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+#include <dm/util.h>
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+#include <dt-bindings/clock/n5x-clock.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+struct socfpga_mem_clk_plat {
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+ void __iomem *regs;
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+};
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+
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+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
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+{
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+ u32 inter_val;
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+ u32 retry = 0;
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+
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+ do {
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+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
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+
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+ /* Wait for stable lock */
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+ if (inter_val == mask)
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+ retry++;
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+ else
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+ retry = 0;
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+
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+ if (retry >= 10)
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+ return;
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+ } while (1);
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+}
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+
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+/*
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+ * function to write the bypass register which requires a poll of the
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+ * busy bit
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+ */
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+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
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+{
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+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
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+}
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+
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+/*
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+ * Setup clocks while making no assumptions about previous state of the clocks.
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+ */
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+static void clk_mem_basic_init(struct udevice *dev,
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+ const struct cm_config * const cfg)
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+{
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+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
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+
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+ if (!cfg)
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+ return;
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+
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+ /* Put PLLs in bypass */
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+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
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+
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+ /* Put PLLs in Reset */
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+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
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+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
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+
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+ /* setup mem PLL */
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+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
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+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
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+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
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+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
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+
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+ /* Take PLL out of reset and power up */
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+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
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+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
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+}
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+
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+static int socfpga_mem_clk_enable(struct clk *clk)
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+{
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+ const struct cm_config *cm_default_cfg = cm_get_default_config();
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+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
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+
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+ clk_mem_basic_init(clk->dev, cm_default_cfg);
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+
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+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
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+
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+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
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+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
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+ MEMCLKMGR_MEMPLL_PLLGLOB);
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+
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+ /* Take all PLLs out of bypass */
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+ clk_mem_write_bypass_mempll(plat, 0);
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+
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+ /* Clear the loss of lock bits (write 1 to clear) */
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+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
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+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
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+
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+ /* Take all ping pong counters out of reset */
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+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
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+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
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+
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+ return 0;
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+}
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+
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+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
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+{
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+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
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+ fdt_addr_t addr;
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+
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+ addr = devfdt_get_addr(dev);
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+ if (addr == FDT_ADDR_T_NONE)
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+ return -EINVAL;
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+ plat->regs = (void __iomem *)addr;
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+
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+ return 0;
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+}
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+
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+static struct clk_ops socfpga_mem_clk_ops = {
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+ .enable = socfpga_mem_clk_enable
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+};
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+
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+static const struct udevice_id socfpga_mem_clk_match[] = {
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+ { .compatible = "intel,n5x-mem-clkmgr" },
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+ {}
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+};
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+
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+U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
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+ .name = "mem-clk-n5x",
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+ .id = UCLASS_CLK,
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+ .of_match = socfpga_mem_clk_match,
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+ .ops = &socfpga_mem_clk_ops,
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+ .of_to_plat = socfpga_mem_clk_of_to_plat,
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+ .plat_auto = sizeof(struct socfpga_mem_clk_plat),
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+};
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