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spl: amp: Enable UART2 and move rtos image to memory

Enable UART2 for rtos and move rtos image to running memory.
The image size is 832KB.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Minda Chen 1 month ago
parent
commit
1444304dac
2 changed files with 37 additions and 0 deletions
  1. 3 0
      arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
  2. 34 0
      board/starfive/visionfive2/spl.c

+ 3 - 0
arch/riscv/include/asm/arch-jh7110/jh7110-regs.h

@@ -114,5 +114,8 @@
 #define CLK_QSPI_REF_SW_SHIFT	24
 #define CLK_QSPI_REF_SW_MASK	0x1000000U
 
+#define CLK_UART2_APB_OFFSET   0x254
+#define CLK_UART2_CORE_OFFSET  0x258
+#define CLK_RSTN_3_OFFSET      0x300
 #endif /* __STARFIVE_JH7110_REGS_H */
 

+ 34 - 0
board/starfive/visionfive2/spl.c

@@ -18,6 +18,8 @@
 
 #define MODE_SELECT_REG		0x1702002c
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int spl_board_init_f(void)
 {
 	int ret;
@@ -186,4 +188,36 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+static void spl_enable_uart2(void)
+{
+	/* uart2 clock */
+	setbits_le32(SYS_CRG_BASE + CLK_UART2_APB_OFFSET, BIT(31));
+	setbits_le32(SYS_CRG_BASE + CLK_UART2_CORE_OFFSET, BIT(31));
+	clrsetbits_le32(SYS_CRG_BASE + CLK_RSTN_3_OFFSET, BIT(23) | BIT(24), 0);
+
+	/*uart2 tx*/
+	SYS_IOMUX_DOEN(43, LOW);
+	SYS_IOMUX_DOUT(43, 0x4f);
+	SYS_IOMUX_SET_DS(43, 3);
+	/*uart2 rx*/
+	SYS_IOMUX_DOEN(42, HIGH);
+	SYS_IOMUX_DIN(42, 62);
+}
 
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	unsigned long rtos_offset, rtos_image_addr;
+	unsigned long rtos_base;
+
+	rtos_base = fdtdec_get_config_int(gd->fdt_blob,
+					  "amp,rtos-code-base", 0);
+	rtos_offset = fdtdec_get_config_int(gd->fdt_blob,
+					    "amp,rtos-offset", 0);
+
+	if (rtos_base && rtos_offset) {
+		spl_enable_uart2();
+		rtos_image_addr = CONFIG_SPL_OPENSBI_LOAD_ADDR + rtos_offset;
+		memcpy((void *)rtos_base, (void *)(rtos_image_addr),
+		       spl_image->size - rtos_offset);
+	}
+}