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@@ -18,6 +18,8 @@
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#define MODE_SELECT_REG 0x1702002c
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+DECLARE_GLOBAL_DATA_PTR;
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+
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int spl_board_init_f(void)
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{
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int ret;
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@@ -186,4 +188,36 @@ int board_fit_config_name_match(const char *name)
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}
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#endif
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+static void spl_enable_uart2(void)
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+{
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+ /* uart2 clock */
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+ setbits_le32(SYS_CRG_BASE + CLK_UART2_APB_OFFSET, BIT(31));
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+ setbits_le32(SYS_CRG_BASE + CLK_UART2_CORE_OFFSET, BIT(31));
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+ clrsetbits_le32(SYS_CRG_BASE + CLK_RSTN_3_OFFSET, BIT(23) | BIT(24), 0);
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+
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+ /*uart2 tx*/
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+ SYS_IOMUX_DOEN(43, LOW);
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+ SYS_IOMUX_DOUT(43, 0x4f);
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+ SYS_IOMUX_SET_DS(43, 3);
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+ /*uart2 rx*/
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+ SYS_IOMUX_DOEN(42, HIGH);
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+ SYS_IOMUX_DIN(42, 62);
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+}
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+void spl_perform_fixups(struct spl_image_info *spl_image)
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+{
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+ unsigned long rtos_offset, rtos_image_addr;
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+ unsigned long rtos_base;
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+
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+ rtos_base = fdtdec_get_config_int(gd->fdt_blob,
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+ "amp,rtos-code-base", 0);
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+ rtos_offset = fdtdec_get_config_int(gd->fdt_blob,
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+ "amp,rtos-offset", 0);
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+
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+ if (rtos_base && rtos_offset) {
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+ spl_enable_uart2();
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+ rtos_image_addr = CONFIG_SPL_OPENSBI_LOAD_ADDR + rtos_offset;
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+ memcpy((void *)rtos_base, (void *)(rtos_image_addr),
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+ spl_image->size - rtos_offset);
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+ }
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+}
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