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@@ -3,8 +3,6 @@
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Openpiton RISC-V SoC
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====================
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-OpenPiton RISC-V SoC
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---------------------
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OpenPiton is an open source, manycore processor and research platform. It is a
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tiled manycore framework scalable from one to 1/2 billion cores. It supports a
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number of ISAs including RISC-V with its P-Mesh cache coherence protocol and
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@@ -14,21 +12,23 @@ running full-stack Debian linux.
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RISC-V Standard Bootflow
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-------------------------
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+
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Currently, OpenPiton implements RISC-V standard bootflow in the following steps
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mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
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This board supports S-mode u-boot as well as M-mode SPL
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Building OpenPition
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---------------------
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+
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If you'd like to build OpenPiton, please go to OpenPiton github repo
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(at https://github.com/PrincetonUniversity/openpiton) to build from the latest
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changes
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Building Images
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----------------------------
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+---------------
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SPL
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----
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+~~~
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1. Add the RISC-V toolchain to your PATH.
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2. Setup ARCH & cross compilation environment variable:
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@@ -42,7 +42,7 @@ SPL
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4. make
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U-Boot
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-------
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+~~~~~~
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1. Add the RISC-V toolchain to your PATH.
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2. Setup ARCH & cross compilation environment variable:
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@@ -55,9 +55,8 @@ U-Boot
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3. make openpiton_riscv64_defconfig
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4. make
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-
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opensbi
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--------
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+~~~~~~~
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1. Add the RISC-V toolchain to your PATH.
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2. Setup ARCH & cross compilation environment variable:
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@@ -70,9 +69,9 @@ opensbi
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3. Go to OpenSBI directory
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4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin>
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+Using fw_payload.bin with Linux
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+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-Using fw_payload.bin with linux
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--------------------------------
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Put the generated fw_payload.bin into the /boot directory on the root filesystem,
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plug in the SD card, then flash the bitstream. Linux will boot automatically.
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@@ -81,7 +80,7 @@ Booting
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Once you plugin the sdcard and power up, you should see the U-Boot prompt.
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Sample Dual-core Debian boot log from OpenPiton
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------------------------------------------------
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+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. code-block:: none
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