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@@ -0,0 +1,49 @@
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+Armada-8K PCIe DT details:
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+==========================
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+
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+Armada-8k uses synopsis designware PCIe controller.
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+
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+Required properties:
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+- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
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+- reg: base addresses and lengths of the pcie control and global control registers.
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+ "ctrl" registers points to the global control registers, while the "config" space
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+ points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
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+- interrupt-map-mask and interrupt-map, standard PCI properties to
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+ define the mapping of the PCIe interface to interrupt numbers.
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+- All other definitions as per generic PCI bindings
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+See Linux kernel documentation:
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+"Documentation/devicetree/bindings/pci/designware-pcie.txt"
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+
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+Optional properties:
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+PHY support is still not supported for armada-8k, once it will, the following parameters can be used:
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+- phys : phandle to phy node associated with pcie controller.
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+- phy-names : must be "pcie-phy"
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+- marvell,reset-gpio : specifies a gpio that needs to be activated for plug-in
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+ card reset signal release.
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+Example:
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+
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+cpm_pcie0: pcie@f2600000 {
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+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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+ reg = <0 0xf2600000 0 0x10000>,
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+ <0 0xf6f00000 0 0x80000>;
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+ reg-names = "ctrl", "config";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ device_type = "pci";
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+ dma-coherent;
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+
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+ bus-range = <0 0xff>;
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+ ranges =
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+ /* downstream I/O */
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+ <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
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+ /* non-prefetchable memory */
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+ 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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+ num-lanes = <1>;
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+ clocks = <&cpm_syscon0 1 13>;
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+ marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>;
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+ status = "disabled";
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+};
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