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@@ -482,6 +482,16 @@ static struct clk_root_map root_array[] = {
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SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
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SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
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},
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+ {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
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+ {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
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+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
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+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
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+ },
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+ {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
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+ {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
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+ SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
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+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
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+ },
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{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
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{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
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SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
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@@ -509,6 +519,21 @@ static struct clk_root_map root_array[] = {
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SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
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SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
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},
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+ {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
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+ {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
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+ SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
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+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
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+ },
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+ {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
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+ {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
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+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
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+ VIDEO_PLL_CLK}
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+ },
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+ {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
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+ {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
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+ SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
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+ AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
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+ },
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{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
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{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
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SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
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