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@@ -10,6 +10,7 @@
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#include <pci.h>
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#include <asm/addrspace.h>
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+#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/malta.h>
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#include <asm/mipsregs.h>
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@@ -34,7 +35,7 @@ lowlevel_init:
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mtc0 t0, CP0_CONFIG, 2
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/* detect the core card */
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- li t0, KSEG1ADDR(MALTA_REVISION)
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+ PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
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lw t0, 0(t0)
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srl t0, t0, MALTA_REVISION_CORID_SHF
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andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
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@@ -68,12 +69,12 @@ lowlevel_init:
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*/
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_gt64120:
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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- li t1, KSEG1ADDR(GT_DEF_BASE)
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+ PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
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li t0, CPU_TO_GT32(0xdf000000)
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sw t0, GT_ISD_OFS(t1)
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/* setup MEM-to-PCI0 mapping */
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- li t1, KSEG1ADDR(MALTA_GT_BASE)
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+ PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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li t0, CPU_TO_GT32(0xc0000000)
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@@ -100,7 +101,7 @@ _gt64120:
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*/
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_msc01:
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/* setup peripheral bus controller clock divide */
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- li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
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+ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
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li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
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sw t1, MSC01_PBC_CLKCFG_OFS(t0)
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@@ -122,7 +123,7 @@ _msc01:
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sw t1, MSC01_PBC_CS0CFG_OFS(t0)
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/* setup basic address decode */
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- li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
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+ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
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li t1, 0x0
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li t2, -CONFIG_SYS_MEM_SIZE
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sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
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@@ -157,7 +158,7 @@ _msc01:
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sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
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/* setup PCI memory */
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- li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
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+ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
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li t1, MALTA_MSC01_PCIMEM_BASE
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li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
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li t3, MALTA_MSC01_PCIMEM_MAP
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