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@@ -9,11 +9,13 @@
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#define __STARFIVE_JH7110_REGS_H
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/*system control register*/
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-#define STG_SYSCON_BASE 0x10240000
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-#define SYS_SYSCON_BASE 0x13030000
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-#define SYS_IOMUX_BASE 0x13040000
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-#define AON_SYSCON_BASE 0x17010000
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-#define SYS_CRG_BASE 0x13020000
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+#define STG_SYSCON_BASE 0x10240000
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+#define SYS_SYSCON_BASE 0x13030000
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+#define SYS_IOMUX_BASE 0x13040000
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+#define AON_SYSCON_BASE 0x17010000
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+#define SYS_CRG_BASE 0x13020000
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+#define AON_CRG_BASE 0x17000000
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+#define STG_CRG_BASE 0x10230000
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#define CLK_ENABLE_MASK 0x80000000U
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#define SYS_CRG_RESET_ASSERT3_SHIFT 0X304U
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#define SYS_CRG_RESET_STATUS3_SHIFT 0X314U
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@@ -57,5 +59,25 @@
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#define TIMER_RSTN_TIMER2_SHIFT 24
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#define TIMER_RSTN_TIMER3_SHIFT 25
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+#define CLK_CPU_ROOT_OFFSET 0x0
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+#define CLK_CPU_ROOT_SW_SHIFT 24
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+#define CLK_CPU_ROOT_SW_MASK 0x1000000U
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+
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+#define CLK_BUS_ROOT_OFFSET 0x14
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+#define CLK_BUS_ROOT_SW_SHIFT 24
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+#define CLK_BUS_ROOT_SW_MASK 0x1000000U
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+
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+#define CLK_NOC_BUS_STG_AXI_OFFSET 0x180
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+#define CLK_NOC_BUS_STG_AXI_EN_SHIFT 31
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+#define CLK_NOC_BUS_STG_AXI_EN_MASK 0x80000000U
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+
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+#define CLK_AON_APB_FUNC_OFFSET 0x4
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+#define CLK_AON_APB_FUNC_SW_SHIFT 24
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+#define CLK_AON_APB_FUNC_SW_MASK 0x1000000U
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+
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+#define CLK_QSPI_REF_OFFSET 0x168
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+#define CLK_QSPI_REF_SW_SHIFT 24
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+#define CLK_QSPI_REF_SW_MASK 0x1000000U
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+
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#endif /* __STARFIVE_JH7110_REGS_H */
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