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+SiFive PWM controller
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+
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+Unlike most other PWM controllers, the SiFive PWM controller currently only
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+supports one period for all channels in the PWM. All PWMs need to run at
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+the same period. The period also has significant restrictions on the values
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+it can achieve, which the driver rounds to the nearest achievable period.
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+PWM RTL that corresponds to the IP block version numbers can be found
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+here:
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+
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+https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
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+
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+Required properties:
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+- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
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+ Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
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+ PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
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+ SiFive PWM v0 IP block with no chip integration tweaks.
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+- reg: physical base address and length of the controller's registers
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+- clocks: Should contain a clock identifier for the PWM's parent clock.
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+- #pwm-cells: Should be 3.
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+- interrupts: one interrupt per PWM channel
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+
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+Examples:
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+
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+pwm: pwm@10020000 {
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+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
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+ reg = <0x0 0x10020000 0x0 0x1000>;
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+ clocks = <&tlclk>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <42 43 44 45>;
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+ #pwm-cells = <3>;
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+};
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