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@@ -21,7 +21,33 @@ DECLARE_GLOBAL_DATA_PTR;
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#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
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#define RFU_SW_RESET_OFFSET 0
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+/*
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+ * The following table includes all memory regions for Armada 7k and
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+ * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
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+ * define these regions at the beginning of the struct so that they
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+ * can be easier removed later dynamically if an Armada 7k device is detected.
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+ * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
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+ */
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+#define ARMADA_7K8K_COMMON_REGIONS_START 2
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static struct mm_region mvebu_mem_map[] = {
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+ /* Armada 80x0 memory regions include the CP1 (slave) units */
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+ {
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+ /* SRAM, MMIO regions - CP110 slave region */
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+ .phys = 0xf4000000UL,
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+ .virt = 0xf4000000UL,
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+ .size = 0x02000000UL, /* 32MiB internal registers */
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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+ PTE_BLOCK_NON_SHARE
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+ },
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+ {
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+ /* PCI CP1 regions */
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+ .phys = 0xfa000000UL,
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+ .virt = 0xfa000000UL,
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+ .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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+ PTE_BLOCK_NON_SHARE
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+ },
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+ /* Armada 80x0 and 70x0 common memory regions start here */
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{
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/* RAM */
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.phys = 0x0UL,
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@@ -47,29 +73,35 @@ static struct mm_region mvebu_mem_map[] = {
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PTE_BLOCK_NON_SHARE
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},
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{
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- /* SRAM, MMIO regions - CP110 slave region */
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- .phys = 0xf4000000UL,
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- .virt = 0xf4000000UL,
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- .size = 0x02000000UL, /* 32MiB internal registers */
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+ /* PCI CP0 regions */
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+ .phys = 0xf6000000UL,
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+ .virt = 0xf6000000UL,
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+ .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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- /* PCI regions */
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- .phys = 0xf8000000UL,
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- .virt = 0xf8000000UL,
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- .size = 0x08000000UL, /* 128MiB PCI space (master & slave) */
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- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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- PTE_BLOCK_NON_SHARE
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- },
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- {
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- /* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = mvebu_mem_map;
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+void enable_caches(void)
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+{
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+ /*
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+ * Armada 7k is not equipped with the CP110 slave CP. In case this
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+ * code runs on an Armada 7k device, lets remove the CP110 slave
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+ * entries from the memory mapping by moving the start to the
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+ * common regions.
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+ */
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+ if (of_machine_is_compatible("marvell,armada7040"))
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+ mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
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+
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+ icache_enable();
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+ dcache_enable();
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+}
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+
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void reset_cpu(ulong ignored)
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{
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u32 reg;
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