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clk:starfive-jh7110: Update pll0/pll1/pll2 clk

Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to  clk-jh7110.c

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
yanhong.wang 2 роки тому
батько
коміт
0b2572d997
2 змінених файлів з 4 додано та 24 видалено
  1. 0 18
      arch/riscv/dts/jh7110_clk.dtsi
  2. 4 6
      drivers/clk/starfive/clk-jh7110.c

+ 0 - 18
arch/riscv/dts/jh7110_clk.dtsi

@@ -113,22 +113,4 @@
 		clock-frequency = <297000000>;
 	};
 	/* external clocks end */
-
-	pll0_out: pll0_out {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1250000000>;
-	};
-
-	pll1_out: pll1_out {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1066000000>;
-	};
-
-	pll2_out: pll2_out {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1228800000>;
-	};
 };

+ 4 - 6
drivers/clk/starfive/clk-jh7110.c

@@ -303,17 +303,16 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg,
 static int jh7110_clk_init(struct udevice *dev)
 {
 	struct jh7110_clk_priv *priv = dev_get_priv(dev);
-#if 0
+
 	clk_dm(JH7110_PLL0_OUT,
 		starfive_clk_fix_factor(priv->sys,
-			"pll0_out", "osc", 52, 1));
+			"pll0_out", "osc", 1250, 24));
 	clk_dm(JH7110_PLL1_OUT,
 		starfive_clk_fix_factor(priv->sys,
-			"pll1_out", "osc", 44, 1));
+			"pll1_out", "osc", 1066, 24));
 	clk_dm(JH7110_PLL2_OUT,
 		starfive_clk_fix_factor(priv->sys,
-			"pll2_out", "osc", 51, 1));
-#endif
+			"pll2_out", "osc", 12288, 240));
 	/*root*/
 	clk_dm(JH7110_CPU_ROOT,
 		starfive_clk_mux(priv->sys, "cpu_root",
@@ -643,6 +642,5 @@ U_BOOT_DRIVER(jh7110_clk) = {
 	.probe = jh7110_clk_probe,
 	.ops = &starfive_clk_ops,
 	.priv_auto = sizeof(struct jh7110_clk_priv),
-	.flags = DM_FLAG_PRE_RELOC,
 };