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@@ -40,6 +40,7 @@
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#define YTPHY_SPEED_MODE 0xc000
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#define YTPHY_SPEED_MODE_BIT 14
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#define YTPHY_RGMII_SW_DR_MASK GENMASK(5, 4)
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+#define YTPHY_RGMII_RXC_DR_MASK GENMASK(15, 13)
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#define YT8521_EXT_CLK_GATE 0xc
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#define YT8521_EN_SLEEP_SW_BIT 15
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@@ -73,6 +74,12 @@ struct ytphy_reg_field {
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const u8 dflt; /* Default value */
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};
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+static const struct ytphy_reg_field ytphy_dr_grp[] = {
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+ { "rgmii_sw_dr", 2, 4, 0x3},
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+ { "rgmii_sw_dr_2", 1, 12, 0x0},
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+ { "rgmii_sw_dr_rxc", 3, 13, 0x3}
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+};
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+
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static const struct ytphy_reg_field ytphy_rxtxd_grp[] = {
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{ "rx_delay_sel", 4, 10, 0x0 },
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{ "tx_delay_sel_fe", 4, 4, 0xf },
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@@ -228,9 +235,20 @@ static int ytphy_of_config(struct phy_device *phydev)
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ytphy_write_ext(phydev, YTPHY_EXTREG_CHIP_CONFIG, val);
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}
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- /* set drive strenght of rxd/rx_ctl rgmii pad */
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val = ytphy_read_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG);
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- val |= YTPHY_RGMII_SW_DR_MASK;
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+ for (i = 0; i < ARRAY_SIZE(ytphy_dr_grp); i++) {
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+
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+ cfg = ofnode_read_u32_default(node,
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+ ytphy_dr_grp[i].name, ~0);
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+ cfg = (cfg != -1) ? cfg : ytphy_dr_grp[i].dflt;
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+
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+ /*check the cfg overflow or not*/
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+ cfg = (cfg > ((1 << ytphy_dr_grp[i].size) - 1)) ?
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+ ((1 << ytphy_dr_grp[i].size) - 1) : cfg;
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+
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+ val = bitfield_replace(val, ytphy_dr_grp[i].off,
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+ ytphy_dr_grp[i].size, cfg);
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+ }
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ytphy_write_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG, val);
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val = ytphy_read_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1);
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