|
@@ -164,6 +164,52 @@
|
|
|
#clock-cells = <1>;
|
|
|
ranges;
|
|
|
|
|
|
+ pmu {
|
|
|
+ compatible = "riscv,pmu";
|
|
|
+ riscv,event-to-mhpmcounters = <0x5 0x06 0x18
|
|
|
+ 0x08 0x09 0x18>;
|
|
|
+ riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000
|
|
|
+ 0x06 0x00000000 0x4001
|
|
|
+ 0x08 0x00000000 0x4008
|
|
|
+ 0x09 0x00000000 0x4009>;
|
|
|
+ riscv,raw-event-to-mhpmcounters =
|
|
|
+ <0x00000000 0x100 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x200 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x400 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x800 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x1000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x2000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x4000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x8000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x10000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x20000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x40000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x80000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x100000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x200000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x400000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x800000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x1000000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x2000000 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x101 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x201 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x401 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x801 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x1001 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x2001 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x4001 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x8001 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x10001 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x20001 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x40001 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x102 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x202 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x402 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x802 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x1002 0xffffffff 0xffffffff 0x18
|
|
|
+ 0x00000000 0x2002 0xffffffff 0xffffffff 0x18>;
|
|
|
+ };
|
|
|
+
|
|
|
cachectrl: cache-controller@2010000 {
|
|
|
compatible = "sifive,fu740-c000-ccache", "cache";
|
|
|
reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
|