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@@ -250,7 +250,7 @@ DECLARE_GLOBAL_DATA_PTR;
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enum stm32mp1_parent_id {
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/*
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* _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
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- * they are used as index in osc[] as entry point
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+ * they are used as index in osc_clk[] as clock reference
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*/
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_HSI,
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_HSE,
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@@ -430,8 +430,7 @@ struct stm32mp1_clk_data {
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struct stm32mp1_clk_priv {
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fdt_addr_t base;
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const struct stm32mp1_clk_data *data;
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- ulong osc[NB_OSC];
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- struct udevice *osc_dev[NB_OSC];
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+ struct clk osc_clk[NB_OSC];
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};
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#define STM32MP1_CLK(off, b, idx, s) \
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@@ -790,7 +789,7 @@ static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
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return 0;
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}
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- return priv->osc[idx];
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+ return clk_get_rate(&priv->osc_clk[idx]);
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}
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static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
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@@ -1545,7 +1544,7 @@ static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
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break;
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if (hsidiv == 4) {
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- log_err("clk-hsi frequency invalid");
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+ log_err("hsi frequency invalid");
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return -1;
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}
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@@ -1952,13 +1951,13 @@ static int stm32mp1_clktree(struct udevice *dev)
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* switch ON oscillator found in device-tree,
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* HSI already ON after bootrom
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*/
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- if (priv->osc[_LSI])
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+ if (clk_valid(&priv->osc_clk[_LSI]))
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stm32mp1_lsi_set(rcc, 1);
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- if (priv->osc[_LSE]) {
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+ if (clk_valid(&priv->osc_clk[_LSE])) {
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int bypass, digbyp;
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u32 lsedrv;
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- struct udevice *dev = priv->osc_dev[_LSE];
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+ struct udevice *dev = priv->osc_clk[_LSE].dev;
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bypass = dev_read_bool(dev, "st,bypass");
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digbyp = dev_read_bool(dev, "st,digbypass");
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@@ -1969,9 +1968,9 @@ static int stm32mp1_clktree(struct udevice *dev)
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stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
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}
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- if (priv->osc[_HSE]) {
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+ if (clk_valid(&priv->osc_clk[_HSE])) {
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int bypass, digbyp, css;
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- struct udevice *dev = priv->osc_dev[_HSE];
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+ struct udevice *dev = priv->osc_clk[_HSE].dev;
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bypass = dev_read_bool(dev, "st,bypass");
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digbyp = dev_read_bool(dev, "st,digbypass");
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@@ -1996,8 +1995,8 @@ static int stm32mp1_clktree(struct udevice *dev)
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/* configure HSIDIV */
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dev_dbg(dev, "configure HSIDIV\n");
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- if (priv->osc[_HSI]) {
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- stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
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+ if (clk_valid(&priv->osc_clk[_HSI])) {
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+ stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI]));
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stgen_config(priv);
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}
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@@ -2043,7 +2042,7 @@ static int stm32mp1_clktree(struct udevice *dev)
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}
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/* wait LSE ready before to use it */
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- if (priv->osc[_LSE])
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+ if (clk_valid(&priv->osc_clk[_LSE]))
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stm32mp1_lse_wait(rcc);
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/* configure with expected clock source */
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@@ -2082,7 +2081,7 @@ static int stm32mp1_clktree(struct udevice *dev)
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dev_dbg(dev, "oscillator off\n");
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/* switch OFF HSI if not found in device-tree */
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- if (!priv->osc[_HSI])
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+ if (!clk_valid(&priv->osc_clk[_HSI]))
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stm32mp1_hsi_set(rcc, 0);
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/* Software Self-Refresh mode (SSR) during DDR initilialization */
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@@ -2178,40 +2177,25 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
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return -EINVAL;
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}
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-static void stm32mp1_osc_clk_init(const char *name,
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- struct stm32mp1_clk_priv *priv,
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- int index)
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-{
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- struct clk clk;
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- struct udevice *dev = NULL;
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-
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- priv->osc[index] = 0;
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- clk.id = 0;
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- if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
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- if (clk_request(dev, &clk))
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- log_err("%s request", name);
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- else
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- priv->osc[index] = clk_get_rate(&clk);
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- }
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- priv->osc_dev[index] = dev;
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-}
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-
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static void stm32mp1_osc_init(struct udevice *dev)
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{
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struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
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int i;
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const char *name[NB_OSC] = {
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- [_LSI] = "clk-lsi",
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- [_LSE] = "clk-lse",
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- [_HSI] = "clk-hsi",
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- [_HSE] = "clk-hse",
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- [_CSI] = "clk-csi",
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+ [_LSI] = "lsi",
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+ [_LSE] = "lse",
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+ [_HSI] = "hsi",
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+ [_HSE] = "hse",
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+ [_CSI] = "csi",
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[_I2S_CKIN] = "i2s_ckin",
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};
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for (i = 0; i < NB_OSC; i++) {
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- stm32mp1_osc_clk_init(name[i], priv, i);
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- dev_dbg(dev, "%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
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+ if (clk_get_by_name(dev, name[i], &priv->osc_clk[i]))
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+ dev_dbg(dev, "No source clock \"%s\"", name[i]);
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+ else
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+ dev_dbg(dev, "%s clock rate: %luHz\n",
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+ name[i], clk_get_rate(&priv->osc_clk[i]));
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}
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}
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