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@@ -7,10 +7,32 @@
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#define __IMX6_SPL_CONFIG_H
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#ifdef CONFIG_SPL
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+
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+#ifdef CONFIG_MX6_OCRAM_256KB
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/*
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- * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:
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+ * see Figure 8.4.1 in IMX6DQ Reference manuals:
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+ * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
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+ * - BOOT ROM stack is at 0x0093FFB8
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+ * - if icache/dcache is enabled (eFuse/strapping controlled) then the
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+ * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to
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+ * fit between 0x00907000 and 0x00938000.
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+ * - Additionally the BOOT ROM loads what they consider the firmware image
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+ * which consists of a 4K header in front of us that contains the IVT, DCD
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+ * and some padding thus 'our' max size is really 0x00908000 - 0x00938000
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+ * or 192KB
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+ */
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+#define CONFIG_SPL_MAX_SIZE 0x30000
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+#define CONFIG_SPL_STACK 0x0093FFB8
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+/*
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+ * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the
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+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
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+ * boot media (given that boot media specific offset is configured properly).
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+ */
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+#define CONFIG_SPL_PAD_TO 0x31000
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+#else
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+/*
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+ * see Figure 8-3 in IMX6SDL Reference manuals:
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* - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
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- * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well
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* - BOOT ROM stack is at 0x0091FFB8
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* - if icache/dcache is enabled (eFuse/strapping controlled) then the
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* IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
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@@ -29,6 +51,8 @@
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*/
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#define CONFIG_SPL_PAD_TO 0x11000
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+#endif
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+
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/* MMC support */
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#if defined(CONFIG_SPL_MMC_SUPPORT)
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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