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@@ -38,6 +38,58 @@ static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
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#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
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#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
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+static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
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+{
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+ u64 max_addr = 0;
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+ u64 ips, va_bits;
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+ u64 tcr;
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+ int i;
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+
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+ /* Find the largest address we need to support */
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+ for (i = 0; i < ARRAY_SIZE(mem_map); i++)
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+ max_addr = max(max_addr, mem_map[i].base + mem_map[i].size);
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+
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+ /* Calculate the maximum physical (and thus virtual) address */
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+ if (max_addr > (1ULL << 44)) {
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+ ips = 5;
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+ va_bits = 48;
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+ } else if (max_addr > (1ULL << 42)) {
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+ ips = 4;
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+ va_bits = 44;
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+ } else if (max_addr > (1ULL << 40)) {
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+ ips = 3;
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+ va_bits = 42;
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+ } else if (max_addr > (1ULL << 36)) {
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+ ips = 2;
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+ va_bits = 40;
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+ } else if (max_addr > (1ULL << 32)) {
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+ ips = 1;
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+ va_bits = 36;
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+ } else {
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+ ips = 0;
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+ va_bits = 32;
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+ }
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+
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+ if (el == 1) {
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+ tcr = TCR_EL1_RSVD | (ips << 32);
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+ } else if (el == 2) {
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+ tcr = TCR_EL2_RSVD | (ips << 16);
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+ } else {
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+ tcr = TCR_EL3_RSVD | (ips << 16);
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+ }
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+
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+ /* PTWs cacheable, inner/outer WBWA and inner shareable */
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+ tcr |= TCR_TG0_64K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
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+ tcr |= TCR_T0SZ(VA_BITS);
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+
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+ if (pips)
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+ *pips = ips;
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+ if (pva_bits)
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+ *pva_bits = va_bits;
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+
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+ return tcr;
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+}
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+
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static void setup_pgtables(void)
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{
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int l1_e, l2_e;
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@@ -110,6 +162,10 @@ __weak void mmu_setup(void)
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/* Set up page tables only on BSP */
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if (coreid == BSP_COREID)
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setup_pgtables();
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+
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+ el = current_el();
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+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
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+ MEMORY_ATTRIBUTES);
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#else
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/* Setup an identity-mapping for all spaces */
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for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
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@@ -128,7 +184,6 @@ __weak void mmu_setup(void)
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}
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}
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-#endif
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/* load TTBR0 */
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el = current_el();
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if (el == 1) {
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@@ -144,6 +199,8 @@ __weak void mmu_setup(void)
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TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
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MEMORY_ATTRIBUTES);
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}
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+#endif
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+
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/* enable the mmu */
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set_sctlr(get_sctlr() | CR_M);
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}
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