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@@ -15,16 +15,28 @@
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DECLARE_GLOBAL_DATA_PTR;
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-static struct mm_region zynqmp_mem_map[] = {
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+/*
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+ * Number of filled static entries and also the first empty
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+ * slot in zynqmp_mem_map.
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+ */
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+#define ZYNQMP_MEM_MAP_USED 4
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+
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#if !defined(CONFIG_ZYNQMP_NO_DDR)
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- {
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- .virt = 0x0UL,
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- .phys = 0x0UL,
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- .size = 0x80000000UL,
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- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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- PTE_BLOCK_INNER_SHARE
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- },
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+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
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+#else
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+#define DRAM_BANKS 0
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#endif
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+
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+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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+#define TCM_MAP 1
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+#else
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+#define TCM_MAP 0
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+#endif
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+
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+/* +1 is end of list which needs to be empty */
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+#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
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+
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+static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
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{
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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@@ -32,8 +44,7 @@ static struct mm_region zynqmp_mem_map[] = {
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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- },
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- {
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+ }, {
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.virt = 0xf8000000UL,
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.phys = 0xf8000000UL,
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.size = 0x07e00000UL,
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@@ -41,42 +52,51 @@ static struct mm_region zynqmp_mem_map[] = {
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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-#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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- .virt = 0xffe00000UL,
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- .phys = 0xffe00000UL,
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- .size = 0x00200000UL,
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- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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- PTE_BLOCK_INNER_SHARE
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- }, {
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-#endif
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.virt = 0x400000000UL,
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.phys = 0x400000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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- },
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-#if !defined(CONFIG_ZYNQMP_NO_DDR)
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- {
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- .virt = 0x800000000UL,
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- .phys = 0x800000000UL,
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- .size = 0x800000000UL,
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- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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- PTE_BLOCK_INNER_SHARE
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- },
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-#endif
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- {
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+ }, {
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.virt = 0x1000000000UL,
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.phys = 0x1000000000UL,
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.size = 0xf000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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- }, {
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- /* List terminator */
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- 0,
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}
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};
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+
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+void mem_map_fill(void)
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+{
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+ int banks = ZYNQMP_MEM_MAP_USED;
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+
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+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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+ zynqmp_mem_map[banks].virt = 0xffe00000UL;
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+ zynqmp_mem_map[banks].phys = 0xffe00000UL;
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+ zynqmp_mem_map[banks].size = 0x00200000UL;
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+ zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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+ PTE_BLOCK_INNER_SHARE;
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+ banks = banks + 1;
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+#endif
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+
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+#if !defined(CONFIG_ZYNQMP_NO_DDR)
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+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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+ /* Zero size means no more DDR that's this is end */
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+ if (!gd->bd->bi_dram[i].size)
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+ break;
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+
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+ zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
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+ zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
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+ zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
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+ zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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+ PTE_BLOCK_INNER_SHARE;
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+ banks = banks + 1;
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+ }
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+#endif
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+}
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+
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struct mm_region *mem_map = zynqmp_mem_map;
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u64 get_page_table_size(void)
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