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ARM: Move SYS_CACHELINE_SIZE over to Kconfig

This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Tom Rini 7 роки тому
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067716bac5
81 змінених файлів з 32 додано та 182 видалено
  1. 27 0
      arch/arm/Kconfig
  2. 0 5
      arch/arm/cpu/arm11/cpu.c
  3. 0 5
      arch/arm/cpu/arm926ejs/cache.c
  4. 0 5
      arch/arm/cpu/pxa/cache.c
  5. 0 2
      arch/arm/include/asm/arch-armada100/config.h
  6. 0 2
      arch/arm/include/asm/arch-fsl-layerscape/config.h
  7. 0 2
      arch/arm/include/asm/arch-ls102xa/config.h
  8. 0 2
      arch/arm/include/asm/arch-mx5/imx-regs.h
  9. 0 6
      arch/arm/include/asm/arch-mx6/imx-regs.h
  10. 0 2
      arch/arm/include/asm/arch-mx7/imx-regs.h
  11. 4 7
      arch/arm/include/asm/cache.h
  12. 0 4
      arch/arm/lib/cache.c
  13. 0 2
      arch/arm/mach-kirkwood/include/mach/config.h
  14. 0 2
      arch/arm/mach-mvebu/include/mach/config.h
  15. 1 0
      arch/arm/mach-uniphier/Kconfig
  16. 0 2
      include/configs/am3517_crane.h
  17. 0 2
      include/configs/am3517_evm.h
  18. 0 2
      include/configs/am43xx_evm.h
  19. 0 2
      include/configs/at91-sama5_common.h
  20. 0 1
      include/configs/bcm23550_w1d.h
  21. 0 1
      include/configs/bcm28155_ap.h
  22. 0 2
      include/configs/bcm_ep_board.h
  23. 0 1
      include/configs/bur_am335x_common.h
  24. 0 3
      include/configs/cm_t3517.h
  25. 0 1
      include/configs/cm_t43.h
  26. 0 4
      include/configs/colibri_vf.h
  27. 0 1
      include/configs/corvus.h
  28. 0 2
      include/configs/dragonboard410c.h
  29. 0 1
      include/configs/exynos4-common.h
  30. 0 1
      include/configs/exynos5-common.h
  31. 0 1
      include/configs/flea3.h
  32. 0 3
      include/configs/hikey.h
  33. 0 1
      include/configs/kc1.h
  34. 0 2
      include/configs/kzm9g.h
  35. 0 2
      include/configs/mcx.h
  36. 0 1
      include/configs/meson-gxbb-common.h
  37. 0 2
      include/configs/nokia_rx51.h
  38. 0 2
      include/configs/omap3_beagle.h
  39. 0 2
      include/configs/omap3_cairo.h
  40. 0 2
      include/configs/omap3_evm.h
  41. 0 1
      include/configs/omap3_logic.h
  42. 0 1
      include/configs/omap3_overo.h
  43. 0 2
      include/configs/omap3_pandora.h
  44. 0 2
      include/configs/omap3_zoom1.h
  45. 0 2
      include/configs/pcm052.h
  46. 0 2
      include/configs/rcar-gen2-common.h
  47. 0 2
      include/configs/rk3036_common.h
  48. 0 2
      include/configs/rk3288_common.h
  49. 0 2
      include/configs/rk3399_common.h
  50. 0 6
      include/configs/rpi.h
  51. 0 4
      include/configs/s5p_goni.h
  52. 0 2
      include/configs/siemens-am33x-common.h
  53. 0 2
      include/configs/smartweb.h
  54. 0 2
      include/configs/smdkc100.h
  55. 0 2
      include/configs/sniper.h
  56. 0 1
      include/configs/socfpga_common.h
  57. 0 1
      include/configs/sunxi-common.h
  58. 0 2
      include/configs/tam3517-common.h
  59. 0 2
      include/configs/tao3530.h
  60. 0 2
      include/configs/taurus.h
  61. 0 3
      include/configs/tegra114-common.h
  62. 0 3
      include/configs/tegra124-common.h
  63. 0 3
      include/configs/tegra186-common.h
  64. 0 3
      include/configs/tegra20-common.h
  65. 0 3
      include/configs/tegra210-common.h
  66. 0 3
      include/configs/tegra30-common.h
  67. 0 2
      include/configs/ti814x_evm.h
  68. 0 2
      include/configs/ti816x_evm.h
  69. 0 1
      include/configs/ti_am335x_common.h
  70. 0 1
      include/configs/ti_armv7_keystone2.h
  71. 0 2
      include/configs/ti_omap3_common.h
  72. 0 1
      include/configs/ti_omap4_common.h
  73. 0 2
      include/configs/ti_omap5_common.h
  74. 0 2
      include/configs/tricorder.h
  75. 0 6
      include/configs/uniphier.h
  76. 0 3
      include/configs/vexpress_aemv8a.h
  77. 0 2
      include/configs/vexpress_common.h
  78. 0 2
      include/configs/vf610twr.h
  79. 0 1
      include/configs/woodburn_common.h
  80. 0 3
      include/configs/xilinx_zynqmp.h
  81. 0 2
      include/configs/zynq-common.h

+ 27 - 0
arch/arm/Kconfig

@@ -7,6 +7,7 @@ config SYS_ARCH
 config ARM64
 	bool
 	select PHYS_64BIT
+	select SYS_CACHE_SHIFT_6
 
 config DMA_ADDR_T_64BIT
 	bool
@@ -20,37 +21,47 @@ config HAS_THUMB2
 
 config CPU_ARM720T
         bool
+	select SYS_CACHE_SHIFT_5
 
 config CPU_ARM920T
         bool
+	select SYS_CACHE_SHIFT_5
 
 config CPU_ARM926EJS
         bool
+	select SYS_CACHE_SHIFT_5
 
 config CPU_ARM946ES
         bool
+	select SYS_CACHE_SHIFT_5
 
 config CPU_ARM1136
         bool
+	select SYS_CACHE_SHIFT_5
 
 config CPU_ARM1176
         bool
         select HAS_VBAR
+	select SYS_CACHE_SHIFT_5
 
 config CPU_V7
         bool
         select HAS_VBAR
         select HAS_THUMB2
+	select SYS_CACHE_SHIFT_6
 
 config CPU_V7M
 	bool
         select HAS_THUMB2
+	select SYS_CACHE_SHIFT_5
 
 config CPU_PXA
         bool
+	select SYS_CACHE_SHIFT_5
 
 config CPU_SA1100
         bool
+	select SYS_CACHE_SHIFT_5
 
 config SYS_CPU
         default "arm720t" if CPU_ARM720T
@@ -79,6 +90,21 @@ config SYS_ARM_ARCH
 	default 4 if CPU_SA1100
 	default 8 if ARM64
 
+config SYS_CACHE_SHIFT_5
+	bool
+
+config SYS_CACHE_SHIFT_6
+	bool
+
+config SYS_CACHE_SHIFT_7
+	bool
+
+config SYS_CACHELINE_SIZE
+	int
+	default 128 if SYS_CACHE_SHIFT_7
+	default 64 if SYS_CACHE_SHIFT_6
+	default 32 if SYS_CACHE_SHIFT_5
+
 config SEMIHOSTING
 	bool "support boot from semihosting"
 	help
@@ -867,6 +893,7 @@ config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
 	select ARM64
 	select OF_CONTROL
+	select SYS_CACHE_SHIFT_7
 
 endchoice
 

+ 0 - 5
arch/arm/cpu/arm11/cpu.c

@@ -53,11 +53,6 @@ static void cache_flush(void)
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
 void invalidate_dcache_all(void)
 {
 	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));

+ 0 - 5
arch/arm/cpu/arm926ejs/cache.c

@@ -8,11 +8,6 @@
 #include <common.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
 void invalidate_dcache_all(void)
 {
 	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));

+ 0 - 5
arch/arm/cpu/pxa/cache.c

@@ -8,11 +8,6 @@
 #include <common.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
 void invalidate_dcache_all(void)
 {
 	/* Flush/Invalidate I cache */

+ 0 - 2
arch/arm/include/asm/arch-armada100/config.h

@@ -16,8 +16,6 @@
 #define _ARMD1_CONFIG_H
 
 #include <asm/arch/armada100.h>
-/* default Dcache Line length for armada100 */
-#define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */

+ 0 - 2
arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -36,7 +36,6 @@
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_PAGE_SIZE		0x10000
-#define CONFIG_SYS_CACHELINE_SIZE	64
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
@@ -150,7 +149,6 @@
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_CACHELINE_SIZE		64
 #define CONFIG_NUM_DDR_CONTROLLERS		1
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */

+ 0 - 2
arch/arm/include/asm/arch-ls102xa/config.h

@@ -7,8 +7,6 @@
 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
 #define _ASM_ARMV7_LS102XA_CONFIG_
 
-#define CONFIG_SYS_CACHELINE_SIZE		64
-
 #define OCRAM_BASE_ADDR				0x10000000
 #define OCRAM_SIZE				0x00010000
 #define OCRAM_BASE_S_ADDR			0x10010000

+ 0 - 2
arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -9,8 +9,6 @@
 
 #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
 #define IPU_SOC_BASE_ADDR	0x40000000

+ 0 - 6
arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -9,12 +9,6 @@
 
 #define ARCH_MXC
 
-#ifdef CONFIG_MX6UL
-#define CONFIG_SYS_CACHELINE_SIZE	64
-#else
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
 

+ 0 - 2
arch/arm/include/asm/arch-mx7/imx-regs.h

@@ -9,8 +9,6 @@
 
 #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define ROM_SW_INFO_ADDR                0x000001E8
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x00017FFF

+ 4 - 7
arch/arm/include/asm/cache.h

@@ -43,14 +43,11 @@ void dram_bank_mmu_setup(int bank);
 #endif
 
 /*
- * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
- * use that value for aligning DMA buffers unless the board config has specified
- * an alternate cache line size.
+ * The value of the largest data cache relevant to DMA operations shall be set
+ * for us in CONFIG_SYS_CACHELINE_SIZE.  In some cases this may be a larger
+ * value than found in the L1 cache but this is OK to use in terms of
+ * alignment.
  */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
 #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	64
-#endif
 
 #endif /* _ASM_CACHE_H */

+ 0 - 4
arch/arm/lib/cache.c

@@ -10,10 +10,6 @@
 #include <common.h>
 #include <malloc.h>
 
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
 /*
  * Flush range from all levels of d-cache/unified-cache.
  * Affects the range [start, start + size - 1].

+ 0 - 2
arch/arm/mach-kirkwood/include/mach/config.h

@@ -24,8 +24,6 @@
 #endif /* CONFIG_KW88F6281 */
 
 #include <asm/arch/soc.h>
-#define CONFIG_SYS_CACHELINE_SIZE	32
-				/* default Dcache Line length for kirkwood */
 #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
 #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */

+ 0 - 2
arch/arm/mach-mvebu/include/mach/config.h

@@ -26,8 +26,6 @@
 #define MV88F78X60 /* for the DDR training bin_hdr code */
 #endif
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #define CONFIG_SYS_L2_PL310
 
 #ifdef CONFIG_SPL_BUILD

+ 1 - 0
arch/arm/mach-uniphier/Kconfig

@@ -75,6 +75,7 @@ config ARCH_UNIPHIER_LD6B
 config CACHE_UNIPHIER
 	bool "Enable the UniPhier L2 cache controller"
 	depends on ARCH_UNIPHIER_32BIT
+	select SYS_CACHE_SHIFT_7
 	default y
 	help
 	  This option allows to use the UniPhier System Cache as L2 cache.

+ 0 - 2
include/configs/am3517_crane.h

@@ -13,8 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * High Level Configuration Options
  */

+ 0 - 2
include/configs/am3517_evm.h

@@ -18,8 +18,6 @@
 #define CONFIG_OMAP
 #define CONFIG_OMAP_COMMON
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */

+ 0 - 2
include/configs/am43xx_evm.h

@@ -11,7 +11,6 @@
 
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE       32
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
@@ -49,7 +48,6 @@
 /* Enabling L2 Cache */
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE	0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
  * Since SPL did pll and ddr initialization for us,

+ 0 - 2
include/configs/at91-sama5_common.h

@@ -12,8 +12,6 @@
 
 #include <asm/hardware.h>
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #define CONFIG_SYS_TEXT_BASE		0x26f00000
 
 /* ARM asynchronous clock */

+ 0 - 1
include/configs/bcm23550_w1d.h

@@ -127,7 +127,6 @@
 /* Commands */
 #define CONFIG_FAT_WRITE
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
 #undef CONFIG_USB_GADGET_VBUS_DRAW
 #define CONFIG_USB_GADGET_VBUS_DRAW	0
 #define CONFIG_USBID_ADDR		0x34052c46

+ 0 - 1
include/configs/bcm28155_ap.h

@@ -126,7 +126,6 @@
 /* Commands */
 #define CONFIG_FAT_WRITE
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_USBID_ADDR		0x34052c46
 
 #endif /* __BCM28155_AP_H */

+ 0 - 2
include/configs/bcm_ep_board.h

@@ -11,8 +11,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * Memory configuration
  * (these must be defined elsewhere)

+ 0 - 1
include/configs/bur_am335x_common.h

@@ -15,7 +15,6 @@
 #define CONFIG_AM33XX
 #define CONFIG_OMAP
 #define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
 /* Timer information */

+ 0 - 3
include/configs/cm_t3517.h

@@ -10,8 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * High Level Configuration Options
  */
@@ -30,7 +28,6 @@
  * Although the default iss 64, we still define it
  * to be on the safe side once the default is changed.
  */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 

+ 0 - 1
include/configs/cm_t43.h

@@ -79,7 +79,6 @@
 /* Enabling L2 Cache */
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE		0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
  * Since SPL did pll and ddr initialization for us,

+ 0 - 4
include/configs/colibri_vf.h

@@ -12,8 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610
@@ -207,8 +205,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
 /* USB Host Support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_VF

+ 0 - 1
include/configs/corvus.h

@@ -118,7 +118,6 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
-#define CONFIG_SYS_CACHELINE_SIZE	SZ_8K
 #define CONFIG_SYS_LOAD_ADDR	ATMEL_BASE_CS6
 
 /* bootstrap + u-boot + env in nandflash */

+ 0 - 2
include/configs/dragonboard410c.h

@@ -27,8 +27,6 @@
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
 #define CONFIG_SYS_BOOTM_LEN		0x1000000 /* 16MB max kernel size */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /* UART */
 #define CONFIG_BAUDRATE			115200
 

+ 0 - 1
include/configs/exynos4-common.h

@@ -15,7 +15,6 @@
 
 #define CONFIG_BOARD_COMMON
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
 #define CONFIG_REVISION_TAG
 
 /* SD/MMC configuration */

+ 0 - 1
include/configs/exynos5-common.h

@@ -13,7 +13,6 @@
 
 #include "exynos-common.h"
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_EXYNOS_SPL
 
 #ifdef FTRACE

+ 0 - 1
include/configs/flea3.h

@@ -19,7 +19,6 @@
 #define CONFIG_MX35
 
 #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define CONFIG_DISPLAY_CPUINFO
 

+ 0 - 3
include/configs/hikey.h

@@ -21,9 +21,6 @@
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_IDENT_STRING		"hikey"
 
 #define CONFIG_BOARD_EARLY_INIT_F

+ 0 - 1
include/configs/kc1.h

@@ -24,7 +24,6 @@
 
 #define CONFIG_SYS_L2_PL310		1
 #define CONFIG_SYS_PL310_BASE		0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
  * Platform

+ 0 - 2
include/configs/kzm9g.h

@@ -10,8 +10,6 @@
 
 #undef DEBUG
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #define CONFIG_SH73A0
 #define CONFIG_KZM_A9_GT
 #define CONFIG_ARCH_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"

+ 0 - 2
include/configs/mcx.h

@@ -25,8 +25,6 @@
 #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */

+ 0 - 1
include/configs/meson-gxbb-common.h

@@ -10,7 +10,6 @@
 
 #define CONFIG_CPU_ARMV8
 #define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_ENV_IS_NOWHERE		1

+ 0 - 2
include/configs/nokia_rx51.h

@@ -19,8 +19,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
 /*
  * High Level Configuration Options
  */

+ 0 - 2
include/configs/omap3_beagle.h

@@ -275,8 +275,6 @@
 
 #define CONFIG_OMAP3_SPI
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /* Defines for SPL */
 #define CONFIG_SPL_OMAP3_ID_NAND
 

+ 0 - 2
include/configs/omap3_cairo.h

@@ -192,8 +192,6 @@
 
 #define CONFIG_OMAP3_SPI
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /* Defines for SPL */
 #define CONFIG_SPL_OMAP3_ID_NAND
 

+ 0 - 2
include/configs/omap3_evm.h

@@ -340,8 +340,6 @@
 /* Uncomment to define the board revision statically */
 /* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /* Defines for SPL */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		0x40200800

+ 0 - 1
include/configs/omap3_logic.h

@@ -82,7 +82,6 @@
 #define CONFIG_ANDROID_BOOT_IMAGE
 #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* TWL4030 */
 #define CONFIG_TWL4030_PWM

+ 0 - 1
include/configs/omap3_overo.h

@@ -215,7 +215,6 @@
 /* Initial RAM setup */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT

+ 0 - 2
include/configs/omap3_pandora.h

@@ -119,6 +119,4 @@
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #endif				/* __CONFIG_H */

+ 0 - 2
include/configs/omap3_zoom1.h

@@ -176,8 +176,6 @@
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #ifdef CONFIG_CMD_NET
 /* Ethernet (LAN9211 from SMSC9118 family) */
 #define CONFIG_SMC911X

+ 0 - 2
include/configs/pcm052.h

@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610

+ 0 - 2
include/configs/rcar-gen2-common.h

@@ -9,8 +9,6 @@
 #ifndef __RCAR_GEN2_COMMON_H
 #define __RCAR_GEN2_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
 #include <asm/arch/rmobile.h>
 
 #define CONFIG_CMD_DFL

+ 0 - 2
include/configs/rk3036_common.h

@@ -6,8 +6,6 @@
 #ifndef __CONFIG_RK3036_COMMON_H
 #define __CONFIG_RK3036_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #include <asm/arch/hardware.h>
 
 #define CONFIG_SYS_NO_FLASH

+ 0 - 2
include/configs/rk3288_common.h

@@ -7,8 +7,6 @@
 #ifndef __CONFIG_RK3288_COMMON_H
 #define __CONFIG_RK3288_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #include <asm/arch/hardware.h>
 
 #define CONFIG_SYS_NO_FLASH

+ 0 - 2
include/configs/rk3399_common.h

@@ -7,8 +7,6 @@
 #ifndef __CONFIG_RK3399_COMMON_H
 #define __CONFIG_RK3399_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_ENV_SIZE			0x2000

+ 0 - 6
include/configs/rpi.h

@@ -14,12 +14,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
-#ifdef CONFIG_BCM2835
-#define CONFIG_SYS_CACHELINE_SIZE		32
-#else
-#define CONFIG_SYS_CACHELINE_SIZE		64
-#endif
-
 /* Architecture, CPU, etc.*/
 #define CONFIG_ARCH_CPU_INIT
 

+ 0 - 4
include/configs/s5p_goni.h

@@ -17,8 +17,6 @@
 #define CONFIG_S5PC110		1	/* which is in a S5PC110 */
 #define CONFIG_MACH_GONI	1	/* working with Goni */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #include <linux/sizes.h>
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 
@@ -236,8 +234,6 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
 
-#define CONFIG_SYS_CACHELINE_SIZE       64
-
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX8998

+ 0 - 2
include/configs/siemens-am33x-common.h

@@ -36,8 +36,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_SYS_CACHELINE_SIZE       64
-
 /* commands to include */
 
 #define CONFIG_ENV_VARS_UBOOT_CONFIG

+ 0 - 2
include/configs/smartweb.h

@@ -170,8 +170,6 @@
 #define CONFIG_DFU_NAND
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
-
-#define CONFIG_SYS_CACHELINE_SIZE	0x2000
 #endif
 
 /* General Boot Parameter */

+ 0 - 2
include/configs/smdkc100.h

@@ -12,8 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * High Level Configuration Options
  * (easy to change)

+ 0 - 2
include/configs/sniper.h

@@ -16,8 +16,6 @@
  * CPU
  */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_ARM_ARCH_CP15_ERRATA
 #define CONFIG_ARM_ERRATA_454179
 #define CONFIG_ARM_ERRATA_430973

+ 0 - 1
include/configs/socfpga_common.h

@@ -75,7 +75,6 @@
 /*
  * Cache
  */
-#define CONFIG_SYS_CACHELINE_SIZE 32
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 

+ 0 - 1
include/configs/sunxi-common.h

@@ -55,7 +55,6 @@
 
 /* CPU */
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_TIMER_CLK_FREQ		24000000
 
 /*

+ 0 - 2
include/configs/tam3517-common.h

@@ -23,8 +23,6 @@
 
 #define CONFIG_SYS_TEXT_BASE 0x80008000
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */

+ 0 - 2
include/configs/tao3530.h

@@ -13,8 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * High Level Configuration Options
  */

+ 0 - 2
include/configs/taurus.h

@@ -133,8 +133,6 @@
 #define CONFIG_DFU_NAND
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
-
-#define CONFIG_SYS_CACHELINE_SIZE	SZ_8K
 #endif
 
 /* SPI EEPROM */

+ 0 - 3
include/configs/tegra114-common.h

@@ -8,9 +8,6 @@
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * NS16550 Configuration
  */

+ 0 - 3
include/configs/tegra124-common.h

@@ -10,9 +10,6 @@
 
 #include "tegra-common.h"
 
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * NS16550 Configuration
  */

+ 0 - 3
include/configs/tegra186-common.h

@@ -9,9 +9,6 @@
 
 #include "tegra-common.h"
 
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * NS16550 Configuration
  */

+ 0 - 3
include/configs/tegra20-common.h

@@ -9,9 +9,6 @@
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 /*
  * Errata configuration
  */

+ 0 - 3
include/configs/tegra210-common.h

@@ -10,9 +10,6 @@
 
 #include "tegra-common.h"
 
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * NS16550 Configuration
  */

+ 0 - 3
include/configs/tegra30-common.h

@@ -9,9 +9,6 @@
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 /*
  * Errata configuration
  */

+ 0 - 2
include/configs/ti814x_evm.h

@@ -16,8 +16,6 @@
 #ifndef __CONFIG_TI814X_EVM_H
 #define __CONFIG_TI814X_EVM_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_TI81XX
 #define CONFIG_TI814X
 #define CONFIG_SYS_NO_FLASH

+ 0 - 2
include/configs/ti816x_evm.h

@@ -10,8 +10,6 @@
 #ifndef __CONFIG_TI816X_EVM_H
 #define __CONFIG_TI816X_EVM_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_TI81XX
 #define CONFIG_TI816X
 #define CONFIG_SYS_NO_FLASH

+ 0 - 1
include/configs/ti_am335x_common.h

@@ -14,7 +14,6 @@
 
 #define CONFIG_AM33XX
 #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC

+ 0 - 1
include/configs/ti_armv7_keystone2.h

@@ -200,7 +200,6 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_EFI_PARTITION
 #define CONFIG_FS_FAT
-#define CONFIG_SYS_CACHELINE_SIZE		64
 #define CONFIG_USB_SS_BASE			KS2_USB_SS_BASE
 #define CONFIG_USB_HOST_XHCI_BASE		KS2_USB_HOST_XHCI_BASE
 #define CONFIG_DEV_USB_PHY_BASE			KS2_DEV_USB_PHY_BASE

+ 0 - 2
include/configs/ti_omap3_common.h

@@ -18,8 +18,6 @@
  * High Level Configuration Options
  */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #include <asm/arch/cpu.h>
 #include <asm/arch/omap.h>
 

+ 0 - 1
include/configs/ti_omap4_common.h

@@ -26,7 +26,6 @@
 #define CONFIG_SYS_L2_PL310		1
 #define CONFIG_SYS_PL310_BASE	0x48242000
 #endif
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>

+ 0 - 2
include/configs/ti_omap5_common.h

@@ -23,8 +23,6 @@
 /* Common ARM Erratas */
 #define CONFIG_ARM_ERRATA_798870
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /* Use General purpose timer 1 */
 #define CONFIG_SYS_TIMERBASE		GPT2_BASE
 

+ 0 - 2
include/configs/tricorder.h

@@ -16,8 +16,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /* High Level Configuration Options */
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_OMAP			/* in a TI OMAP core */

+ 0 - 6
include/configs/uniphier.h

@@ -30,12 +30,6 @@
 /* #define CONFIG_SYS_ICACHE_OFF */
 /* #define CONFIG_SYS_DCACHE_OFF */
 
-#ifdef CONFIG_CACHE_UNIPHIER
-#define CONFIG_SYS_CACHELINE_SIZE	128
-#else
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_F

+ 0 - 3
include/configs/vexpress_aemv8a.h

@@ -19,9 +19,6 @@
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
 
 /* Link Definitions */

+ 0 - 2
include/configs/vexpress_common.h

@@ -118,8 +118,6 @@
 #define CONFIG_SYS_MEMTEST_START	V2M_BASE
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_SYS_L2CACHE_OFF		1

+ 0 - 2
include/configs/vf610twr.h

@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610

+ 0 - 1
include/configs/woodburn_common.h

@@ -19,7 +19,6 @@
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define CONFIG_DISPLAY_CPUINFO
 

+ 0 - 3
include/configs/xilinx_zynqmp.h

@@ -34,9 +34,6 @@
 /* Have release address at the end of 256MB for now */
 #define CPU_RELEASE_ADDR	0xFFFFFF0
 
-/* Cache Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 #if !defined(CONFIG_IDENT_STRING)
 # define CONFIG_IDENT_STRING		" Xilinx ZynqMP"
 #endif

+ 0 - 2
include/configs/zynq-common.h

@@ -16,8 +16,6 @@
 #endif
 
 /* Cache options */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
 # define CONFIG_SYS_L2_PL310