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@@ -374,28 +374,6 @@ void init_wdog_clk(void)
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clock_enable(CCGR_WDOG3, 1);
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}
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-void init_usb_clk(void)
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-{
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- if (!is_usb_boot()) {
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- clock_enable(CCGR_USB_CTRL1, 0);
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- clock_enable(CCGR_USB_CTRL2, 0);
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- clock_enable(CCGR_USB_PHY1, 0);
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- clock_enable(CCGR_USB_PHY2, 0);
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- /* 500MHz */
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- clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
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- CLK_ROOT_SOURCE_SEL(1));
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- /* 100MHz */
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- clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
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- CLK_ROOT_SOURCE_SEL(1));
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- /* 100MHz */
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- clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
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- CLK_ROOT_SOURCE_SEL(1));
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- clock_enable(CCGR_USB_CTRL1, 1);
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- clock_enable(CCGR_USB_CTRL2, 1);
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- clock_enable(CCGR_USB_PHY1, 1);
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- clock_enable(CCGR_USB_PHY2, 1);
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- }
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-}
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void init_nand_clk(void)
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{
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@@ -658,7 +636,7 @@ void dram_pll_init(ulong pll_val)
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;
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}
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-int frac_pll_init(u32 pll, enum frac_pll_out_val val)
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+static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
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{
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void __iomem *pll_cfg0, __iomem *pll_cfg1;
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u32 val_cfg0, val_cfg1;
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@@ -699,77 +677,6 @@ int frac_pll_init(u32 pll, enum frac_pll_out_val val)
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return 0;
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}
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-int sscg_pll_init(u32 pll)
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-{
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- void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
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- u32 val_cfg0, val_cfg1, val_cfg2, val;
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- u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
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- int ret;
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-
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- switch (pll) {
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- case ANATOP_SYSTEM_PLL1:
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- pll_cfg0 = &ana_pll->sys_pll1_cfg0;
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- pll_cfg1 = &ana_pll->sys_pll1_cfg1;
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- pll_cfg2 = &ana_pll->sys_pll1_cfg2;
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- /* 800MHz */
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- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
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- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
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- val_cfg1 = 0;
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- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
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- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
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- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
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- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
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- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
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- SSCG_PLL_REFCLK_SEL_OSC_25M;
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- break;
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- case ANATOP_SYSTEM_PLL2:
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- pll_cfg0 = &ana_pll->sys_pll2_cfg0;
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- pll_cfg1 = &ana_pll->sys_pll2_cfg1;
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- pll_cfg2 = &ana_pll->sys_pll2_cfg2;
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- /* 1000MHz */
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- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
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- SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
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- val_cfg1 = 0;
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- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
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- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
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- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
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- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
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- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
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- SSCG_PLL_REFCLK_SEL_OSC_25M;
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- break;
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- case ANATOP_SYSTEM_PLL3:
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- pll_cfg0 = &ana_pll->sys_pll3_cfg0;
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- pll_cfg1 = &ana_pll->sys_pll3_cfg1;
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- pll_cfg2 = &ana_pll->sys_pll3_cfg2;
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- /* 800MHz */
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- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
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- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
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- val_cfg1 = 0;
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- val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
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- SSCG_PLL_REFCLK_SEL_OSC_25M;
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- break;
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- default:
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- return -EINVAL;
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- }
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-
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- /*bypass*/
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- setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
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- /* set value */
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- writel(val_cfg2, pll_cfg2);
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- writel(val_cfg1, pll_cfg1);
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- /*unbypass1 and wait 70us */
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- writel(val_cfg0 | bypass2_mask, pll_cfg1);
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-
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- __udelay(70);
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-
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- /* unbypass2 and wait lock */
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- writel(val_cfg0, pll_cfg1);
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- ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
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- if (ret)
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- printf("%s timeout\n", __func__);
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-
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- return ret;
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-}
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int clock_init(void)
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{
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@@ -833,7 +740,7 @@ int clock_init(void)
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* Dump some clockes.
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*/
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#ifndef CONFIG_SPL_BUILD
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-int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
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+static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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u32 freq;
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