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@@ -0,0 +1,96 @@
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+/dts-v1/;
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+/ {
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+ compatible = "riscv32 nx25";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ interrupt-parent = <&intc>;
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+
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+ aliases {
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+ uart0 = &serial0;
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+ ethernet0 = &mac0;
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+ spi0 = &spi;
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+ } ;
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+
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+ chosen {
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+ bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
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+ stdout-path = "uart0:38400n8";
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+ tick-timer = &timer0;
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+ };
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+
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+ memory@0 {
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+ device_type = "memory";
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+ reg = <0x00000000 0x40000000>;
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+ };
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+
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+ spiclk: virt_100mhz {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <100000000>;
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ cpu@0 {
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+ compatible = "andestech,n13";
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+ reg = <0>;
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+ /* FIXME: to fill correct frqeuency */
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+ clock-frequency = <60000000>;
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+ };
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+ };
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+
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+ intc: interrupt-controller {
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+ compatible = "andestech,atnointc010";
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+
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+ serial0: serial@f0300000 {
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+ compatible = "andestech,uart16550", "ns16550a";
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+ reg = <0xf0300000 0x1000>;
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+ interrupts = <7 4>;
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+ clock-frequency = <19660800>;
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+ reg-shift = <2>;
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+ reg-offset = <32>;
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+ no-loopback-test = <1>;
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+ };
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+
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+ timer0: timer@f0400000 {
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+ compatible = "andestech,atcpit100";
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+ reg = <0xf0400000 0x1000>;
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+ interrupts = <2 4>;
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+ clock-frequency = <40000000>;
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+ };
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+
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+ mac0: mac@e0100000 {
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+ compatible = "andestech,atmac100";
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+ reg = <0xe0100000 0x1000>;
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+ interrupts = <25 4>;
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+ };
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+
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+ mmc0: mmc@f0e00000 {
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+ compatible = "andestech,atsdc010";
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+ max-frequency = <100000000>;
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+ fifo-depth = <0x10>;
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+ reg = <0xf0e00000 0x1000>;
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+ interrupts = <17 4>;
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+ };
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+
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+ spi: spi@f0b00000 {
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+ compatible = "andestech,atcspi200";
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+ reg = <0xf0b00000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ num-cs = <1>;
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+ clocks = <&spiclk>;
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+ interrupts = <3 4>;
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+ flash@0 {
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+ compatible = "spi-flash";
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+ spi-max-frequency = <50000000>;
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+ reg = <0>;
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+ spi-cpol;
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+ spi-cpha;
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+ };
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+ };
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+
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+};
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