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@@ -396,6 +396,19 @@ static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
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return 0;
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}
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+static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie,
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+ bool enable)
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+{
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+ u32 val;
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+
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+ fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, &val);
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+ if (enable)
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+ val |= 1;
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+ else
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+ val &= ~1;
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+ fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val);
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+}
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+
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static int fsl_pcie_init_port(struct fsl_pcie *pcie)
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{
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ccsr_fsl_pci_t *regs = pcie->regs;
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@@ -470,7 +483,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
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* Set to 0 to protect the read-only registers.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
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- clrbits_be32(®s->dbi_ro_wr_en, 0x01);
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+ fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
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#endif
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/*
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@@ -504,13 +517,12 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
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static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
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{
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- ccsr_fsl_pci_t *regs = pcie->regs;
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u32 classcode_reg;
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u32 val;
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
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classcode_reg = PCI_CLASS_REVISION;
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- setbits_be32(®s->dbi_ro_wr_en, 0x01);
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+ fsl_pcie_dbi_read_only_reg_write_enable(pcie, true);
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} else {
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classcode_reg = CSR_CLASSCODE;
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}
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@@ -521,7 +533,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
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fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
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if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
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- clrbits_be32(®s->dbi_ro_wr_en, 0x01);
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+ fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
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return 0;
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}
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