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@@ -485,15 +485,27 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
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static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
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{
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+ const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
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+ unsigned int esc_rate;
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+ u32 esc_clk_division;
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+
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/*
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* The maximum permitted escape clock is 20MHz and it is derived from
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- * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
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+ * lanebyteclk, which is running at "lane_mbps / 8".
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+ */
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+ if (phy_ops->get_esc_clk_rate)
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+ phy_ops->get_esc_clk_rate(dsi->device, &esc_rate);
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+ else
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+ esc_rate = 20; /* Default to 20MHz */
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+
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+ /*
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+ * We want:
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*
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- * (lane_mbps >> 3) / esc_clk_division < 20
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+ * (lane_mbps >> 3) / esc_clk_division < X
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* which is:
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- * (lane_mbps >> 3) / 20 > esc_clk_division
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+ * (lane_mbps >> 3) / X > esc_clk_division
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*/
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- u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
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+ esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
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dsi_write(dsi, DSI_PWR_UP, RESET);
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