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@@ -129,8 +129,8 @@ int ddr_calibration(unsigned int fsp_table[3])
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* Polling SIM LPDDR_CTRL2 Bit phy_freq_chg_req until be 1'b1
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*/
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reg_val = readl(AVD_SIM_LPDDR_CTRL2);
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- phy_freq_req = (reg_val >> 7) & 0x1;
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-
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+ /* DFS interrupt is set */
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+ phy_freq_req = ((reg_val >> 7) & 0x1) && ((reg_val >> 15) & 0x1);
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if (phy_freq_req) {
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phy_freq_type = reg_val & 0x1F;
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if (phy_freq_type == 0x00) {
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@@ -159,7 +159,11 @@ int ddr_calibration(unsigned int fsp_table[3])
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if (freq_chg_pt == 2)
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freq_chg_cnt--;
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}
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- reg_val = readl(AVD_SIM_LPDDR_CTRL2);
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+
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+ /* Hardware clear the ack on falling edge of LPDDR_CTRL2:phy_freq_chg_reg */
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+ /* Ensure the ack is clear before starting to poll request again */
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+ while ((readl(AVD_SIM_LPDDR_CTRL2) & BIT(6)))
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+ ;
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}
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} while (1);
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