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riscv:starfive-jh7110: clear L2 LIM memory

Clear L2 LIM memory on StarFive  JH7110, avoid some unexpect exception.
yanhong.wang 2 years ago
parent
commit
00018eb98a
1 changed files with 14 additions and 0 deletions
  1. 14 0
      arch/riscv/cpu/jh7110/spl.c

+ 14 - 0
arch/riscv/cpu/jh7110/spl.c

@@ -42,4 +42,18 @@ void harts_early_init(void)
 	 */
 	if (CONFIG_IS_ENABLED(RISCV_MMODE))
 		csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+#ifdef CONFIG_SPL_BUILD
+
+	/*clear L2 LIM  memory
+	 * set __bss_end to 0x81e0000 region to zero
+	 */
+	__asm__ __volatile__ (
+		"la t1, __bss_end\n"
+		"li t2, 0x81e0000\n"
+		"spl_clear_l2im:\n"
+			"addi t1, t1, 8\n"
+			"sd zero, 0(t1)\n"
+			"blt t1, t2, spl_clear_l2im\n");
+#endif
 }