/**
  ******************************************************************************
  * @file  isp_reg.h
  * @author  StarFive Isp Team
  * @version  V1.0
  * @date  12/14/2019
  * @brief  isp registers operation macro
  ******************************************************************************
  * @copy
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * Copyright (C)  2019 - 2022 StarFive Technology Co., Ltd.
  */
#ifndef __ISP_REG_H__
#define __ISP_REG_H__

//#include <asm/io.h>
typedef uint32_t UINT32;
////////////////////////////////////////////////////////////////////////////////////////////////////
// Parse from Isp_Register_List_20191214.csv
////////////////////////////////////////////////////////////////////////////////////////////////////
//#define REG_VARIABLE_ENABLE                1
//#define REG_FUNCTION_ENABLE                1
////////////////////////////////////////////////////////////////////////////////////////////////////
// Register offset define.
////////////////////////////////////////////////////////////////////////////////////////////////////
#define ADDR_ISP_BASE                      0x00000000
#define ADDR_REG_ENABLE_STATUS             (ADDR_ISP_BASE + 0x0000) // csi input enable & status register.
#define ADDR_REG_VCNT                      (ADDR_ISP_BASE + 0x0004) // input pixel counter register.
#define ADDR_REG_CSIINTS                   (ADDR_ISP_BASE + 0x0008) // Interrupt and Shadow 
#define ADDR_REG_FUNCTION_MODE             (ADDR_ISP_BASE + 0x0010) // csi module enable register.
#define ADDR_REG_SENSOR                    (ADDR_ISP_BASE + 0x0014) // input dvp format & signal polarity cfg.
#define ADDR_REG_CFA                       (ADDR_ISP_BASE + 0x0018) // input RAW format cfg.
#define ADDR_REG_CAPTURE_WINDOW_START      (ADDR_ISP_BASE + 0x001C) // input picture capture start cfg(x/y start location), each 16bit (cropping)
#define ADDR_REG_CAPTURE_WINDOW_END        (ADDR_ISP_BASE + 0x0020) // input picture capture end cfg(x/y end location), each 16bit (cropping)
#define ADDR_REG_DUMP_CFG_0                (ADDR_ISP_BASE + 0x0024) // base address for captured image
#define ADDR_REG_DUMP_CFG_1                (ADDR_ISP_BASE + 0x0028) // dump configuration
#define ADDR_REG_DEC_CFG                   (ADDR_ISP_BASE + 0x0030) // csi pipeline dec cfg register, Horizontal/Vertical period/keep, must set to odd 
#define ADDR_REG_OBC_CFG                   (ADDR_ISP_BASE + 0x0034) // OBC(Optical Black Compensation) window height(2^HEIGHT)/OBC window width(2^WIDTH),
#define ADDR_REG_DC_CFG_0                  (ADDR_ISP_BASE + 0x0040) // DC axi base address register
#define ADDR_REG_DC_CFG_1                  (ADDR_ISP_BASE + 0x0044) // DC axi id
#define ADDR_REG_LCCF_CFG_0                (ADDR_ISP_BASE + 0x0050) // X/Y distance from capture window(each 15bits)
#define ADDR_REG_LCCF_CFG_1                (ADDR_ISP_BASE + 0x0058) // LCCF maximum distance register
#define ADDR_REG_LCBQ_CFG_0                (ADDR_ISP_BASE + 0x0074) // LCBQ pseudo sub-window register
#define ADDR_REG_LCBQ_CFG_1                (ADDR_ISP_BASE + 0x007C) // LCBQ X/Y coordinate register
#define ADDR_REG_OBA_CFG_0                 (ADDR_ISP_BASE + 0x0090) // Vertical starting point/Horizontal ending point, each 16bits (black cropping)
#define ADDR_REG_OBA_CFG_1                 (ADDR_ISP_BASE + 0x0094) // Vertical ending point/Horizontal ending point, each 16bits
#define ADDR_REG_SCD_CFG_0                 (ADDR_ISP_BASE + 0x0098) // SC dumping base address 
#define ADDR_REG_SCD_CFG_1                 (ADDR_ISP_BASE + 0x009C) // SC dumping axi id
#define ADDR_REG_OBA_ACC_0                 (ADDR_ISP_BASE + 0x00A0) // OBA value for symbol 0
#define ADDR_REG_OBA_ACC_1                 (ADDR_ISP_BASE + 0x00A4) // OBA value for symbol 1
#define ADDR_REG_OBA_ACC_2                 (ADDR_ISP_BASE + 0x00A8) // OBA value for symbol 2
#define ADDR_REG_OBA_ACC_3                 (ADDR_ISP_BASE + 0x00AC) // OBA value for symbol 3
#define ADDR_REG_SC_CFG_0                  (ADDR_ISP_BASE + 0x00B8) // SC frame cropping for sc awb
#define ADDR_REG_SC_CFG_1                  (ADDR_ISP_BASE + 0x00BC) // SC cfg1 register
#define ADDR_REG_SC_AF                     (ADDR_ISP_BASE + 0x00C0) // SC AF register
#define ADDR_REG_SC_AWB_PS_CFG_0           (ADDR_ISP_BASE + 0x00C4) // SC AWB pixel sum registers0
#define ADDR_REG_SC_AWB_PS_CFG_1           (ADDR_ISP_BASE + 0x00C8) // SC AWB pixel sum registers1
#define ADDR_REG_SC_AWB_PS_CFG_2           (ADDR_ISP_BASE + 0x00CC) // SC AWB pixel sum registers2
#define ADDR_REG_SC_AWB_PS_CFG_3           (ADDR_ISP_BASE + 0x00D0) // SC AWB pixel sum registers3
#define ADDR_REG_SC_AWB_PS_CFG_4           (ADDR_ISP_BASE + 0x00D4) // SC AWB pixel sum registers4
#define ADDR_REG_SC_DEC                    (ADDR_ISP_BASE + 0x00D8) // sc0 dec cfg register for sc awb, Horizontal/Vertical period/keep
#define ADDR_REG_LCCF_CFG_2                (ADDR_ISP_BASE + 0x00E0) // LCCF F parameter for symbol 0 register
#define ADDR_REG_LCCF_CFG_3                (ADDR_ISP_BASE + 0x00E4) // LCCF F parameter for symbol 1 register
#define ADDR_REG_LCCF_CFG_4                (ADDR_ISP_BASE + 0x00E8) // LCCF F parameter for symbol 2 register
#define ADDR_REG_LCCF_CFG_5                (ADDR_ISP_BASE + 0x00EC) // LCCF F parameter for symbol 3 register
#define ADDR_REG_SCR_ADR                   (ADDR_ISP_BASE + 0x00F8) // SC read index
#define ADDR_REG_SCR_DAT                   (ADDR_ISP_BASE + 0x00FC) // SC read data
#define ADDR_REG_OECF_X0_CFG_0             (ADDR_ISP_BASE + 0x0100) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X0_CFG_1             (ADDR_ISP_BASE + 0x0104) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X0_CFG_2             (ADDR_ISP_BASE + 0x0108) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X0_CFG_3             (ADDR_ISP_BASE + 0x010C) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X0_CFG_4             (ADDR_ISP_BASE + 0x0110) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X0_CFG_5             (ADDR_ISP_BASE + 0x0114) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X0_CFG_6             (ADDR_ISP_BASE + 0x0118) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X0_CFG_7             (ADDR_ISP_BASE + 0x011C) // OECF X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_X1_CFG_0             (ADDR_ISP_BASE + 0x0120) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X1_CFG_1             (ADDR_ISP_BASE + 0x0124) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X1_CFG_2             (ADDR_ISP_BASE + 0x0128) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X1_CFG_3             (ADDR_ISP_BASE + 0x012C) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X1_CFG_4             (ADDR_ISP_BASE + 0x0130) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X1_CFG_5             (ADDR_ISP_BASE + 0x0134) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X1_CFG_6             (ADDR_ISP_BASE + 0x0138) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X1_CFG_7             (ADDR_ISP_BASE + 0x013C) // OECF X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_X2_CFG_0             (ADDR_ISP_BASE + 0x0140) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X2_CFG_1             (ADDR_ISP_BASE + 0x0144) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X2_CFG_2             (ADDR_ISP_BASE + 0x0148) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X2_CFG_3             (ADDR_ISP_BASE + 0x014C) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X2_CFG_4             (ADDR_ISP_BASE + 0x0150) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X2_CFG_5             (ADDR_ISP_BASE + 0x0154) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X2_CFG_6             (ADDR_ISP_BASE + 0x0158) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X2_CFG_7             (ADDR_ISP_BASE + 0x015C) // OECF X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_X3_CFG_0             (ADDR_ISP_BASE + 0x0160) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_X3_CFG_1             (ADDR_ISP_BASE + 0x0164) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_X3_CFG_2             (ADDR_ISP_BASE + 0x0168) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_X3_CFG_3             (ADDR_ISP_BASE + 0x016C) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_X3_CFG_4             (ADDR_ISP_BASE + 0x0170) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_X3_CFG_5             (ADDR_ISP_BASE + 0x0174) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_X3_CFG_6             (ADDR_ISP_BASE + 0x0178) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_X3_CFG_7             (ADDR_ISP_BASE + 0x017C) // OECF X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y0_CFG_0             (ADDR_ISP_BASE + 0x0180) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y0_CFG_1             (ADDR_ISP_BASE + 0x0184) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y0_CFG_2             (ADDR_ISP_BASE + 0x0188) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y0_CFG_3             (ADDR_ISP_BASE + 0x018C) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y0_CFG_4             (ADDR_ISP_BASE + 0x0190) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y0_CFG_5             (ADDR_ISP_BASE + 0x0194) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y0_CFG_6             (ADDR_ISP_BASE + 0x0198) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y0_CFG_7             (ADDR_ISP_BASE + 0x019C) // OECF Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECF_Y1_CFG_0             (ADDR_ISP_BASE + 0x01A0) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y1_CFG_1             (ADDR_ISP_BASE + 0x01A4) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y1_CFG_2             (ADDR_ISP_BASE + 0x01A8) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y1_CFG_3             (ADDR_ISP_BASE + 0x01AC) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y1_CFG_4             (ADDR_ISP_BASE + 0x01B0) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y1_CFG_5             (ADDR_ISP_BASE + 0x01B4) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y1_CFG_6             (ADDR_ISP_BASE + 0x01B8) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y1_CFG_7             (ADDR_ISP_BASE + 0x01BC) // OECF Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECF_Y2_CFG_0             (ADDR_ISP_BASE + 0x01C0) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y2_CFG_1             (ADDR_ISP_BASE + 0x01C4) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y2_CFG_2             (ADDR_ISP_BASE + 0x01C8) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y2_CFG_3             (ADDR_ISP_BASE + 0x01CC) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y2_CFG_4             (ADDR_ISP_BASE + 0x01D0) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y2_CFG_5             (ADDR_ISP_BASE + 0x01D4) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y2_CFG_6             (ADDR_ISP_BASE + 0x01D8) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y2_CFG_7             (ADDR_ISP_BASE + 0x01DC) // OECF Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECF_Y3_CFG_0             (ADDR_ISP_BASE + 0x01E0) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y3_CFG_1             (ADDR_ISP_BASE + 0x01E4) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y3_CFG_2             (ADDR_ISP_BASE + 0x01E8) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y3_CFG_3             (ADDR_ISP_BASE + 0x01EC) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y3_CFG_4             (ADDR_ISP_BASE + 0x01F0) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y3_CFG_5             (ADDR_ISP_BASE + 0x01F4) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y3_CFG_6             (ADDR_ISP_BASE + 0x01F8) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_Y3_CFG_7             (ADDR_ISP_BASE + 0x01FC) // OECF Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECF_S0_CFG_0             (ADDR_ISP_BASE + 0x0200) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S0_CFG_1             (ADDR_ISP_BASE + 0x0204) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S0_CFG_2             (ADDR_ISP_BASE + 0x0208) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S0_CFG_3             (ADDR_ISP_BASE + 0x020C) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S0_CFG_4             (ADDR_ISP_BASE + 0x0210) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S0_CFG_5             (ADDR_ISP_BASE + 0x0214) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S0_CFG_6             (ADDR_ISP_BASE + 0x0218) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S0_CFG_7             (ADDR_ISP_BASE + 0x021C) // OECF [0.3.7] S parameter register for symbol 0 
#define ADDR_REG_OECF_S1_CFG_0             (ADDR_ISP_BASE + 0x0220) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S1_CFG_1             (ADDR_ISP_BASE + 0x0224) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S1_CFG_2             (ADDR_ISP_BASE + 0x0228) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S1_CFG_3             (ADDR_ISP_BASE + 0x022C) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S1_CFG_4             (ADDR_ISP_BASE + 0x0230) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S1_CFG_5             (ADDR_ISP_BASE + 0x0234) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S1_CFG_6             (ADDR_ISP_BASE + 0x0238) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S1_CFG_7             (ADDR_ISP_BASE + 0x023C) // OECF [0.3.7] S parameter register for symbol 1 
#define ADDR_REG_OECF_S2_CFG_0             (ADDR_ISP_BASE + 0x0240) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S2_CFG_1             (ADDR_ISP_BASE + 0x0244) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S2_CFG_2             (ADDR_ISP_BASE + 0x0248) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S2_CFG_3             (ADDR_ISP_BASE + 0x024C) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S2_CFG_4             (ADDR_ISP_BASE + 0x0250) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S2_CFG_5             (ADDR_ISP_BASE + 0x0254) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S2_CFG_6             (ADDR_ISP_BASE + 0x0258) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S2_CFG_7             (ADDR_ISP_BASE + 0x025C) // OECF [0.3.7] S parameter register for symbol 2 
#define ADDR_REG_OECF_S3_CFG_0             (ADDR_ISP_BASE + 0x0260) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_OECF_S3_CFG_1             (ADDR_ISP_BASE + 0x0264) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_OECF_S3_CFG_2             (ADDR_ISP_BASE + 0x0268) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_OECF_S3_CFG_3             (ADDR_ISP_BASE + 0x026C) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_OECF_S3_CFG_4             (ADDR_ISP_BASE + 0x0270) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_OECF_S3_CFG_5             (ADDR_ISP_BASE + 0x0274) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_OECF_S3_CFG_6             (ADDR_ISP_BASE + 0x0278) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_OECF_S3_CFG_7             (ADDR_ISP_BASE + 0x027C) // OECF [0.3.7] S parameter register for symbol 3 
#define ADDR_REG_AWB_X0_CFG_0              (ADDR_ISP_BASE + 0x0280) // X0/X1 for symbol 0, each 10bits
#define ADDR_REG_AWB_X0_CFG_1              (ADDR_ISP_BASE + 0x0284) // X2/X3 for symbol 0, each 10bits
#define ADDR_REG_AWB_X1_CFG_0              (ADDR_ISP_BASE + 0x0288) // X0/X1 for symbol 1, each 10bits
#define ADDR_REG_AWB_X1_CFG_1              (ADDR_ISP_BASE + 0x028C) // X2/X3 for symbol 1, each 10bits
#define ADDR_REG_AWB_X2_CFG_0              (ADDR_ISP_BASE + 0x0290) // X0/X1 for symbol 2, each 10bits
#define ADDR_REG_AWB_X2_CFG_1              (ADDR_ISP_BASE + 0x0294) // X2/X3 for symbol 2, each 10bits
#define ADDR_REG_AWB_X3_CFG_0              (ADDR_ISP_BASE + 0x0298) // X0/X1 for symbol 3, each 10bits
#define ADDR_REG_AWB_X3_CFG_1              (ADDR_ISP_BASE + 0x029C) // X2/X3 for symbol 3, each 10bits
#define ADDR_REG_AWB_Y0_CFG_0              (ADDR_ISP_BASE + 0x02A0) // Y0/Y1 for symbol 0, each 10bits
#define ADDR_REG_AWB_Y0_CFG_1              (ADDR_ISP_BASE + 0x02A4) // Y2/Y3 for symbol 0, each 10bits
#define ADDR_REG_AWB_Y1_CFG_0              (ADDR_ISP_BASE + 0x02A8) // Y0/Y1 for symbol 1, each 10bits
#define ADDR_REG_AWB_Y1_CFG_1              (ADDR_ISP_BASE + 0x02AC) // Y2/Y3 for symbol 1, each 10bits
#define ADDR_REG_AWB_Y2_CFG_0              (ADDR_ISP_BASE + 0x02B0) // Y0/Y1 for symbol 2, each 10bits
#define ADDR_REG_AWB_Y2_CFG_1              (ADDR_ISP_BASE + 0x02B4) // Y2/Y3 for symbol 2, each 10bits
#define ADDR_REG_AWB_Y3_CFG_0              (ADDR_ISP_BASE + 0x02B8) // Y0/Y1 for symbol 3, each 10bits
#define ADDR_REG_AWB_Y3_CFG_1              (ADDR_ISP_BASE + 0x02BC) // Y2/Y3 for symbol 3, each 10bits
#define ADDR_REG_AWB_S0_CFG_0              (ADDR_ISP_BASE + 0x02C0) // [0.3.7] S0/S1 for symbol 0, each 10bits
#define ADDR_REG_AWB_S0_CFG_1              (ADDR_ISP_BASE + 0x02C4) // [0.3.7] S2/S3 for symbol 0, each 10bits
#define ADDR_REG_AWB_S1_CFG_0              (ADDR_ISP_BASE + 0x02C8) // [0.3.7] S0/S1 for symbol 1, each 10bits
#define ADDR_REG_AWB_S1_CFG_1              (ADDR_ISP_BASE + 0x02CC) // [0.3.7] S2/S3 for symbol 1, each 10bits
#define ADDR_REG_AWB_S2_CFG_0              (ADDR_ISP_BASE + 0x02D0) // [0.3.7] S0/S1 for symbol 2, each 10bits
#define ADDR_REG_AWB_S2_CFG_1              (ADDR_ISP_BASE + 0x02D4) // [0.3.7] S2/S3 for symbol 2, each 10bits
#define ADDR_REG_AWB_S3_CFG_0              (ADDR_ISP_BASE + 0x02D8) // [0.3.7] S0/S1 for symbol 3, each 10bits
#define ADDR_REG_AWB_S3_CFG_1              (ADDR_ISP_BASE + 0x02DC) // [0.3.7] S2/S3 for symbol 3, each 10bits
#define ADDR_REG_OBCG_CFG_0                (ADDR_ISP_BASE + 0x02E0) // each symbol has four point, each point has one 8bit gain register
#define ADDR_REG_OBCG_CFG_1                (ADDR_ISP_BASE + 0x02E4) // each symbol has four point, each point has one 8bit gain register
#define ADDR_REG_OBCG_CFG_2                (ADDR_ISP_BASE + 0x02E8) // each symbol has four point, each point has one 8bit gain register
#define ADDR_REG_OBCG_CFG_3                (ADDR_ISP_BASE + 0x02EC) // each symbol has four point, each point has one 8bit gain register
#define ADDR_REG_OBCO_CFG_0                (ADDR_ISP_BASE + 0x02F0) // each symbol has four points
#define ADDR_REG_OBCO_CFG_1                (ADDR_ISP_BASE + 0x02F4) // each symbol has four points
#define ADDR_REG_OBCO_CFG_2                (ADDR_ISP_BASE + 0x02F8) // each symbol has four points
#define ADDR_REG_OBCO_CFG_3                (ADDR_ISP_BASE + 0x02FC) // each symbol has four points
#define ADDR_REG_LCBQ_GAIN0_CFG_0          (ADDR_ISP_BASE + 0x0300) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_1          (ADDR_ISP_BASE + 0x0304) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_2          (ADDR_ISP_BASE + 0x0308) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_3          (ADDR_ISP_BASE + 0x030C) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_4          (ADDR_ISP_BASE + 0x0310) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_5          (ADDR_ISP_BASE + 0x0314) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_6          (ADDR_ISP_BASE + 0x0318) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_7          (ADDR_ISP_BASE + 0x031C) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_8          (ADDR_ISP_BASE + 0x0320) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_9          (ADDR_ISP_BASE + 0x0324) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_10         (ADDR_ISP_BASE + 0x0328) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_11         (ADDR_ISP_BASE + 0x032C) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN0_CFG_12         (ADDR_ISP_BASE + 0x0330) // LCBQ [0.1.8] Gain parameter register for symbol 0 
#define ADDR_REG_LCBQ_GAIN1_CFG_0          (ADDR_ISP_BASE + 0x0334) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_1          (ADDR_ISP_BASE + 0x0338) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_2          (ADDR_ISP_BASE + 0x033C) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_3          (ADDR_ISP_BASE + 0x0340) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_4          (ADDR_ISP_BASE + 0x0344) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_5          (ADDR_ISP_BASE + 0x0348) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_6          (ADDR_ISP_BASE + 0x034C) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_7          (ADDR_ISP_BASE + 0x0350) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_8          (ADDR_ISP_BASE + 0x0354) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_9          (ADDR_ISP_BASE + 0x0358) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_10         (ADDR_ISP_BASE + 0x035C) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_11         (ADDR_ISP_BASE + 0x0360) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN1_CFG_12         (ADDR_ISP_BASE + 0x0364) // LCBQ [0.1.8] Gain parameter register for symbol 1 
#define ADDR_REG_LCBQ_GAIN2_CFG_0          (ADDR_ISP_BASE + 0x0368) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_1          (ADDR_ISP_BASE + 0x036C) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_2          (ADDR_ISP_BASE + 0x0370) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_3          (ADDR_ISP_BASE + 0x0374) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_4          (ADDR_ISP_BASE + 0x0378) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_5          (ADDR_ISP_BASE + 0x037C) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_6          (ADDR_ISP_BASE + 0x0380) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_7          (ADDR_ISP_BASE + 0x0384) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_8          (ADDR_ISP_BASE + 0x0388) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_9          (ADDR_ISP_BASE + 0x038C) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_10         (ADDR_ISP_BASE + 0x0390) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_11         (ADDR_ISP_BASE + 0x0394) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN2_CFG_12         (ADDR_ISP_BASE + 0x0398) // LCBQ [0.1.8] Gain parameter register for symbol 2 
#define ADDR_REG_LCBQ_GAIN3_CFG_0          (ADDR_ISP_BASE + 0x039C) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_1          (ADDR_ISP_BASE + 0x03A0) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_2          (ADDR_ISP_BASE + 0x03A4) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_3          (ADDR_ISP_BASE + 0x03A8) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_4          (ADDR_ISP_BASE + 0x03AC) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_5          (ADDR_ISP_BASE + 0x03B0) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_6          (ADDR_ISP_BASE + 0x03B4) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_7          (ADDR_ISP_BASE + 0x03B8) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_8          (ADDR_ISP_BASE + 0x03BC) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_9          (ADDR_ISP_BASE + 0x03C0) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_10         (ADDR_ISP_BASE + 0x03C4) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_11         (ADDR_ISP_BASE + 0x03C8) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_LCBQ_GAIN3_CFG_12         (ADDR_ISP_BASE + 0x03CC) // LCBQ [0.1.8] Gain parameter register for symbol 3 
#define ADDR_REG_OECFHM_Y_CFG_0            (ADDR_ISP_BASE + 0x03D0) // OECF Hermite
#define ADDR_REG_OECFHM_Y_CFG_1            (ADDR_ISP_BASE + 0x03D4) // OECF Hermite
#define ADDR_REG_OECFHM_Y_CFG_2            (ADDR_ISP_BASE + 0x03D8) // OECF Hermite
#define ADDR_REG_OECFHM_S_CFG_0            (ADDR_ISP_BASE + 0x03DC) // OECF Hermite
#define ADDR_REG_OECFHM_S_CFG_1            (ADDR_ISP_BASE + 0x03E0) // OECF Hermite
#define ADDR_REG_OECFHM_S_CFG_2            (ADDR_ISP_BASE + 0x03E4) // OECF Hermite
#define ADDR_REG_LCBQ_OFFSET0_CFG_0        (ADDR_ISP_BASE + 0x0400) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_1        (ADDR_ISP_BASE + 0x0404) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_2        (ADDR_ISP_BASE + 0x0408) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_3        (ADDR_ISP_BASE + 0x040C) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_4        (ADDR_ISP_BASE + 0x0410) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_5        (ADDR_ISP_BASE + 0x0414) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_6        (ADDR_ISP_BASE + 0x0418) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_7        (ADDR_ISP_BASE + 0x041C) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_8        (ADDR_ISP_BASE + 0x0420) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_9        (ADDR_ISP_BASE + 0x0424) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_10       (ADDR_ISP_BASE + 0x0428) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_11       (ADDR_ISP_BASE + 0x042C) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET0_CFG_12       (ADDR_ISP_BASE + 0x0430) // LCBQ [1.8.0] Offset parameter register for symbol 0 
#define ADDR_REG_LCBQ_OFFSET1_CFG_0        (ADDR_ISP_BASE + 0x0434) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_1        (ADDR_ISP_BASE + 0x0438) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_2        (ADDR_ISP_BASE + 0x043C) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_3        (ADDR_ISP_BASE + 0x0440) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_4        (ADDR_ISP_BASE + 0x0444) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_5        (ADDR_ISP_BASE + 0x0448) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_6        (ADDR_ISP_BASE + 0x044C) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_7        (ADDR_ISP_BASE + 0x0450) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_8        (ADDR_ISP_BASE + 0x0454) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_9        (ADDR_ISP_BASE + 0x0458) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_10       (ADDR_ISP_BASE + 0x045C) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_11       (ADDR_ISP_BASE + 0x0460) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET1_CFG_12       (ADDR_ISP_BASE + 0x0464) // LCBQ [1.8.0] Offset parameter register for symbol 1 
#define ADDR_REG_LCBQ_OFFSET2_CFG_0        (ADDR_ISP_BASE + 0x0468) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_1        (ADDR_ISP_BASE + 0x046C) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_2        (ADDR_ISP_BASE + 0x0470) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_3        (ADDR_ISP_BASE + 0x0474) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_4        (ADDR_ISP_BASE + 0x0478) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_5        (ADDR_ISP_BASE + 0x047C) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_6        (ADDR_ISP_BASE + 0x0480) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_7        (ADDR_ISP_BASE + 0x0484) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_8        (ADDR_ISP_BASE + 0x0488) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_9        (ADDR_ISP_BASE + 0x048C) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_10       (ADDR_ISP_BASE + 0x0490) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_11       (ADDR_ISP_BASE + 0x0494) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET2_CFG_12       (ADDR_ISP_BASE + 0x0498) // LCBQ [1.8.0] Offset parameter register for symbol 2 
#define ADDR_REG_LCBQ_OFFSET3_CFG_0        (ADDR_ISP_BASE + 0x049C) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_1        (ADDR_ISP_BASE + 0x04A0) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_2        (ADDR_ISP_BASE + 0x04A4) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_3        (ADDR_ISP_BASE + 0x04A8) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_4        (ADDR_ISP_BASE + 0x04AC) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_5        (ADDR_ISP_BASE + 0x04B0) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_6        (ADDR_ISP_BASE + 0x04B4) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_7        (ADDR_ISP_BASE + 0x04B8) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_8        (ADDR_ISP_BASE + 0x04BC) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_9        (ADDR_ISP_BASE + 0x04C0) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_10       (ADDR_ISP_BASE + 0x04C4) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_11       (ADDR_ISP_BASE + 0x04C8) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_LCBQ_OFFSET3_CFG_12       (ADDR_ISP_BASE + 0x04CC) // LCBQ [1.8.0] Offset parameter register for symbol 3 
#define ADDR_REG_SC_AWB_WS_CW0_CFG_0       (ADDR_ISP_BASE + 0x04D0) // Weighting value at point(0,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW0_CFG_1       (ADDR_ISP_BASE + 0x04D4) // Weighting value at point(0,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW1_CFG_0       (ADDR_ISP_BASE + 0x04D8) // Weighting value at point(1,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW1_CFG_1       (ADDR_ISP_BASE + 0x04DC) // Weighting value at point(1,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW2_CFG_0       (ADDR_ISP_BASE + 0x04E0) // Weighting value at point(2,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW2_CFG_1       (ADDR_ISP_BASE + 0x04E4) // Weighting value at point(2,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW3_CFG_0       (ADDR_ISP_BASE + 0x04E8) // Weighting value at point(3,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW3_CFG_1       (ADDR_ISP_BASE + 0x04EC) // Weighting value at point(3,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW4_CFG_0       (ADDR_ISP_BASE + 0x04F0) // Weighting value at point(4,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW4_CFG_1       (ADDR_ISP_BASE + 0x04F4) // Weighting value at point(4,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW5_CFG_0       (ADDR_ISP_BASE + 0x04F8) // Weighting value at point(5,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW5_CFG_1       (ADDR_ISP_BASE + 0x04FC) // Weighting value at point(5,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW6_CFG_0       (ADDR_ISP_BASE + 0x0500) // Weighting value at point(6,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW6_CFG_1       (ADDR_ISP_BASE + 0x0504) // Weighting value at point(6,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW7_CFG_0       (ADDR_ISP_BASE + 0x0508) // Weighting value at point(7,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW7_CFG_1       (ADDR_ISP_BASE + 0x050C) // Weighting value at point(7,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW8_CFG_0       (ADDR_ISP_BASE + 0x0510) // Weighting value at point(8,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW8_CFG_1       (ADDR_ISP_BASE + 0x0514) // Weighting value at point(8,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW9_CFG_0       (ADDR_ISP_BASE + 0x0518) // Weighting value at point(9,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW9_CFG_1       (ADDR_ISP_BASE + 0x051C) // Weighting value at point(9,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW10_CFG_0      (ADDR_ISP_BASE + 0x0520) // Weighting value at point(10,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW10_CFG_1      (ADDR_ISP_BASE + 0x0524) // Weighting value at point(10,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW11_CFG_0      (ADDR_ISP_BASE + 0x0528) // Weighting value at point(11,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW11_CFG_1      (ADDR_ISP_BASE + 0x052C) // Weighting value at point(11,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_CW12_CFG_0      (ADDR_ISP_BASE + 0x0530) // Weighting value at point(12,0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_CW12_CFG_1      (ADDR_ISP_BASE + 0x0534) // Weighting value at point(12,8~12), each 4bits
#define ADDR_REG_SC_AWB_WS_IWV_CFG_0       (ADDR_ISP_BASE + 0x0538) // Weighting value at point(0~7), each 4bits
#define ADDR_REG_SC_AWB_WS_IWV_CFG_1       (ADDR_ISP_BASE + 0x053C) // Weighting value at point(8~15), each 4bits
#define ADDR_REG_SC_AWB_WS_IWS_CFG_0       (ADDR_ISP_BASE + 0x0540) // Slope value at point(0~3), each 8bits
#define ADDR_REG_SC_AWB_WS_IWS_CFG_1       (ADDR_ISP_BASE + 0x0544) // Slope value at point(4~7), each 8bits
#define ADDR_REG_SC_AWB_WS_IWS_CFG_2       (ADDR_ISP_BASE + 0x0548) // Slope value at point(8~11), each 8bits
#define ADDR_REG_SC_AWB_WS_IWS_CFG_3       (ADDR_ISP_BASE + 0x054C) // Slope value at point(12~15), each 8bits
#define ADDR_REG_SC_AWB_WS_CFG_0           (ADDR_ISP_BASE + 0x05D0) // SC AWB weight sum registers0
#define ADDR_REG_SC_AWB_WS_CFG_1           (ADDR_ISP_BASE + 0x05D4) // SC AWB weight sum registers1
#define ADDR_REG_CSICBFS                   (ADDR_ISP_BASE + 0x0600) // Color Bar Frame Size
#define ADDR_REG_CSICBS                    (ADDR_ISP_BASE + 0x0604) // Color Bar Frame Start
#define ADDR_REG_CSICBE                    (ADDR_ISP_BASE + 0x0608) // Color Bar Frame End
#define ADDR_REG_CSICBMD0                  (ADDR_ISP_BASE + 0x060C) // Color Bar Mode 0
#define ADDR_REG_CSICBMD1                  (ADDR_ISP_BASE + 0x0610) // Color Bar Mode 1
#define ADDR_REG_CSICBP01                  (ADDR_ISP_BASE + 0x0614) // Color Bar Pixel 01
#define ADDR_REG_CSICBP23                  (ADDR_ISP_BASE + 0x0618) // Color Bar Pixel 23
#define ADDR_REG_CSICBP45                  (ADDR_ISP_BASE + 0x061C) // Color Bar Pixel 45
#define ADDR_REG_CSICBP67                  (ADDR_ISP_BASE + 0x0620) // Color Bar Pixel 67
#define ADDR_REG_CSICBP89                  (ADDR_ISP_BASE + 0x0624) // Color Bar Pixel 89
#define ADDR_REG_CSICBPAB                  (ADDR_ISP_BASE + 0x0628) // Color Bar Pixel AB
#define ADDR_REG_CSICBPCD                  (ADDR_ISP_BASE + 0x062C) // Color Bar Pixel CD
#define ADDR_REG_CSICBPEF                  (ADDR_ISP_BASE + 0x0630) // Color Bar Pixel EF
#define ADDR_REG_CSICBL1P01                (ADDR_ISP_BASE + 0x0634) // Color Bar Line 1 Pixel 01
#define ADDR_REG_CSICBL1P23                (ADDR_ISP_BASE + 0x0638) // Color Bar Line 1 Pixel 23
#define ADDR_REG_CSICBL1P45                (ADDR_ISP_BASE + 0x063C) // Color Bar Line 1 Pixel 45
#define ADDR_REG_CSICBL1P67                (ADDR_ISP_BASE + 0x0640) // Color Bar Line 1 Pixel 67
#define ADDR_REG_CSICBL1P89                (ADDR_ISP_BASE + 0x0644) // Color Bar Line 1 Pixel 89
#define ADDR_REG_CSICBL1PAB                (ADDR_ISP_BASE + 0x0648) // Color Bar Line 1 Pixel AB
#define ADDR_REG_CSICBL1PCD                (ADDR_ISP_BASE + 0x064C) // Color Bar Line 1 Pixel CD
#define ADDR_REG_CSICBL1PEF                (ADDR_ISP_BASE + 0x0650) // Color Bar Line 1 Pixel EF
#define ADDR_REG_ISPCTRL0                  (ADDR_ISP_BASE + 0x0A00) // ISP Control Register 0
#define ADDR_REG_ISPSTAT0                  (ADDR_ISP_BASE + 0x0A04) // ISP status
#define ADDR_REG_ISPCTRL1                  (ADDR_ISP_BASE + 0x0A08) // ISP Control Register 1
#define ADDR_REG_IFSZ                      (ADDR_ISP_BASE + 0x0A0C) // isp pipeline X/Y size, each 13bits(after decimation)
#define ADDR_REG_ICTC                      (ADDR_ISP_BASE + 0x0A10) // GrGb Filter threshold 1 Register
#define ADDR_REG_IDBC                      (ADDR_ISP_BASE + 0x0A14) // GrGb filter threshold 2 Register
#define ADDR_REG_ICFAM                     (ADDR_ISP_BASE + 0x0A1C) // CFA Mode Register
#define ADDR_REG_ISAT0                     (ADDR_ISP_BASE + 0x0A30) // Chroma Saturation Gain
#define ADDR_REG_ISAT1                     (ADDR_ISP_BASE + 0x0A34) // Chroma Saturation Threshold
#define ADDR_REG_ISAT2                     (ADDR_ISP_BASE + 0x0A38) // Chroma Saturation UV Offset
#define ADDR_REG_ISAT3                     (ADDR_ISP_BASE + 0x0A3C) // Chroma Saturation Hue Factor 
#define ADDR_REG_ISAT4                     (ADDR_ISP_BASE + 0x0A40) // Chroma Saturation scaling coefficient
#define ADDR_REG_IESHD                     (ADDR_ISP_BASE + 0x0A50) // Image engine shadow control Register
#define ADDR_REG_IYADJ0                    (ADDR_ISP_BASE + 0x0A54) // Y Adjustment Register 0
#define ADDR_REG_IYADJ1                    (ADDR_ISP_BASE + 0x0A58) // Y Adjustment Register 1
#define ADDR_REG_UOAY                      (ADDR_ISP_BASE + 0x0A80) // Unscaled Output Image Y Plane Start Address Register
#define ADDR_REG_UOAUV                     (ADDR_ISP_BASE + 0x0A84) // Unscaled Output Image UV Plane Start Address Register
#define ADDR_REG_UOS                       (ADDR_ISP_BASE + 0x0A88) // Unscaled Output Image Stride Register
#define ADDR_REG_UOPGM                     (ADDR_ISP_BASE + 0x0A8C) // Unscaled Output Pixel Coordinate Generator Mode Register
#define ADDR_REG_UOAXI                     (ADDR_ISP_BASE + 0x0A90) // Unscaled Output AXI Control Register
#define ADDR_REG_SS0AY                     (ADDR_ISP_BASE + 0x0A94) // SS0 Output Image Y Plane Start Address Register
#define ADDR_REG_SS0AUV                    (ADDR_ISP_BASE + 0x0A98) // SS0 Output Image UV Plane Start Address Register
#define ADDR_REG_SS0S                      (ADDR_ISP_BASE + 0x0A9C) // SS0 Output Image Stride Register
#define ADDR_REG_SS0HF                     (ADDR_ISP_BASE + 0x0AA0) // SS0 H Scaling Factor Register
#define ADDR_REG_SS0VF                     (ADDR_ISP_BASE + 0x0AA4) // SS0 V Scaling Factor Register
#define ADDR_REG_SS0IW                     (ADDR_ISP_BASE + 0x0AA8) // SS0 Output Image Size Register
#define ADDR_REG_SS1AY                     (ADDR_ISP_BASE + 0x0AAC) // SS1 Output Image Y Plane Start Address Register
#define ADDR_REG_SS1AUV                    (ADDR_ISP_BASE + 0x0AB0) // SS1 Output Image UV Plane Start Address Register
#define ADDR_REG_SS1S                      (ADDR_ISP_BASE + 0x0AB4) // SS1 Output Image Stride Register
#define ADDR_REG_SS1HF                     (ADDR_ISP_BASE + 0x0AB8) // SS1 H Scaling Factor Register
#define ADDR_REG_SS1VF                     (ADDR_ISP_BASE + 0x0ABC) // SS1 V Scaling Factor Register
#define ADDR_REG_SS1IW                     (ADDR_ISP_BASE + 0x0AC0) // SS1 Output Image Size Register
#define ADDR_REG_SSAXI                     (ADDR_ISP_BASE + 0x0AC4) // SS AXI Control Register
#define ADDR_REG_ITIIWSR                   (ADDR_ISP_BASE + 0x0B20) // ITI image window size register
#define ADDR_REG_ITIDWLSR                  (ADDR_ISP_BASE + 0x0B24) // ITI DRAM write line stride register
#define ADDR_REG_ITIDWYSAR                 (ADDR_ISP_BASE + 0x0B28) // ITI DRAM write Y start address register
#define ADDR_REG_ITIDWUSAR                 (ADDR_ISP_BASE + 0x0B2C) // ITI DRAM write UV start address register
#define ADDR_REG_ITIDRYSAR                 (ADDR_ISP_BASE + 0x0B30) // ITI DRAM read Y start address register
#define ADDR_REG_ITIDRUSAR                 (ADDR_ISP_BASE + 0x0B34) // ITI DRAM read UV start address register
#define ADDR_REG_ITIPDFR                   (ADDR_ISP_BASE + 0x0B38) // ITI package data format register
#define ADDR_REG_ITIDRLSR                  (ADDR_ISP_BASE + 0x0B3C) // ITI DRAM read line stride register
#define ADDR_REG_ITIBSR                    (ADDR_ISP_BASE + 0x0B40) // ISP tiling interface BUSY status register
#define ADDR_REG_ITIAIR                    (ADDR_ISP_BASE + 0x0B44) // ISP tiling interface AXI ID register
#define ADDR_REG_ITIDPSR                   (ADDR_ISP_BASE + 0x0B48) // ISP tiling interface data path select register
#define ADDR_REG_DNYUV_YSWR0               (ADDR_ISP_BASE + 0x0C00) // DNYUV Y channel S weight table register 0
#define ADDR_REG_DNYUV_YSWR1               (ADDR_ISP_BASE + 0x0C04) // DNYUV Y channel S weight table register 1
#define ADDR_REG_DNYUV_CSWR0               (ADDR_ISP_BASE + 0x0C08) // DNYUV UV channel S weight table register 0
#define ADDR_REG_DNYUV_CSWR1               (ADDR_ISP_BASE + 0x0C0C) // DNYUV UV channel S weight table register  1
#define ADDR_REG_DNYUV_YDR0                (ADDR_ISP_BASE + 0x0C10) // DNYUV Y Curve D component register 0
#define ADDR_REG_DNYUV_YDR1                (ADDR_ISP_BASE + 0x0C14) // DNYUV Y Curve D component register 1
#define ADDR_REG_DNYUV_YDR2                (ADDR_ISP_BASE + 0x0C18) // DNYUV Y Curve D component register 2
#define ADDR_REG_DNYUV_CDR0                (ADDR_ISP_BASE + 0x0C1C) // DNYUV UV Curve D component register 0
#define ADDR_REG_DNYUV_CDR1                (ADDR_ISP_BASE + 0x0C20) // DNYUV UV Curve D component register 1
#define ADDR_REG_DNYUV_CDR2                (ADDR_ISP_BASE + 0x0C24) // DNYUV UV Curve D component register 2
#define ADDR_REG_ICAMD_0                   (ADDR_ISP_BASE + 0x0C40) // Color correction matrix register
#define ADDR_REG_ICAMD_1                   (ADDR_ISP_BASE + 0x0C44) // Color correction matrix Register 
#define ADDR_REG_ICAMD_2                   (ADDR_ISP_BASE + 0x0C48) // Color correction matrix Register 
#define ADDR_REG_ICAMD_3                   (ADDR_ISP_BASE + 0x0C4C) // Color correction matrix Register 
#define ADDR_REG_ICAMD_4                   (ADDR_ISP_BASE + 0x0C50) // Color correction matrix Register 
#define ADDR_REG_ICAMD_5                   (ADDR_ISP_BASE + 0x0C54) // Color correction matrix Register 
#define ADDR_REG_ICAMD_6                   (ADDR_ISP_BASE + 0x0C58) // Color correction matrix Register 
#define ADDR_REG_ICAMD_7                   (ADDR_ISP_BASE + 0x0C5C) // Color correction matrix Register 
#define ADDR_REG_ICAMD_8                   (ADDR_ISP_BASE + 0x0C60) // Color correction matrix Register 
#define ADDR_REG_ICAMD_9                   (ADDR_ISP_BASE + 0x0C64) // Color correction matrix Register 
#define ADDR_REG_ICAMD_10                  (ADDR_ISP_BASE + 0x0C68) // Color correction matrix Register 
#define ADDR_REG_ICAMD_11                  (ADDR_ISP_BASE + 0x0C6C) // Color correction matrix Register 
#define ADDR_REG_ICAMD_12                  (ADDR_ISP_BASE + 0x0C70) // Color correction matrix Register 
#define ADDR_REG_ICAMD_13                  (ADDR_ISP_BASE + 0x0C74) // Color correction matrix Register 
#define ADDR_REG_ICAMD_14                  (ADDR_ISP_BASE + 0x0C78) // Color correction matrix Register 
#define ADDR_REG_ICAMD_15                  (ADDR_ISP_BASE + 0x0C7C) // Color correction matrix Register 
#define ADDR_REG_ICAMD_16                  (ADDR_ISP_BASE + 0x0C80) // Color correction matrix Register 
#define ADDR_REG_ICAMD_17                  (ADDR_ISP_BASE + 0x0C84) // Color correction matrix Register 
#define ADDR_REG_ICAMD_18                  (ADDR_ISP_BASE + 0x0C88) // Color correction matrix Register 
#define ADDR_REG_ICAMD_19                  (ADDR_ISP_BASE + 0x0C8C) // Color correction matrix Register 
#define ADDR_REG_ICAMD_20                  (ADDR_ISP_BASE + 0x0C90) // Color correction matrix Register 
#define ADDR_REG_ICAMD_21                  (ADDR_ISP_BASE + 0x0C94) // Color correction matrix Register 
#define ADDR_REG_ICAMD_22                  (ADDR_ISP_BASE + 0x0C98) // Color correction matrix Register 
#define ADDR_REG_ICAMD_23                  (ADDR_ISP_BASE + 0x0C9C) // Color correction matrix Register 
#define ADDR_REG_ICAMD_24                  (ADDR_ISP_BASE + 0x0CA0) // Color correction matrix Register 24, dth
#define ADDR_REG_ICAMD_25                  (ADDR_ISP_BASE + 0x0CA4) // Color correction matrix Register 25, th1
#define ADDR_REG_YHIST_CFG_0               (ADDR_ISP_BASE + 0x0CC8) // Y Histogram Start Location Register
#define ADDR_REG_YHIST_CFG_1               (ADDR_ISP_BASE + 0x0CCC) // Y Histogram Size Register
#define ADDR_REG_YHIST_CFG_2               (ADDR_ISP_BASE + 0x0CD0) // Y Histogram Decimation Register
#define ADDR_REG_YHIST_CFG_3               (ADDR_ISP_BASE + 0x0CD4) // Y Histogram mux select register
#define ADDR_REG_YHIST_CFG_4               (ADDR_ISP_BASE + 0x0CD8) // Y histogram dumping base address 
#define ADDR_REG_YHIST_ACC_0               (ADDR_ISP_BASE + 0x0D00) // Y Histogram result register 0
#define ADDR_REG_YHIST_ACC_1               (ADDR_ISP_BASE + 0x0D04) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_2               (ADDR_ISP_BASE + 0x0D08) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_3               (ADDR_ISP_BASE + 0x0D0C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_4               (ADDR_ISP_BASE + 0x0D10) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_5               (ADDR_ISP_BASE + 0x0D14) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_6               (ADDR_ISP_BASE + 0x0D18) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_7               (ADDR_ISP_BASE + 0x0D1C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_8               (ADDR_ISP_BASE + 0x0D20) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_9               (ADDR_ISP_BASE + 0x0D24) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_10              (ADDR_ISP_BASE + 0x0D28) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_11              (ADDR_ISP_BASE + 0x0D2C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_12              (ADDR_ISP_BASE + 0x0D30) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_13              (ADDR_ISP_BASE + 0x0D34) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_14              (ADDR_ISP_BASE + 0x0D38) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_15              (ADDR_ISP_BASE + 0x0D3C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_16              (ADDR_ISP_BASE + 0x0D40) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_17              (ADDR_ISP_BASE + 0x0D44) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_18              (ADDR_ISP_BASE + 0x0D48) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_19              (ADDR_ISP_BASE + 0x0D4C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_20              (ADDR_ISP_BASE + 0x0D50) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_21              (ADDR_ISP_BASE + 0x0D54) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_22              (ADDR_ISP_BASE + 0x0D58) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_23              (ADDR_ISP_BASE + 0x0D5C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_24              (ADDR_ISP_BASE + 0x0D60) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_25              (ADDR_ISP_BASE + 0x0D64) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_26              (ADDR_ISP_BASE + 0x0D68) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_27              (ADDR_ISP_BASE + 0x0D6C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_28              (ADDR_ISP_BASE + 0x0D70) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_29              (ADDR_ISP_BASE + 0x0D74) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_30              (ADDR_ISP_BASE + 0x0D78) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_31              (ADDR_ISP_BASE + 0x0D7C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_32              (ADDR_ISP_BASE + 0x0D80) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_33              (ADDR_ISP_BASE + 0x0D84) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_34              (ADDR_ISP_BASE + 0x0D88) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_35              (ADDR_ISP_BASE + 0x0D8C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_36              (ADDR_ISP_BASE + 0x0D90) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_37              (ADDR_ISP_BASE + 0x0D94) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_38              (ADDR_ISP_BASE + 0x0D98) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_39              (ADDR_ISP_BASE + 0x0D9C) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_40              (ADDR_ISP_BASE + 0x0DA0) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_41              (ADDR_ISP_BASE + 0x0DA4) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_42              (ADDR_ISP_BASE + 0x0DA8) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_43              (ADDR_ISP_BASE + 0x0DAC) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_44              (ADDR_ISP_BASE + 0x0DB0) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_45              (ADDR_ISP_BASE + 0x0DB4) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_46              (ADDR_ISP_BASE + 0x0DB8) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_47              (ADDR_ISP_BASE + 0x0DBC) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_48              (ADDR_ISP_BASE + 0x0DC0) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_49              (ADDR_ISP_BASE + 0x0DC4) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_50              (ADDR_ISP_BASE + 0x0DC8) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_51              (ADDR_ISP_BASE + 0x0DCC) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_52              (ADDR_ISP_BASE + 0x0DD0) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_53              (ADDR_ISP_BASE + 0x0DD4) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_54              (ADDR_ISP_BASE + 0x0DD8) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_55              (ADDR_ISP_BASE + 0x0DDC) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_56              (ADDR_ISP_BASE + 0x0DE0) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_57              (ADDR_ISP_BASE + 0x0DE4) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_58              (ADDR_ISP_BASE + 0x0DE8) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_59              (ADDR_ISP_BASE + 0x0DEC) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_60              (ADDR_ISP_BASE + 0x0DF0) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_61              (ADDR_ISP_BASE + 0x0DF4) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_62              (ADDR_ISP_BASE + 0x0DF8) // Y Histogram result register 
#define ADDR_REG_YHIST_ACC_63              (ADDR_ISP_BASE + 0x0DFC) // Y Histogram result register 
#define ADDR_REG_IGRVAL_0                  (ADDR_ISP_BASE + 0x0E00) // RGB Gamma table Register 0
#define ADDR_REG_IGRVAL_1                  (ADDR_ISP_BASE + 0x0E04) // RGB Gamma table Register 1
#define ADDR_REG_IGRVAL_2                  (ADDR_ISP_BASE + 0x0E08) // RGB Gamma table Register 2
#define ADDR_REG_IGRVAL_3                  (ADDR_ISP_BASE + 0x0E0C) // RGB Gamma table Register 3
#define ADDR_REG_IGRVAL_4                  (ADDR_ISP_BASE + 0x0E10) // RGB Gamma table Register 4
#define ADDR_REG_IGRVAL_5                  (ADDR_ISP_BASE + 0x0E14) // RGB Gamma table Register 5
#define ADDR_REG_IGRVAL_6                  (ADDR_ISP_BASE + 0x0E18) // RGB Gamma table Register 6
#define ADDR_REG_IGRVAL_7                  (ADDR_ISP_BASE + 0x0E1C) // RGB Gamma table Register 7
#define ADDR_REG_IGRVAL_8                  (ADDR_ISP_BASE + 0x0E20) // RGB Gamma table Register 8
#define ADDR_REG_IGRVAL_9                  (ADDR_ISP_BASE + 0x0E24) // RGB Gamma table Register 9
#define ADDR_REG_IGRVAL_10                 (ADDR_ISP_BASE + 0x0E28) // RGB Gamma table Register 10
#define ADDR_REG_IGRVAL_11                 (ADDR_ISP_BASE + 0x0E2C) // RGB Gamma table Register 11
#define ADDR_REG_IGRVAL_12                 (ADDR_ISP_BASE + 0x0E30) // RGB Gamma table Register 12
#define ADDR_REG_IGRVAL_13                 (ADDR_ISP_BASE + 0x0E34) // RGB Gamma table Register 13
#define ADDR_REG_IGRVAL_14                 (ADDR_ISP_BASE + 0x0E38) // RGB Gamma table Register 14
#define ADDR_REG_ICCONV_0                  (ADDR_ISP_BASE + 0x0E40) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_1                  (ADDR_ISP_BASE + 0x0E44) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_2                  (ADDR_ISP_BASE + 0x0E48) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_3                  (ADDR_ISP_BASE + 0x0E4C) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_4                  (ADDR_ISP_BASE + 0x0E50) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_5                  (ADDR_ISP_BASE + 0x0E54) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_6                  (ADDR_ISP_BASE + 0x0E58) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_7                  (ADDR_ISP_BASE + 0x0E5C) // RGB to YUV color space conversion Register
#define ADDR_REG_ICCONV_8                  (ADDR_ISP_BASE + 0x0E60) // RGB to YUV color space conversion Register
#define ADDR_REG_ISHRP1_0                  (ADDR_ISP_BASE + 0x0E80) // Sharpen Edge Amplification Weight and Difference 0
#define ADDR_REG_ISHRP1_1                  (ADDR_ISP_BASE + 0x0E84) // Sharpen Edge Amplification Weight and Difference 1
#define ADDR_REG_ISHRP1_2                  (ADDR_ISP_BASE + 0x0E88) // Sharpen Edge Amplification Weight and Difference 2
#define ADDR_REG_ISHRP1_3                  (ADDR_ISP_BASE + 0x0E8C) // Sharpen Edge Amplification Weight and Difference 3
#define ADDR_REG_ISHRP1_4                  (ADDR_ISP_BASE + 0x0E90) // Sharpen Edge Amplification Weight and Difference 4
#define ADDR_REG_ISHRP1_5                  (ADDR_ISP_BASE + 0x0E94) // Sharpen Edge Amplification Weight and Difference 5
#define ADDR_REG_ISHRP1_6                  (ADDR_ISP_BASE + 0x0E98) // Sharpen Edge Amplification Weight and Difference 6
#define ADDR_REG_ISHRP1_7                  (ADDR_ISP_BASE + 0x0E9C) // Sharpen Edge Amplification Weight and Difference 7
#define ADDR_REG_ISHRP1_8                  (ADDR_ISP_BASE + 0x0EA0) // Sharpen Edge Amplification Weight and Difference 8
#define ADDR_REG_ISHRP1_9                  (ADDR_ISP_BASE + 0x0EA4) // Sharpen Edge Amplification Weight and Difference 9
#define ADDR_REG_ISHRP1_10                 (ADDR_ISP_BASE + 0x0EA8) // Sharpen Edge Amplification Weight and Difference 10
#define ADDR_REG_ISHRP1_11                 (ADDR_ISP_BASE + 0x0EAC) // Sharpen Edge Amplification Weight and Difference 11
#define ADDR_REG_ISHRP1_12                 (ADDR_ISP_BASE + 0x0EB0) // Sharpen Edge Amplification Weight and Difference 12
#define ADDR_REG_ISHRP1_13                 (ADDR_ISP_BASE + 0x0EB4) // Sharpen Edge Amplification Weight and Difference 13
#define ADDR_REG_ISHRP1_14                 (ADDR_ISP_BASE + 0x0EB8) // Sharpen Edge Amplification Weight and Difference 14
#define ADDR_REG_ISHRP2_0                  (ADDR_ISP_BASE + 0x0EBC) // Sharpen Edge Amplification Factor and Slope 0
#define ADDR_REG_ISHRP2_1                  (ADDR_ISP_BASE + 0x0EC0) // Sharpen Edge Amplification Factor and Slope 1
#define ADDR_REG_ISHRP2_2                  (ADDR_ISP_BASE + 0x0EC4) // Sharpen Edge Amplification Factor and Slope 2
#define ADDR_REG_ISHRP2_3                  (ADDR_ISP_BASE + 0x0EC8) // Sharpen Edge Amplification Factor and Slope 3
#define ADDR_REG_ISHRP2_4                  (ADDR_ISP_BASE + 0x0ECC) // Sharpen Edge Amplification Factor and Slope 4
#define ADDR_REG_ISHRP2_5                  (ADDR_ISP_BASE + 0x0ED0) // Sharpen Edge Amplification Factor and Slope 5
#define ADDR_REG_ISHRP3                    (ADDR_ISP_BASE + 0x0ED4) // Sharpen Edge Amplification Weight Normalization
#define ADDR_REG_IUVS1                     (ADDR_ISP_BASE + 0x0ED8) // UV smoothing Register 1
#define ADDR_REG_IUVS2                     (ADDR_ISP_BASE + 0x0EDC) // UV smoothing Register 2
#define ADDR_REG_IUVCKS1                   (ADDR_ISP_BASE + 0x0EE0) // UV Color Kill Register 1
#define ADDR_REG_IUVCKS2                   (ADDR_ISP_BASE + 0x0EE4) // UV Color Kill Register 2
#define ADDR_REG_ISHRPET                   (ADDR_ISP_BASE + 0x0EE8) // Sharpen Edge Threshold
#define ADDR_REG_YCURVE_0                  (ADDR_ISP_BASE + 0x0F00) // Y Curve PARAM table Register 0
#define ADDR_REG_YCURVE_1                  (ADDR_ISP_BASE + 0x0F04) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_2                  (ADDR_ISP_BASE + 0x0F08) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_3                  (ADDR_ISP_BASE + 0x0F0C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_4                  (ADDR_ISP_BASE + 0x0F10) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_5                  (ADDR_ISP_BASE + 0x0F14) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_6                  (ADDR_ISP_BASE + 0x0F18) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_7                  (ADDR_ISP_BASE + 0x0F1C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_8                  (ADDR_ISP_BASE + 0x0F20) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_9                  (ADDR_ISP_BASE + 0x0F24) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_10                 (ADDR_ISP_BASE + 0x0F28) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_11                 (ADDR_ISP_BASE + 0x0F2C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_12                 (ADDR_ISP_BASE + 0x0F30) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_13                 (ADDR_ISP_BASE + 0x0F34) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_14                 (ADDR_ISP_BASE + 0x0F38) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_15                 (ADDR_ISP_BASE + 0x0F3C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_16                 (ADDR_ISP_BASE + 0x0F40) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_17                 (ADDR_ISP_BASE + 0x0F44) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_18                 (ADDR_ISP_BASE + 0x0F48) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_19                 (ADDR_ISP_BASE + 0x0F4C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_20                 (ADDR_ISP_BASE + 0x0F50) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_21                 (ADDR_ISP_BASE + 0x0F54) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_22                 (ADDR_ISP_BASE + 0x0F58) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_23                 (ADDR_ISP_BASE + 0x0F5C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_24                 (ADDR_ISP_BASE + 0x0F60) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_25                 (ADDR_ISP_BASE + 0x0F64) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_26                 (ADDR_ISP_BASE + 0x0F68) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_27                 (ADDR_ISP_BASE + 0x0F6C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_28                 (ADDR_ISP_BASE + 0x0F70) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_29                 (ADDR_ISP_BASE + 0x0F74) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_30                 (ADDR_ISP_BASE + 0x0F78) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_31                 (ADDR_ISP_BASE + 0x0F7C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_32                 (ADDR_ISP_BASE + 0x0F80) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_33                 (ADDR_ISP_BASE + 0x0F84) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_34                 (ADDR_ISP_BASE + 0x0F88) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_35                 (ADDR_ISP_BASE + 0x0F8C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_36                 (ADDR_ISP_BASE + 0x0F90) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_37                 (ADDR_ISP_BASE + 0x0F94) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_38                 (ADDR_ISP_BASE + 0x0F98) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_39                 (ADDR_ISP_BASE + 0x0F9C) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_40                 (ADDR_ISP_BASE + 0x0FA0) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_41                 (ADDR_ISP_BASE + 0x0FA4) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_42                 (ADDR_ISP_BASE + 0x0FA8) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_43                 (ADDR_ISP_BASE + 0x0FAC) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_44                 (ADDR_ISP_BASE + 0x0FB0) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_45                 (ADDR_ISP_BASE + 0x0FB4) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_46                 (ADDR_ISP_BASE + 0x0FB8) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_47                 (ADDR_ISP_BASE + 0x0FBC) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_48                 (ADDR_ISP_BASE + 0x0FC0) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_49                 (ADDR_ISP_BASE + 0x0FC4) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_50                 (ADDR_ISP_BASE + 0x0FC8) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_51                 (ADDR_ISP_BASE + 0x0FCC) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_52                 (ADDR_ISP_BASE + 0x0FD0) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_53                 (ADDR_ISP_BASE + 0x0FD4) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_54                 (ADDR_ISP_BASE + 0x0FD8) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_55                 (ADDR_ISP_BASE + 0x0FDC) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_56                 (ADDR_ISP_BASE + 0x0FE0) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_57                 (ADDR_ISP_BASE + 0x0FE4) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_58                 (ADDR_ISP_BASE + 0x0FE8) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_59                 (ADDR_ISP_BASE + 0x0FEC) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_60                 (ADDR_ISP_BASE + 0x0FF0) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_61                 (ADDR_ISP_BASE + 0x0FF4) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_62                 (ADDR_ISP_BASE + 0x0FF8) // Y Curve PARAM table Register 
#define ADDR_REG_YCURVE_63                 (ADDR_ISP_BASE + 0x0FFC) // Y Curve PARAM table Register 63
#if 0
#define ADDR_REG_NL3DGSIGMAX0              (ADDR_ISP_BASE + 0x1020) // NL3D G SIGMA X Register 0
#define ADDR_REG_NL3DGSIGMAX1              (ADDR_ISP_BASE + 0x1024) // NL3D G SIGMA X Register 1
#define ADDR_REG_NL3DGSIGMAX2              (ADDR_ISP_BASE + 0x1028) // NL3D G SIGMA X Register 2
#define ADDR_REG_NL3DGSIGMAX3              (ADDR_ISP_BASE + 0x102C) // NL3D G SIGMA X Register 3
#define ADDR_REG_NL3DGSIGMAX4              (ADDR_ISP_BASE + 0x1030) // NL3D G SIGMA X Register 4
#define ADDR_REG_NL3DGSIGMAX5              (ADDR_ISP_BASE + 0x1034) // NL3D G SIGMA X Register 5
#define ADDR_REG_NL3DGSIGMAX6              (ADDR_ISP_BASE + 0x1038) // NL3D G SIGMA X Register 6
#define ADDR_REG_NL3DGSIGMAX7              (ADDR_ISP_BASE + 0x103C) // NL3D G SIGMA X Register 7
#define ADDR_REG_NL3DGSIGMAY0              (ADDR_ISP_BASE + 0x10A0) // NL3D G SIGMA Y Register 0
#define ADDR_REG_NL3DGSIGMAY1              (ADDR_ISP_BASE + 0x10A4) // NL3D G SIGMA Y Register 1
#define ADDR_REG_NL3DGSIGMAY2              (ADDR_ISP_BASE + 0x10A8) // NL3D G SIGMA Y Register 2
#define ADDR_REG_NL3DGSIGMAY3              (ADDR_ISP_BASE + 0x10AC) // NL3D G SIGMA Y Register 3
#define ADDR_REG_NL3DGSIGMAY4              (ADDR_ISP_BASE + 0x10B0) // NL3D G SIGMA Y Register 4
#define ADDR_REG_NL3DGSIGMAY5              (ADDR_ISP_BASE + 0x10B4) // NL3D G SIGMA Y Register 5
#define ADDR_REG_NL3DGSIGMAY6              (ADDR_ISP_BASE + 0x10B8) // NL3D G SIGMA Y Register 6
#define ADDR_REG_NL3DGSIGMAY7              (ADDR_ISP_BASE + 0x10BC) // NL3D G SIGMA Y Register 7
#define ADDR_REG_NL3DGSIGMAY8              (ADDR_ISP_BASE + 0x10C0) // NL3D G SIGMA Y Register 8
#define ADDR_REG_NL3DGSIGMAY9              (ADDR_ISP_BASE + 0x10C4) // NL3D G SIGMA Y Register 9
#define ADDR_REG_NL3DGSIGMAY10             (ADDR_ISP_BASE + 0x10C8) // NL3D G SIGMA Y Register 10
#define ADDR_REG_NL3DGSIGMAY11             (ADDR_ISP_BASE + 0x10CC) // NL3D G SIGMA Y Register 11
#define ADDR_REG_NL3DGSIGMAY12             (ADDR_ISP_BASE + 0x10D0) // NL3D G SIGMA Y Register 12
#define ADDR_REG_NL3DGSIGMAY13             (ADDR_ISP_BASE + 0x10D4) // NL3D G SIGMA Y Register 13
#define ADDR_REG_NL3DGSIGMAY14             (ADDR_ISP_BASE + 0x10D8) // NL3D G SIGMA Y Register 14
#define ADDR_REG_NL3DGSIGMAY15             (ADDR_ISP_BASE + 0x10DC) // NL3D G SIGMA Y Register 15
#define ADDR_REG_NL3DGSIGMAS0              (ADDR_ISP_BASE + 0x1140) // NL3D G SIGMA S Register 0
#define ADDR_REG_NL3DGSIGMAS1              (ADDR_ISP_BASE + 0x1144) // NL3D G SIGMA S Register 1
#define ADDR_REG_NL3DGSIGMAS2              (ADDR_ISP_BASE + 0x1148) // NL3D G SIGMA S Register 2
#define ADDR_REG_NL3DGSIGMAS3              (ADDR_ISP_BASE + 0x114C) // NL3D G SIGMA S Register 3
#define ADDR_REG_NL3DGSIGMAS4              (ADDR_ISP_BASE + 0x1150) // NL3D G SIGMA S Register 4
#define ADDR_REG_NL3DGSIGMAS5              (ADDR_ISP_BASE + 0x1154) // NL3D G SIGMA S Register 5
#define ADDR_REG_NL3DGSIGMAS6              (ADDR_ISP_BASE + 0x1158) // NL3D G SIGMA S Register 6
#define ADDR_REG_NL3DGSIGMAS7              (ADDR_ISP_BASE + 0x115C) // NL3D G SIGMA S Register 7
#define ADDR_REG_NL3DGFILTPARX0            (ADDR_ISP_BASE + 0x11A0) // NL3D G FILTPAR X Register 0
#define ADDR_REG_NL3DGFILTPARX1            (ADDR_ISP_BASE + 0x11A4) // NL3D G FILTPAR X Register 1
#define ADDR_REG_NL3DGFILTPARX2            (ADDR_ISP_BASE + 0x11A8) // NL3D G FILTPAR X Register 2
#define ADDR_REG_NL3DGFILTPARX3            (ADDR_ISP_BASE + 0x11AC) // NL3D G FILTPAR X Register 3
#define ADDR_REG_NL3DGFILTPARX4            (ADDR_ISP_BASE + 0x11B0) // NL3D G FILTPAR X Register 4
#define ADDR_REG_NL3DGFILTPARX5            (ADDR_ISP_BASE + 0x11B4) // NL3D G FILTPAR X Register 5
#define ADDR_REG_NL3DGFILTPARX6            (ADDR_ISP_BASE + 0x11B8) // NL3D G FILTPAR X Register 6
#define ADDR_REG_NL3DGFILTPARX7            (ADDR_ISP_BASE + 0x11BC) // NL3D G FILTPAR X Register 7
#define ADDR_REG_NL3DGFILTPARY0            (ADDR_ISP_BASE + 0x1220) // NL3D G FILTPAR Y Register 0
#define ADDR_REG_NL3DGFILTPARY1            (ADDR_ISP_BASE + 0x1224) // NL3D G FILTPAR Y Register 1
#define ADDR_REG_NL3DGFILTPARY2            (ADDR_ISP_BASE + 0x1228) // NL3D G FILTPAR Y Register 2
#define ADDR_REG_NL3DGFILTPARY3            (ADDR_ISP_BASE + 0x122C) // NL3D G FILTPAR Y Register 3
#define ADDR_REG_NL3DGFILTPARY4            (ADDR_ISP_BASE + 0x1230) // NL3D G FILTPAR Y Register 4
#define ADDR_REG_NL3DGFILTPARY5            (ADDR_ISP_BASE + 0x1234) // NL3D G FILTPAR Y Register 5
#define ADDR_REG_NL3DGFILTPARY6            (ADDR_ISP_BASE + 0x1238) // NL3D G FILTPAR Y Register 6
#define ADDR_REG_NL3DGFILTPARY7            (ADDR_ISP_BASE + 0x123C) // NL3D G FILTPAR Y Register 7
#define ADDR_REG_NL3DGFILTPARY8            (ADDR_ISP_BASE + 0x1240) // NL3D G FILTPAR Y Register 8
#define ADDR_REG_NL3DGFILTPARY9            (ADDR_ISP_BASE + 0x1244) // NL3D G FILTPAR Y Register 9
#define ADDR_REG_NL3DGFILTPARY10           (ADDR_ISP_BASE + 0x1248) // NL3D G FILTPAR Y Register 10
#define ADDR_REG_NL3DGFILTPARY11           (ADDR_ISP_BASE + 0x124C) // NL3D G FILTPAR Y Register 11
#define ADDR_REG_NL3DGFILTPARY12           (ADDR_ISP_BASE + 0x1250) // NL3D G FILTPAR Y Register 12
#define ADDR_REG_NL3DGFILTPARY13           (ADDR_ISP_BASE + 0x1254) // NL3D G FILTPAR Y Register 13
#define ADDR_REG_NL3DGFILTPARY14           (ADDR_ISP_BASE + 0x1258) // NL3D G FILTPAR Y Register 14
#define ADDR_REG_NL3DGFILTPARY15           (ADDR_ISP_BASE + 0x125C) // NL3D G FILTPAR Y Register 15
#define ADDR_REG_NL3DGFILTPARS0            (ADDR_ISP_BASE + 0x12C0) // NL3D G FILTPAR S Register 0
#define ADDR_REG_NL3DGFILTPARS1            (ADDR_ISP_BASE + 0x12C4) // NL3D G FILTPAR S Register 1
#define ADDR_REG_NL3DGFILTPARS2            (ADDR_ISP_BASE + 0x12C8) // NL3D G FILTPAR S Register 2
#define ADDR_REG_NL3DGFILTPARS3            (ADDR_ISP_BASE + 0x12CC) // NL3D G FILTPAR S Register 3
#define ADDR_REG_NL3DGFILTPARS4            (ADDR_ISP_BASE + 0x12D0) // NL3D G FILTPAR S Register 4
#define ADDR_REG_NL3DGFILTPARS5            (ADDR_ISP_BASE + 0x12D4) // NL3D G FILTPAR S Register 5
#define ADDR_REG_NL3DGFILTPARS6            (ADDR_ISP_BASE + 0x12D8) // NL3D G FILTPAR S Register 6
#define ADDR_REG_NL3DGFILTPARS7            (ADDR_ISP_BASE + 0x12DC) // NL3D G FILTPAR S Register 7
#define ADDR_REG_NL3DCFG                   (ADDR_ISP_BASE + 0x1300) // NL 3D CFG Register
#define ADDR_REG_DNRIAY                    (ADDR_ISP_BASE + 0x1304) // DN Reference Input Image Y Plane Start Address Register
#define ADDR_REG_DNRFBDCAR                 (ADDR_ISP_BASE + 0x1308) // FBDC axi read address status register
#define ADDR_REG_DNRIS                     (ADDR_ISP_BASE + 0x130C) // DN Reference Input Image Stride Register, no use
#define ADDR_REG_DNROAY                    (ADDR_ISP_BASE + 0x1310) // DN Reference Output Image Y Plane Start Address Register
#define ADDR_REG_DNRCC2                    (ADDR_ISP_BASE + 0x1314) // DN Reference Buffer Compression Control Register 2
#define ADDR_REG_DNRCC3                    (ADDR_ISP_BASE + 0x1318) // DN Reference Buffer Compression Control Register 3
#define ADDR_REG_DNRISZ                    (ADDR_ISP_BASE + 0x131C) // DN Reference Input Buffer Size Register, byte unit
#define ADDR_REG_DNROSZ                    (ADDR_ISP_BASE + 0x1320) // DN Reference Output Buffer Size Register, byte unit
#define ADDR_REG_DNRCC                     (ADDR_ISP_BASE + 0x1324) // DN Reference Buffer Compression Control Register
#define ADDR_REG_DNRCC1                    (ADDR_ISP_BASE + 0x1328) // DN Reference Buffer Compression Control Register 1
#define ADDR_REG_DNRCS                     (ADDR_ISP_BASE + 0x132C) // DN Reference Buffer Compression Status Register
#define ADDR_REG_DNRCL                     (ADDR_ISP_BASE + 0x1330) // DN Reference Buffer Compression had used the max buffer length.
#define ADDR_REG_NL3D_W2D1R                (ADDR_ISP_BASE + 0x1334) // NL3D 1st 2D filter weight table regsiter
#define ADDR_REG_NL3D_D2D1R0               (ADDR_ISP_BASE + 0x1338) // NL3D 1st 2D filter difference table regsiter for R
#define ADDR_REG_NL3D_D2D1R1               (ADDR_ISP_BASE + 0x133C) // NL3D 1st 2D filter difference table regsiter for R
#define ADDR_REG_NL3D_D2D1G0               (ADDR_ISP_BASE + 0x1340) // NL3D 1st 2D filter difference table regsiter for G
#define ADDR_REG_NL3D_D2D1G1               (ADDR_ISP_BASE + 0x1344) // NL3D 1st 2D filter difference table regsiter for G
#define ADDR_REG_NL3D_D2D1B0               (ADDR_ISP_BASE + 0x1348) // NL3D 1st 2D filter difference table regsiter for B
#define ADDR_REG_NL3D_D2D1B1               (ADDR_ISP_BASE + 0x134C) // NL3D 1st 2D filter difference table regsiter for B
#define ADDR_REG_NL3D_S2D1R0               (ADDR_ISP_BASE + 0x1350) // NL3D 1st 2D filter spatial weight table regsiter
#define ADDR_REG_NL3D_S2D1R1               (ADDR_ISP_BASE + 0x1354) // NL3D 1st 2D filter spatial weight table regsiter
#define ADDR_REG_NL3D_W2D2R                (ADDR_ISP_BASE + 0x1358) // NL3D 2nd 2D filter weight table regsiter
#define ADDR_REG_NL3D_D2D2R0               (ADDR_ISP_BASE + 0x135C) // NL3D 2nd 2D filter difference table regsiter
#define ADDR_REG_NL3D_D2D2R1               (ADDR_ISP_BASE + 0x1360) // NL3D 2nd 2D filter difference table regsiter
#define ADDR_REG_NL3D_S2D2R0               (ADDR_ISP_BASE + 0x1364) // NL3D 2nd 2D filter spatial weight table regsiter
#define ADDR_REG_NL3D_S2D2R1               (ADDR_ISP_BASE + 0x1368) // NL3D 2nd 2D filter spatial weight table regsiter
#define ADDR_REG_NL3D_REFWCX0              (ADDR_ISP_BASE + 0x136C) // NL3D refw curve x register
#define ADDR_REG_NL3D_REFWCX1              (ADDR_ISP_BASE + 0x1370) // NL3D  refw curve x register
#define ADDR_REG_NL3D_REFWCY0              (ADDR_ISP_BASE + 0x1374) // NL3D  refw curve y register
#define ADDR_REG_NL3D_REFWCY1              (ADDR_ISP_BASE + 0x1378) // NL3D  refw curve y register
#define ADDR_REG_NL3D_MOVWCX0              (ADDR_ISP_BASE + 0x137C) // NL3D movw curve x register
#define ADDR_REG_NL3D_MOVWCX1              (ADDR_ISP_BASE + 0x1380) // NL3D  movw curve x register
#define ADDR_REG_NL3D_MOVWCY0              (ADDR_ISP_BASE + 0x1384) // NL3D  movw curve y register
#define ADDR_REG_NL3D_MOVWCY1              (ADDR_ISP_BASE + 0x1388) // NL3D  movw curve y register
#define ADDR_REG_NL3D_SNTCX0               (ADDR_ISP_BASE + 0x138C) // NL3D snt curve x register
#define ADDR_REG_NL3D_SNTCX1               (ADDR_ISP_BASE + 0x1390) // NL3D  snt curve x register
#define ADDR_REG_NL3D_SNTCY0               (ADDR_ISP_BASE + 0x1394) // NL3D  snt curve y register
#define ADDR_REG_NL3D_SNTCY1               (ADDR_ISP_BASE + 0x1398) // NL3D  snt curve y register
#define ADDR_REG_NL2DRSIGMAX0              (ADDR_ISP_BASE + 0x2000) // NL2D R SIGMA X Register 0
#define ADDR_REG_NL2DRSIGMAX1              (ADDR_ISP_BASE + 0x2004) // NL2D R SIGMA X Register 1
#define ADDR_REG_NL2DRSIGMAX2              (ADDR_ISP_BASE + 0x2008) // NL2D R SIGMA X Register 2
#define ADDR_REG_NL2DRSIGMAX3              (ADDR_ISP_BASE + 0x200C) // NL2D R SIGMA X Register 3
#define ADDR_REG_NL2DRSIGMAX4              (ADDR_ISP_BASE + 0x2010) // NL2D R SIGMA X Register 4
#define ADDR_REG_NL2DRSIGMAX5              (ADDR_ISP_BASE + 0x2014) // NL2D R SIGMA X Register 5
#define ADDR_REG_NL2DRSIGMAX6              (ADDR_ISP_BASE + 0x2018) // NL2D R SIGMA X Register 6
#define ADDR_REG_NL2DRSIGMAX7              (ADDR_ISP_BASE + 0x201C) // NL2D R SIGMA X Register 7
#define ADDR_REG_NL2DGSIGMAX0              (ADDR_ISP_BASE + 0x2020) // NL2D G SIGMA X Register 0
#define ADDR_REG_NL2DGSIGMAX1              (ADDR_ISP_BASE + 0x2024) // NL2D G SIGMA X Register 1
#define ADDR_REG_NL2DGSIGMAX2              (ADDR_ISP_BASE + 0x2028) // NL2D G SIGMA X Register 2
#define ADDR_REG_NL2DGSIGMAX3              (ADDR_ISP_BASE + 0x202C) // NL2D G SIGMA X Register 3
#define ADDR_REG_NL2DGSIGMAX4              (ADDR_ISP_BASE + 0x2030) // NL2D G SIGMA X Register 4
#define ADDR_REG_NL2DGSIGMAX5              (ADDR_ISP_BASE + 0x2034) // NL2D G SIGMA X Register 5
#define ADDR_REG_NL2DGSIGMAX6              (ADDR_ISP_BASE + 0x2038) // NL2D G SIGMA X Register 6
#define ADDR_REG_NL2DGSIGMAX7              (ADDR_ISP_BASE + 0x203C) // NL2D G SIGMA X Register 7
#define ADDR_REG_NL2DBSIGMAX0              (ADDR_ISP_BASE + 0x2040) // NL2D B SIGMA X Register 0
#define ADDR_REG_NL2DBSIGMAX1              (ADDR_ISP_BASE + 0x2044) // NL2D B SIGMA X Register 1
#define ADDR_REG_NL2DBSIGMAX2              (ADDR_ISP_BASE + 0x2048) // NL2D B SIGMA X Register 2
#define ADDR_REG_NL2DBSIGMAX3              (ADDR_ISP_BASE + 0x204C) // NL2D B SIGMA X Register 3
#define ADDR_REG_NL2DBSIGMAX4              (ADDR_ISP_BASE + 0x2050) // NL2D B SIGMA X Register 4
#define ADDR_REG_NL2DBSIGMAX5              (ADDR_ISP_BASE + 0x2054) // NL2D B SIGMA X Register 5
#define ADDR_REG_NL2DBSIGMAX6              (ADDR_ISP_BASE + 0x2058) // NL2D B SIGMA X Register 6
#define ADDR_REG_NL2DBSIGMAX7              (ADDR_ISP_BASE + 0x205C) // NL2D B SIGMA X Register 7
#define ADDR_REG_NL2DRSIGMAY0              (ADDR_ISP_BASE + 0x2060) // NL2D R SIGMA Y Register 0
#define ADDR_REG_NL2DRSIGMAY1              (ADDR_ISP_BASE + 0x2064) // NL2D R SIGMA Y Register 1
#define ADDR_REG_NL2DRSIGMAY2              (ADDR_ISP_BASE + 0x2068) // NL2D R SIGMA Y Register 2
#define ADDR_REG_NL2DRSIGMAY3              (ADDR_ISP_BASE + 0x206C) // NL2D R SIGMA Y Register 3
#define ADDR_REG_NL2DRSIGMAY4              (ADDR_ISP_BASE + 0x2070) // NL2D R SIGMA Y Register 4
#define ADDR_REG_NL2DRSIGMAY5              (ADDR_ISP_BASE + 0x2074) // NL2D R SIGMA Y Register 5
#define ADDR_REG_NL2DRSIGMAY6              (ADDR_ISP_BASE + 0x2078) // NL2D R SIGMA Y Register 6
#define ADDR_REG_NL2DRSIGMAY7              (ADDR_ISP_BASE + 0x207C) // NL2D R SIGMA Y Register 7
#define ADDR_REG_NL2DRSIGMAY8              (ADDR_ISP_BASE + 0x2080) // NL2D R SIGMA Y Register 8
#define ADDR_REG_NL2DRSIGMAY9              (ADDR_ISP_BASE + 0x2084) // NL2D R SIGMA Y Register 9
#define ADDR_REG_NL2DRSIGMAY10             (ADDR_ISP_BASE + 0x2088) // NL2D R SIGMA Y Register 10
#define ADDR_REG_NL2DRSIGMAY11             (ADDR_ISP_BASE + 0x208C) // NL2D R SIGMA Y Register 11
#define ADDR_REG_NL2DRSIGMAY12             (ADDR_ISP_BASE + 0x2090) // NL2D R SIGMA Y Register 12
#define ADDR_REG_NL2DRSIGMAY13             (ADDR_ISP_BASE + 0x2094) // NL2D R SIGMA Y Register 13
#define ADDR_REG_NL2DRSIGMAY14             (ADDR_ISP_BASE + 0x2098) // NL2D R SIGMA Y Register 14
#define ADDR_REG_NL2DRSIGMAY15             (ADDR_ISP_BASE + 0x209C) // NL2D R SIGMA Y Register 15
#define ADDR_REG_NL2DGSIGMAY0              (ADDR_ISP_BASE + 0x20A0) // NL2D G SIGMA Y Register 0
#define ADDR_REG_NL2DGSIGMAY1              (ADDR_ISP_BASE + 0x20A4) // NL2D G SIGMA Y Register 1
#define ADDR_REG_NL2DGSIGMAY2              (ADDR_ISP_BASE + 0x20A8) // NL2D G SIGMA Y Register 2
#define ADDR_REG_NL2DGSIGMAY3              (ADDR_ISP_BASE + 0x20AC) // NL2D G SIGMA Y Register 3
#define ADDR_REG_NL2DGSIGMAY4              (ADDR_ISP_BASE + 0x20B0) // NL2D G SIGMA Y Register 4
#define ADDR_REG_NL2DGSIGMAY5              (ADDR_ISP_BASE + 0x20B4) // NL2D G SIGMA Y Register 5
#define ADDR_REG_NL2DGSIGMAY6              (ADDR_ISP_BASE + 0x20B8) // NL2D G SIGMA Y Register 6
#define ADDR_REG_NL2DGSIGMAY7              (ADDR_ISP_BASE + 0x20BC) // NL2D G SIGMA Y Register 7
#define ADDR_REG_NL2DGSIGMAY8              (ADDR_ISP_BASE + 0x20C0) // NL2D G SIGMA Y Register 8
#define ADDR_REG_NL2DGSIGMAY9              (ADDR_ISP_BASE + 0x20C4) // NL2D G SIGMA Y Register 9
#define ADDR_REG_NL2DGSIGMAY10             (ADDR_ISP_BASE + 0x20C8) // NL2D G SIGMA Y Register 10
#define ADDR_REG_NL2DGSIGMAY11             (ADDR_ISP_BASE + 0x20CC) // NL2D G SIGMA Y Register 11
#define ADDR_REG_NL2DGSIGMAY12             (ADDR_ISP_BASE + 0x20D0) // NL2D G SIGMA Y Register 12
#define ADDR_REG_NL2DGSIGMAY13             (ADDR_ISP_BASE + 0x20D4) // NL2D G SIGMA Y Register 13
#define ADDR_REG_NL2DGSIGMAY14             (ADDR_ISP_BASE + 0x20D8) // NL2D G SIGMA Y Register 14
#define ADDR_REG_NL2DGSIGMAY15             (ADDR_ISP_BASE + 0x20DC) // NL2D G SIGMA Y Register 15
#define ADDR_REG_NL2DBSIGMAY0              (ADDR_ISP_BASE + 0x20E0) // NL2D B SIGMA Y Register 0
#define ADDR_REG_NL2DBSIGMAY1              (ADDR_ISP_BASE + 0x20E4) // NL2D B SIGMA Y Register 1
#define ADDR_REG_NL2DBSIGMAY2              (ADDR_ISP_BASE + 0x20E8) // NL2D B SIGMA Y Register 2
#define ADDR_REG_NL2DBSIGMAY3              (ADDR_ISP_BASE + 0x20EC) // NL2D B SIGMA Y Register 3
#define ADDR_REG_NL2DBSIGMAY4              (ADDR_ISP_BASE + 0x20F0) // NL2D B SIGMA Y Register 4
#define ADDR_REG_NL2DBSIGMAY5              (ADDR_ISP_BASE + 0x20F4) // NL2D B SIGMA Y Register 5
#define ADDR_REG_NL2DBSIGMAY6              (ADDR_ISP_BASE + 0x20F8) // NL2D B SIGMA Y Register 6
#define ADDR_REG_NL2DBSIGMAY7              (ADDR_ISP_BASE + 0x20FC) // NL2D B SIGMA Y Register 7
#define ADDR_REG_NL2DBSIGMAY8              (ADDR_ISP_BASE + 0x2100) // NL2D B SIGMA Y Register 8
#define ADDR_REG_NL2DBSIGMAY9              (ADDR_ISP_BASE + 0x2104) // NL2D B SIGMA Y Register 9
#define ADDR_REG_NL2DBSIGMAY10             (ADDR_ISP_BASE + 0x2108) // NL2D B SIGMA Y Register 10
#define ADDR_REG_NL2DBSIGMAY11             (ADDR_ISP_BASE + 0x210C) // NL2D B SIGMA Y Register 11
#define ADDR_REG_NL2DBSIGMAY12             (ADDR_ISP_BASE + 0x2110) // NL2D B SIGMA Y Register 12
#define ADDR_REG_NL2DBSIGMAY13             (ADDR_ISP_BASE + 0x2114) // NL2D B SIGMA Y Register 13
#define ADDR_REG_NL2DBSIGMAY14             (ADDR_ISP_BASE + 0x2118) // NL2D B SIGMA Y Register 14
#define ADDR_REG_NL2DBSIGMAY15             (ADDR_ISP_BASE + 0x211C) // NL2D B SIGMA Y Register 15
#define ADDR_REG_NL2DRSIGMAS0              (ADDR_ISP_BASE + 0x2120) // NL2D R SIGMA S Register 0
#define ADDR_REG_NL2DRSIGMAS1              (ADDR_ISP_BASE + 0x2124) // NL2D R SIGMA S Register 1
#define ADDR_REG_NL2DRSIGMAS2              (ADDR_ISP_BASE + 0x2128) // NL2D R SIGMA S Register 2
#define ADDR_REG_NL2DRSIGMAS3              (ADDR_ISP_BASE + 0x212C) // NL2D R SIGMA S Register 3
#define ADDR_REG_NL2DRSIGMAS4              (ADDR_ISP_BASE + 0x2130) // NL2D R SIGMA S Register 4
#define ADDR_REG_NL2DRSIGMAS5              (ADDR_ISP_BASE + 0x2134) // NL2D R SIGMA S Register 5
#define ADDR_REG_NL2DRSIGMAS6              (ADDR_ISP_BASE + 0x2138) // NL2D R SIGMA S Register 6
#define ADDR_REG_NL2DRSIGMAS7              (ADDR_ISP_BASE + 0x213C) // NL2D R SIGMA S Register 7
#define ADDR_REG_NL2DGSIGMAS0              (ADDR_ISP_BASE + 0x2140) // NL2D G SIGMA S Register 0
#define ADDR_REG_NL2DGSIGMAS1              (ADDR_ISP_BASE + 0x2144) // NL2D G SIGMA S Register 1
#define ADDR_REG_NL2DGSIGMAS2              (ADDR_ISP_BASE + 0x2148) // NL2D G SIGMA S Register 2
#define ADDR_REG_NL2DGSIGMAS3              (ADDR_ISP_BASE + 0x214C) // NL2D G SIGMA S Register 3
#define ADDR_REG_NL2DGSIGMAS4              (ADDR_ISP_BASE + 0x2150) // NL2D G SIGMA S Register 4
#define ADDR_REG_NL2DGSIGMAS5              (ADDR_ISP_BASE + 0x2154) // NL2D G SIGMA S Register 5
#define ADDR_REG_NL2DGSIGMAS6              (ADDR_ISP_BASE + 0x2158) // NL2D G SIGMA S Register 6
#define ADDR_REG_NL2DGSIGMAS7              (ADDR_ISP_BASE + 0x215C) // NL2D G SIGMA S Register 7
#define ADDR_REG_NL2DBSIGMAS0              (ADDR_ISP_BASE + 0x2160) // NL2D B SIGMA S Register 0
#define ADDR_REG_NL2DBSIGMAS1              (ADDR_ISP_BASE + 0x2164) // NL2D B SIGMA S Register 1
#define ADDR_REG_NL2DBSIGMAS2              (ADDR_ISP_BASE + 0x2168) // NL2D B SIGMA S Register 2
#define ADDR_REG_NL2DBSIGMAS3              (ADDR_ISP_BASE + 0x216C) // NL2D B SIGMA S Register 3
#define ADDR_REG_NL2DBSIGMAS4              (ADDR_ISP_BASE + 0x2170) // NL2D B SIGMA S Register 4
#define ADDR_REG_NL2DBSIGMAS5              (ADDR_ISP_BASE + 0x2174) // NL2D B SIGMA S Register 5
#define ADDR_REG_NL2DBSIGMAS6              (ADDR_ISP_BASE + 0x2178) // NL2D B SIGMA S Register 6
#define ADDR_REG_NL2DBSIGMAS7              (ADDR_ISP_BASE + 0x217C) // NL2D B SIGMA S Register 7
#define ADDR_REG_NL2DRFILTPARX0            (ADDR_ISP_BASE + 0x2180) // NL2D R FILTPAR X Register 0
#define ADDR_REG_NL2DRFILTPARX1            (ADDR_ISP_BASE + 0x2184) // NL2D R FILTPAR X Register 1
#define ADDR_REG_NL2DRFILTPARX2            (ADDR_ISP_BASE + 0x2188) // NL2D R FILTPAR X Register 2
#define ADDR_REG_NL2DRFILTPARX3            (ADDR_ISP_BASE + 0x218C) // NL2D R FILTPAR X Register 3
#define ADDR_REG_NL2DRFILTPARX4            (ADDR_ISP_BASE + 0x2190) // NL2D R FILTPAR X Register 4
#define ADDR_REG_NL2DRFILTPARX5            (ADDR_ISP_BASE + 0x2194) // NL2D R FILTPAR X Register 5
#define ADDR_REG_NL2DRFILTPARX6            (ADDR_ISP_BASE + 0x2198) // NL2D R FILTPAR X Register 6
#define ADDR_REG_NL2DRFILTPARX7            (ADDR_ISP_BASE + 0x219C) // NL2D R FILTPAR X Register 7
#define ADDR_REG_NL2DGFILTPARX0            (ADDR_ISP_BASE + 0x21A0) // NL2D G FILTPAR X Register 0
#define ADDR_REG_NL2DGFILTPARX1            (ADDR_ISP_BASE + 0x21A4) // NL2D G FILTPAR X Register 1
#define ADDR_REG_NL2DGFILTPARX2            (ADDR_ISP_BASE + 0x21A8) // NL2D G FILTPAR X Register 2
#define ADDR_REG_NL2DGFILTPARX3            (ADDR_ISP_BASE + 0x21AC) // NL2D G FILTPAR X Register 3
#define ADDR_REG_NL2DGFILTPARX4            (ADDR_ISP_BASE + 0x21B0) // NL2D G FILTPAR X Register 4
#define ADDR_REG_NL2DGFILTPARX5            (ADDR_ISP_BASE + 0x21B4) // NL2D G FILTPAR X Register 5
#define ADDR_REG_NL2DGFILTPARX6            (ADDR_ISP_BASE + 0x21B8) // NL2D G FILTPAR X Register 6
#define ADDR_REG_NL2DGFILTPARX7            (ADDR_ISP_BASE + 0x21BC) // NL2D G FILTPAR X Register 7
#define ADDR_REG_NL2DBFILTPARX0            (ADDR_ISP_BASE + 0x21C0) // NL2D B FILTPAR X Register 0
#define ADDR_REG_NL2DBFILTPARX1            (ADDR_ISP_BASE + 0x21C4) // NL2D B FILTPAR X Register 1
#define ADDR_REG_NL2DBFILTPARX2            (ADDR_ISP_BASE + 0x21C8) // NL2D B FILTPAR X Register 2
#define ADDR_REG_NL2DBFILTPARX3            (ADDR_ISP_BASE + 0x21CC) // NL2D B FILTPAR X Register 3
#define ADDR_REG_NL2DBFILTPARX4            (ADDR_ISP_BASE + 0x21D0) // NL2D B FILTPAR X Register 4
#define ADDR_REG_NL2DBFILTPARX5            (ADDR_ISP_BASE + 0x21D4) // NL2D B FILTPAR X Register 5
#define ADDR_REG_NL2DBFILTPARX6            (ADDR_ISP_BASE + 0x21D8) // NL2D B FILTPAR X Register 6
#define ADDR_REG_NL2DBFILTPARX7            (ADDR_ISP_BASE + 0x21DC) // NL2D B FILTPAR X Register 7
#define ADDR_REG_NL2DRFILTPARY0            (ADDR_ISP_BASE + 0x21E0) // NL2D R FILTPAR Y Register 0
#define ADDR_REG_NL2DRFILTPARY1            (ADDR_ISP_BASE + 0x21E4) // NL2D R FILTPAR Y Register 1
#define ADDR_REG_NL2DRFILTPARY2            (ADDR_ISP_BASE + 0x21E8) // NL2D R FILTPAR Y Register 2
#define ADDR_REG_NL2DRFILTPARY3            (ADDR_ISP_BASE + 0x21EC) // NL2D R FILTPAR Y Register 3
#define ADDR_REG_NL2DRFILTPARY4            (ADDR_ISP_BASE + 0x21F0) // NL2D R FILTPAR Y Register 4
#define ADDR_REG_NL2DRFILTPARY5            (ADDR_ISP_BASE + 0x21F4) // NL2D R FILTPAR Y Register 5
#define ADDR_REG_NL2DRFILTPARY6            (ADDR_ISP_BASE + 0x21F8) // NL2D R FILTPAR Y Register 6
#define ADDR_REG_NL2DRFILTPARY7            (ADDR_ISP_BASE + 0x21FC) // NL2D R FILTPAR Y Register 7
#define ADDR_REG_NL2DRFILTPARY8            (ADDR_ISP_BASE + 0x2200) // NL2D R FILTPAR Y Register 8
#define ADDR_REG_NL2DRFILTPARY9            (ADDR_ISP_BASE + 0x2204) // NL2D R FILTPAR Y Register 9
#define ADDR_REG_NL2DRFILTPARY10           (ADDR_ISP_BASE + 0x2208) // NL2D R FILTPAR Y Register 10
#define ADDR_REG_NL2DRFILTPARY11           (ADDR_ISP_BASE + 0x220C) // NL2D R FILTPAR Y Register 11
#define ADDR_REG_NL2DRFILTPARY12           (ADDR_ISP_BASE + 0x2210) // NL2D R FILTPAR Y Register 12
#define ADDR_REG_NL2DRFILTPARY13           (ADDR_ISP_BASE + 0x2214) // NL2D R FILTPAR Y Register 13
#define ADDR_REG_NL2DRFILTPARY14           (ADDR_ISP_BASE + 0x2218) // NL2D R FILTPAR Y Register 14
#define ADDR_REG_NL2DRFILTPARY15           (ADDR_ISP_BASE + 0x221C) // NL2D R FILTPAR Y Register 15
#define ADDR_REG_NL2DGFILTPARY0            (ADDR_ISP_BASE + 0x2220) // NL2D G FILTPAR Y Register 0
#define ADDR_REG_NL2DGFILTPARY1            (ADDR_ISP_BASE + 0x2224) // NL2D G FILTPAR Y Register 1
#define ADDR_REG_NL2DGFILTPARY2            (ADDR_ISP_BASE + 0x2228) // NL2D G FILTPAR Y Register 2
#define ADDR_REG_NL2DGFILTPARY3            (ADDR_ISP_BASE + 0x222C) // NL2D G FILTPAR Y Register 3
#define ADDR_REG_NL2DGFILTPARY4            (ADDR_ISP_BASE + 0x2230) // NL2D G FILTPAR Y Register 4
#define ADDR_REG_NL2DGFILTPARY5            (ADDR_ISP_BASE + 0x2234) // NL2D G FILTPAR Y Register 5
#define ADDR_REG_NL2DGFILTPARY6            (ADDR_ISP_BASE + 0x2238) // NL2D G FILTPAR Y Register 6
#define ADDR_REG_NL2DGFILTPARY7            (ADDR_ISP_BASE + 0x223C) // NL2D G FILTPAR Y Register 7
#define ADDR_REG_NL2DGFILTPARY8            (ADDR_ISP_BASE + 0x2240) // NL2D G FILTPAR Y Register 8
#define ADDR_REG_NL2DGFILTPARY9            (ADDR_ISP_BASE + 0x2244) // NL2D G FILTPAR Y Register 9
#define ADDR_REG_NL2DGFILTPARY10           (ADDR_ISP_BASE + 0x2248) // NL2D G FILTPAR Y Register 10
#define ADDR_REG_NL2DGFILTPARY11           (ADDR_ISP_BASE + 0x224C) // NL2D G FILTPAR Y Register 11
#define ADDR_REG_NL2DGFILTPARY12           (ADDR_ISP_BASE + 0x2250) // NL2D G FILTPAR Y Register 12
#define ADDR_REG_NL2DGFILTPARY13           (ADDR_ISP_BASE + 0x2254) // NL2D G FILTPAR Y Register 13
#define ADDR_REG_NL2DGFILTPARY14           (ADDR_ISP_BASE + 0x2258) // NL2D G FILTPAR Y Register 14
#define ADDR_REG_NL2DGFILTPARY15           (ADDR_ISP_BASE + 0x225C) // NL2D G FILTPAR Y Register 15
#define ADDR_REG_NL2DBFILTPARY0            (ADDR_ISP_BASE + 0x2260) // NL2D B FILTPAR Y Register 0
#define ADDR_REG_NL2DBFILTPARY1            (ADDR_ISP_BASE + 0x2264) // NL2D B FILTPAR Y Register 1
#define ADDR_REG_NL2DBFILTPARY2            (ADDR_ISP_BASE + 0x2268) // NL2D B FILTPAR Y Register 2
#define ADDR_REG_NL2DBFILTPARY3            (ADDR_ISP_BASE + 0x226C) // NL2D B FILTPAR Y Register 3
#define ADDR_REG_NL2DBFILTPARY4            (ADDR_ISP_BASE + 0x2270) // NL2D B FILTPAR Y Register 4
#define ADDR_REG_NL2DBFILTPARY5            (ADDR_ISP_BASE + 0x2274) // NL2D B FILTPAR Y Register 5
#define ADDR_REG_NL2DBFILTPARY6            (ADDR_ISP_BASE + 0x2278) // NL2D B FILTPAR Y Register 6
#define ADDR_REG_NL2DBFILTPARY7            (ADDR_ISP_BASE + 0x227C) // NL2D B FILTPAR Y Register 7
#define ADDR_REG_NL2DBFILTPARY8            (ADDR_ISP_BASE + 0x2280) // NL2D B FILTPAR Y Register 8
#define ADDR_REG_NL2DBFILTPARY9            (ADDR_ISP_BASE + 0x2284) // NL2D B FILTPAR Y Register 9
#define ADDR_REG_NL2DBFILTPARY10           (ADDR_ISP_BASE + 0x2288) // NL2D B FILTPAR Y Register 10
#define ADDR_REG_NL2DBFILTPARY11           (ADDR_ISP_BASE + 0x228C) // NL2D B FILTPAR Y Register 11
#define ADDR_REG_NL2DBFILTPARY12           (ADDR_ISP_BASE + 0x2290) // NL2D B FILTPAR Y Register 12
#define ADDR_REG_NL2DBFILTPARY13           (ADDR_ISP_BASE + 0x2294) // NL2D B FILTPAR Y Register 13
#define ADDR_REG_NL2DBFILTPARY14           (ADDR_ISP_BASE + 0x2298) // NL2D B FILTPAR Y Register 14
#define ADDR_REG_NL2DBFILTPARY15           (ADDR_ISP_BASE + 0x229C) // NL2D B FILTPAR Y Register 15
#define ADDR_REG_NL2DRFILTPARS0            (ADDR_ISP_BASE + 0x22A0) // NL2D R FILTPAR S Register 0
#define ADDR_REG_NL2DRFILTPARS1            (ADDR_ISP_BASE + 0x22A4) // NL2D R FILTPAR S Register 1
#define ADDR_REG_NL2DRFILTPARS2            (ADDR_ISP_BASE + 0x22A8) // NL2D R FILTPAR S Register 2
#define ADDR_REG_NL2DRFILTPARS3            (ADDR_ISP_BASE + 0x22AC) // NL2D R FILTPAR S Register 3
#define ADDR_REG_NL2DRFILTPARS4            (ADDR_ISP_BASE + 0x22B0) // NL2D R FILTPAR S Register 4
#define ADDR_REG_NL2DRFILTPARS5            (ADDR_ISP_BASE + 0x22B4) // NL2D R FILTPAR S Register 5
#define ADDR_REG_NL2DRFILTPARS6            (ADDR_ISP_BASE + 0x22B8) // NL2D R FILTPAR S Register 6
#define ADDR_REG_NL2DRFILTPARS7            (ADDR_ISP_BASE + 0x22BC) // NL2D R FILTPAR S Register 7
#define ADDR_REG_NL2DGFILTPARS0            (ADDR_ISP_BASE + 0x22C0) // NL2D G FILTPAR S Register 0
#define ADDR_REG_NL2DGFILTPARS1            (ADDR_ISP_BASE + 0x22C4) // NL2D G FILTPAR S Register 1
#define ADDR_REG_NL2DGFILTPARS2            (ADDR_ISP_BASE + 0x22C8) // NL2D G FILTPAR S Register 2
#define ADDR_REG_NL2DGFILTPARS3            (ADDR_ISP_BASE + 0x22CC) // NL2D G FILTPAR S Register 3
#define ADDR_REG_NL2DGFILTPARS4            (ADDR_ISP_BASE + 0x22D0) // NL2D G FILTPAR S Register 4
#define ADDR_REG_NL2DGFILTPARS5            (ADDR_ISP_BASE + 0x22D4) // NL2D G FILTPAR S Register 5
#define ADDR_REG_NL2DGFILTPARS6            (ADDR_ISP_BASE + 0x22D8) // NL2D G FILTPAR S Register 6
#define ADDR_REG_NL2DGFILTPARS7            (ADDR_ISP_BASE + 0x22DC) // NL2D G FILTPAR S Register 7
#define ADDR_REG_NL2DBFILTPARS0            (ADDR_ISP_BASE + 0x22E0) // NL2D B FILTPAR S Register 0
#define ADDR_REG_NL2DBFILTPARS1            (ADDR_ISP_BASE + 0x22E4) // NL2D B FILTPAR S Register 1
#define ADDR_REG_NL2DBFILTPARS2            (ADDR_ISP_BASE + 0x22E8) // NL2D B FILTPAR S Register 2
#define ADDR_REG_NL2DBFILTPARS3            (ADDR_ISP_BASE + 0x22EC) // NL2D B FILTPAR S Register 3
#define ADDR_REG_NL2DBFILTPARS4            (ADDR_ISP_BASE + 0x22F0) // NL2D B FILTPAR S Register 4
#define ADDR_REG_NL2DBFILTPARS5            (ADDR_ISP_BASE + 0x22F4) // NL2D B FILTPAR S Register 5
#define ADDR_REG_NL2DBFILTPARS6            (ADDR_ISP_BASE + 0x22F8) // NL2D B FILTPAR S Register 6
#define ADDR_REG_NL2DBFILTPARS7            (ADDR_ISP_BASE + 0x22FC) // NL2D B FILTPAR S Register 7
#define ADDR_REG_NL2DCFG                   (ADDR_ISP_BASE + 0x2300) // NL2D CFG Register
#define ADDR_REG_NWEDYS1THX0               (ADDR_ISP_BASE + 0x2400) // NWED Y Channel S1 Threshold X Register 0
#define ADDR_REG_NWEDYS1THX1               (ADDR_ISP_BASE + 0x2404) // NWED Y Channel S1Threshold X Register 1
#define ADDR_REG_NWEDYS1THX2               (ADDR_ISP_BASE + 0x2408) // NWED Y Channel S1 Threshold X Register 2
#define ADDR_REG_NWEDYS1THX3               (ADDR_ISP_BASE + 0x240C) // NWED Y Channel S1 Threshold X Register 3
#define ADDR_REG_NWEDYS1THX4               (ADDR_ISP_BASE + 0x2410) // NWED Y Channel S1 Threshold X Register 4
#define ADDR_REG_NWEDYS1THX5               (ADDR_ISP_BASE + 0x2414) // NWED Y Channel S1 Threshold X Register 5
#define ADDR_REG_NWEDYS1THX6               (ADDR_ISP_BASE + 0x2418) // NWED Y Channel S1 Threshold X Register 6
#define ADDR_REG_NWEDYS1THX7               (ADDR_ISP_BASE + 0x241C) // NWED Y Channel S1 Threshold X Register 7
#define ADDR_REG_NWEDYS6THX0               (ADDR_ISP_BASE + 0x2420) // NWED Y Channel S6 Threshold X Register 0
#define ADDR_REG_NWEDYS6THX1               (ADDR_ISP_BASE + 0x2424) // NWED Y Channel S6 Threshold X Register 1
#define ADDR_REG_NWEDYS6THX2               (ADDR_ISP_BASE + 0x2428) // NWED Y Channel S6 Threshold X Register 2
#define ADDR_REG_NWEDYS6THX3               (ADDR_ISP_BASE + 0x242C) // NWED Y Channel S6 Threshold X Register 3
#define ADDR_REG_NWEDYS6THX4               (ADDR_ISP_BASE + 0x2430) // NWED Y Channel S6 Threshold X Register 4
#define ADDR_REG_NWEDYS6THX5               (ADDR_ISP_BASE + 0x2434) // NWED Y Channel S6 Threshold X Register 5
#define ADDR_REG_NWEDYS6THX6               (ADDR_ISP_BASE + 0x2438) // NWED Y Channel S6 Threshold X Register 6
#define ADDR_REG_NWEDYS6THX7               (ADDR_ISP_BASE + 0x243C) // NWED Y Channel S6 Threshold X Register 7
#define ADDR_REG_NWEDUVS1THX0              (ADDR_ISP_BASE + 0x2440) // NWED UV Channel S1 Threshold X Register 0
#define ADDR_REG_NWEDUVS1THX1              (ADDR_ISP_BASE + 0x2444) // NWED UV Channel S1 Threshold X Register 1
#define ADDR_REG_NWEDUVS1THX2              (ADDR_ISP_BASE + 0x2448) // NWED UV  S1 Threshold X Register 2
#define ADDR_REG_NWEDUVS1THX3              (ADDR_ISP_BASE + 0x244C) // NWED UV  S1 Threshold X Register 3
#define ADDR_REG_NWEDUVS1THX4              (ADDR_ISP_BASE + 0x2450) // NWED UV Channel S1 Threshold X Register 4
#define ADDR_REG_NWEDUVS1THX5              (ADDR_ISP_BASE + 0x2454) // NWED UV  S1 Threshold X Register 5
#define ADDR_REG_NWEDUVS1THX6              (ADDR_ISP_BASE + 0x2458) // NWED UV  S1 Threshold X Register 6
#define ADDR_REG_NWEDUVS1THX7              (ADDR_ISP_BASE + 0x245C) // NWED UV Channel S1 Threshold X Register 7
#define ADDR_REG_NWEDUVS6THX0              (ADDR_ISP_BASE + 0x2460) // NWED UV  S6 Threshold X Register 0
#define ADDR_REG_NWEDUVS6THX1              (ADDR_ISP_BASE + 0x2464) // NWED UV  S6 Threshold X Register 1
#define ADDR_REG_NWEDUVS6THX2              (ADDR_ISP_BASE + 0x2468) // NWED UV Channel S6 Threshold X Register 2
#define ADDR_REG_NWEDUVS6THX3              (ADDR_ISP_BASE + 0x246C) // NWED UV Channel S6 Threshold X Register 3
#define ADDR_REG_NWEDUVS6THX4              (ADDR_ISP_BASE + 0x2470) // NWED UV Channel S6 Threshold X Register 4
#define ADDR_REG_NWEDUVS6THX5              (ADDR_ISP_BASE + 0x2474) // NWED UV Channel S6 Threshold X Register 5
#define ADDR_REG_NWEDUVS6THX6              (ADDR_ISP_BASE + 0x2478) // NWED UV Channel S6 Threshold X Register 6
#define ADDR_REG_NWEDUVS6THX7              (ADDR_ISP_BASE + 0x247C) // NWED UV Channel S6 Threshold X Register 7
#define ADDR_REG_NWEDYS1THY0               (ADDR_ISP_BASE + 0x2480) // NWED Y Channel S1 Threshold Y Register 0
#define ADDR_REG_NWEDYS1THY1               (ADDR_ISP_BASE + 0x2484) // NWED Y Channel S1 Threshold Y Register 1
#define ADDR_REG_NWEDYS1THY2               (ADDR_ISP_BASE + 0x2488) // NWED Y Channel S1 Threshold Y Register 2
#define ADDR_REG_NWEDYS1THY3               (ADDR_ISP_BASE + 0x248C) // NWED Y Channel S1 Threshold Y Register 3
#define ADDR_REG_NWEDYS1THY4               (ADDR_ISP_BASE + 0x2490) // NWED Y Channel S1 Threshold Y Register 4
#define ADDR_REG_NWEDYS1THY5               (ADDR_ISP_BASE + 0x2494) // NWED Y Channel S1 Threshold Y Register 5
#define ADDR_REG_NWEDYS1THY6               (ADDR_ISP_BASE + 0x2498) // NWED Y Channel S1 Threshold Y Register 6
#define ADDR_REG_NWEDYS1THY7               (ADDR_ISP_BASE + 0x249C) // NWED Y Channel S1 Threshold Y Register 7
#define ADDR_REG_NWEDYS6THY0               (ADDR_ISP_BASE + 0x24A0) // NWED Y Channel S6 Threshold Y Register 0
#define ADDR_REG_NWEDYS6THY1               (ADDR_ISP_BASE + 0x24A4) // NWED Y Channel S6 Threshold Y Register 1
#define ADDR_REG_NWEDYS6THY2               (ADDR_ISP_BASE + 0x24A8) // NWED Y Channel S6 Threshold Y Register 2
#define ADDR_REG_NWEDYS6THY3               (ADDR_ISP_BASE + 0x24AC) // NWED Y Channel S6 Threshold Y Register 3
#define ADDR_REG_NWEDYS6THY4               (ADDR_ISP_BASE + 0x24B0) // NWED Y Channel S6 Threshold Y Register 4
#define ADDR_REG_NWEDYS6THY5               (ADDR_ISP_BASE + 0x24B4) // NWED Y Channel S6 Threshold Y Register 5
#define ADDR_REG_NWEDYS6THY6               (ADDR_ISP_BASE + 0x24B8) // NWED Y Channel S6 Threshold Y Register 6
#define ADDR_REG_NWEDYS6THY7               (ADDR_ISP_BASE + 0x24BC) // NWED Y Channel S6 Threshold Y Register 7
#define ADDR_REG_NWEDUVS1THY0              (ADDR_ISP_BASE + 0x24C0) // NWED UV ChannelS1 Threshold Y Register 0
#define ADDR_REG_NWEDUVS1THY1              (ADDR_ISP_BASE + 0x24C4) // NWED UV Channel S1 Threshold Y Register 1
#define ADDR_REG_NWEDUVS1THY2              (ADDR_ISP_BASE + 0x24C8) // NWED UV Channel S1 Threshold Y Register 2
#define ADDR_REG_NWEDUVS1THY3              (ADDR_ISP_BASE + 0x24CC) // NWED UV Channel S1 Threshold Y Register 3
#define ADDR_REG_NWEDUVS1THY4              (ADDR_ISP_BASE + 0x24D0) // NWED UV Channel S1 Threshold Y Register 4
#define ADDR_REG_NWEDUVS1THY5              (ADDR_ISP_BASE + 0x24D4) // NWED UV Channel S1 Threshold Y Register 5
#define ADDR_REG_NWEDUVS1THY6              (ADDR_ISP_BASE + 0x24D8) // NWED UV Channel S1 Threshold Y Register 6
#define ADDR_REG_NWEDUVS1THY7              (ADDR_ISP_BASE + 0x24DC) // NWED UV Channel S1 Threshold Y Register 7
#define ADDR_REG_NWEDUVS6THY0              (ADDR_ISP_BASE + 0x24E0) // NWED UV ChannelS6 Threshold Y Register 0
#define ADDR_REG_NWEDUVS6THY1              (ADDR_ISP_BASE + 0x24E4) // NWED UV Channel S6 Threshold Y Register 1
#define ADDR_REG_NWEDUVS6THY2              (ADDR_ISP_BASE + 0x24E8) // NWED UV Channel S6 Threshold Y Register 2
#define ADDR_REG_NWEDUVS6THY3              (ADDR_ISP_BASE + 0x24EC) // NWED UV Channel S6 Threshold Y Register 3
#define ADDR_REG_NWEDUVS6THY4              (ADDR_ISP_BASE + 0x24F0) // NWED UV Channel S6 Threshold Y Register 4
#define ADDR_REG_NWEDUVS6THY5              (ADDR_ISP_BASE + 0x24F4) // NWED UV Channel S6 Threshold Y Register 5
#define ADDR_REG_NWEDUVS6THY6              (ADDR_ISP_BASE + 0x24F8) // NWED UV Channel S6 Threshold Y Register 6
#define ADDR_REG_NWEDUVS6THY7              (ADDR_ISP_BASE + 0x24FC) // NWED UV Channel S6 Threshold Y Register 7
#define ADDR_REG_NWEDYS1THS0               (ADDR_ISP_BASE + 0x2500) // NWED Y Channel S1 Threshold S Register 0
#define ADDR_REG_NWEDYS1THS1               (ADDR_ISP_BASE + 0x2504) // NWED Y Channel S1 Threshold S Register 1
#define ADDR_REG_NWEDYS1THS2               (ADDR_ISP_BASE + 0x2508) // NWED Y Channel S1 Threshold S Register 2
#define ADDR_REG_NWEDYS1THS3               (ADDR_ISP_BASE + 0x250C) // NWED Y Channel S1 Threshold S Register 3
#define ADDR_REG_NWEDYS1THS4               (ADDR_ISP_BASE + 0x2510) // NWED Y Channel S1 Threshold S Register 4
#define ADDR_REG_NWEDYS1THS5               (ADDR_ISP_BASE + 0x2514) // NWED Y Channel S1 Threshold S Register 5
#define ADDR_REG_NWEDYS1THS6               (ADDR_ISP_BASE + 0x2518) // NWED Y Channel S1 Threshold S Register 6
#define ADDR_REG_NWEDYS1THS7               (ADDR_ISP_BASE + 0x251C) // NWED Y Channel S1 Threshold S Register 7
#define ADDR_REG_NWEDYS6THS0               (ADDR_ISP_BASE + 0x2520) // NWED Y Channel S6 Threshold S Register 0
#define ADDR_REG_NWEDYS6THS1               (ADDR_ISP_BASE + 0x2524) // NWED Y Channel S6 Threshold S Register 1
#define ADDR_REG_NWEDYS6THS2               (ADDR_ISP_BASE + 0x2528) // NWED Y Channel S6 Threshold S Register 2
#define ADDR_REG_NWEDYS6THS3               (ADDR_ISP_BASE + 0x252C) // NWED Y Channel S6 Threshold S Register 3
#define ADDR_REG_NWEDYS6THS4               (ADDR_ISP_BASE + 0x2530) // NWED Y Channel S6 Threshold S Register 4
#define ADDR_REG_NWEDYS6THS5               (ADDR_ISP_BASE + 0x2534) // NWED Y Channel S6 Threshold S Register 5
#define ADDR_REG_NWEDYS6THS6               (ADDR_ISP_BASE + 0x2538) // NWED Y Channel S6 Threshold S Register 6
#define ADDR_REG_NWEDYS6THS7               (ADDR_ISP_BASE + 0x253C) // NWED Y Channel S6 Threshold S Register 7
#define ADDR_REG_NWEDUVS1THS0              (ADDR_ISP_BASE + 0x2540) // NWED UV Channel S1 Threshold S Register 0
#define ADDR_REG_NWEDUVS1THS1              (ADDR_ISP_BASE + 0x2544) // NWED UV Channel S1 Threshold S Register 1
#define ADDR_REG_NWEDUVS1THS2              (ADDR_ISP_BASE + 0x2548) // NWED UV Channel S1 Threshold S Register 2
#define ADDR_REG_NWEDUVS1THS3              (ADDR_ISP_BASE + 0x254C) // NWED UV Channel S1 Threshold S Register 3
#define ADDR_REG_NWEDUVS1THS4              (ADDR_ISP_BASE + 0x2550) // NWED UV Channel S1 Threshold S Register 4
#define ADDR_REG_NWEDUVS1THS5              (ADDR_ISP_BASE + 0x2554) // NWED UV Channel S1 Threshold S Register 5
#define ADDR_REG_NWEDUVS1THS6              (ADDR_ISP_BASE + 0x2558) // NWED UV Channel S1 Threshold S Register 6
#define ADDR_REG_NWEDUVS1THS7              (ADDR_ISP_BASE + 0x255C) // NWED UV Channel S1 Threshold S Register 7
#define ADDR_REG_NWEDUVS6THS0              (ADDR_ISP_BASE + 0x2560) // NWED UV Channel S6 Threshold S Register 0
#define ADDR_REG_NWEDUVS6THS1              (ADDR_ISP_BASE + 0x2564) // NWED UV Channel S6 Threshold S Register 1
#define ADDR_REG_NWEDUVS6THS2              (ADDR_ISP_BASE + 0x2568) // NWED UV Channel S6 Threshold S Register 2
#define ADDR_REG_NWEDUVS6THS3              (ADDR_ISP_BASE + 0x256C) // NWED UV Channel S6 Threshold S Register 3
#define ADDR_REG_NWEDUVS6THS4              (ADDR_ISP_BASE + 0x2570) // NWED UV Channel S6 Threshold S Register 4
#define ADDR_REG_NWEDUVS6THS5              (ADDR_ISP_BASE + 0x2574) // NWED UV Channel S6 Threshold S Register 5
#define ADDR_REG_NWEDUVS6THS6              (ADDR_ISP_BASE + 0x2578) // NWED UV Channel S6 Threshold S Register 6
#define ADDR_REG_NWEDUVS6THS7              (ADDR_ISP_BASE + 0x257C) // NWED UV Channel S6 Threshold S Register 7
#define ADDR_REG_NWEDDS0                   (ADDR_ISP_BASE + 0x2580) // NWED DS Register 0
#define ADDR_REG_NWEDDS1                   (ADDR_ISP_BASE + 0x2584) // NWED DS Register 1
#define ADDR_REG_OBCO_CFG_4                (ADDR_ISP_BASE + 0x3030) // each symbol has four point, each point has one 6~10bit(PW-4) offset register
#define ADDR_REG_OBCO_CFG_5                (ADDR_ISP_BASE + 0x3034) // each symbol has four point, each point has one 6~10bit(PW-4) offset register
#define ADDR_REG_OBCO_CFG_6                (ADDR_ISP_BASE + 0x3038) // each symbol has four point, each point has one 6~10bit(PW-4) offset register
#define ADDR_REG_OBCO_CFG_7                (ADDR_ISP_BASE + 0x303C) // each symbol has four point, each point has one 6~10bit(PW-4) offset register
#define ADDR_REG_OECFC_X0_CFG_0            (ADDR_ISP_BASE + 0x3200) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X0_CFG_1            (ADDR_ISP_BASE + 0x3204) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X0_CFG_2            (ADDR_ISP_BASE + 0x3208) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X0_CFG_3            (ADDR_ISP_BASE + 0x320C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X0_CFG_4            (ADDR_ISP_BASE + 0x3210) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X0_CFG_5            (ADDR_ISP_BASE + 0x3214) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X0_CFG_6            (ADDR_ISP_BASE + 0x3218) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X0_CFG_7            (ADDR_ISP_BASE + 0x321C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_X1_CFG_0            (ADDR_ISP_BASE + 0x3220) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X1_CFG_1            (ADDR_ISP_BASE + 0x3224) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X1_CFG_2            (ADDR_ISP_BASE + 0x3228) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X1_CFG_3            (ADDR_ISP_BASE + 0x322C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X1_CFG_4            (ADDR_ISP_BASE + 0x3230) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X1_CFG_5            (ADDR_ISP_BASE + 0x3234) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X1_CFG_6            (ADDR_ISP_BASE + 0x3238) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X1_CFG_7            (ADDR_ISP_BASE + 0x323C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_X2_CFG_0            (ADDR_ISP_BASE + 0x3240) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X2_CFG_1            (ADDR_ISP_BASE + 0x3244) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X2_CFG_2            (ADDR_ISP_BASE + 0x3248) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X2_CFG_3            (ADDR_ISP_BASE + 0x324C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X2_CFG_4            (ADDR_ISP_BASE + 0x3250) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X2_CFG_5            (ADDR_ISP_BASE + 0x3254) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X2_CFG_6            (ADDR_ISP_BASE + 0x3258) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X2_CFG_7            (ADDR_ISP_BASE + 0x325C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_X3_CFG_0            (ADDR_ISP_BASE + 0x3260) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_X3_CFG_1            (ADDR_ISP_BASE + 0x3264) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_X3_CFG_2            (ADDR_ISP_BASE + 0x3268) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_X3_CFG_3            (ADDR_ISP_BASE + 0x326C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_X3_CFG_4            (ADDR_ISP_BASE + 0x3270) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_X3_CFG_5            (ADDR_ISP_BASE + 0x3274) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_X3_CFG_6            (ADDR_ISP_BASE + 0x3278) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_X3_CFG_7            (ADDR_ISP_BASE + 0x327C) // OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y0_CFG_0            (ADDR_ISP_BASE + 0x3280) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y0_CFG_1            (ADDR_ISP_BASE + 0x3284) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y0_CFG_2            (ADDR_ISP_BASE + 0x3288) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y0_CFG_3            (ADDR_ISP_BASE + 0x328C) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y0_CFG_4            (ADDR_ISP_BASE + 0x3290) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y0_CFG_5            (ADDR_ISP_BASE + 0x3294) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y0_CFG_6            (ADDR_ISP_BASE + 0x3298) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y0_CFG_7            (ADDR_ISP_BASE + 0x329C) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
#define ADDR_REG_OECFC_Y1_CFG_0            (ADDR_ISP_BASE + 0x32A0) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y1_CFG_1            (ADDR_ISP_BASE + 0x32A4) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y1_CFG_2            (ADDR_ISP_BASE + 0x32A8) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y1_CFG_3            (ADDR_ISP_BASE + 0x32AC) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y1_CFG_4            (ADDR_ISP_BASE + 0x32B0) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y1_CFG_5            (ADDR_ISP_BASE + 0x32B4) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y1_CFG_6            (ADDR_ISP_BASE + 0x32B8) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y1_CFG_7            (ADDR_ISP_BASE + 0x32BC) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
#define ADDR_REG_OECFC_Y2_CFG_0            (ADDR_ISP_BASE + 0x32C0) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y2_CFG_1            (ADDR_ISP_BASE + 0x32C4) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y2_CFG_2            (ADDR_ISP_BASE + 0x32C8) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y2_CFG_3            (ADDR_ISP_BASE + 0x32CC) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y2_CFG_4            (ADDR_ISP_BASE + 0x32D0) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y2_CFG_5            (ADDR_ISP_BASE + 0x32D4) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y2_CFG_6            (ADDR_ISP_BASE + 0x32D8) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y2_CFG_7            (ADDR_ISP_BASE + 0x32DC) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
#define ADDR_REG_OECFC_Y3_CFG_0            (ADDR_ISP_BASE + 0x32E0) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y3_CFG_1            (ADDR_ISP_BASE + 0x32E4) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y3_CFG_2            (ADDR_ISP_BASE + 0x32E8) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y3_CFG_3            (ADDR_ISP_BASE + 0x32EC) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y3_CFG_4            (ADDR_ISP_BASE + 0x32F0) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y3_CFG_5            (ADDR_ISP_BASE + 0x32F4) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y3_CFG_6            (ADDR_ISP_BASE + 0x32F8) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_Y3_CFG_7            (ADDR_ISP_BASE + 0x32FC) // OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
#define ADDR_REG_OECFC_S0_CFG_0            (ADDR_ISP_BASE + 0x3300) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S0_CFG_1            (ADDR_ISP_BASE + 0x3304) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S0_CFG_2            (ADDR_ISP_BASE + 0x3308) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S0_CFG_3            (ADDR_ISP_BASE + 0x330C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S0_CFG_4            (ADDR_ISP_BASE + 0x3310) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S0_CFG_5            (ADDR_ISP_BASE + 0x3314) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S0_CFG_6            (ADDR_ISP_BASE + 0x3318) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S0_CFG_7            (ADDR_ISP_BASE + 0x331C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
#define ADDR_REG_OECFC_S1_CFG_0            (ADDR_ISP_BASE + 0x3320) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S1_CFG_1            (ADDR_ISP_BASE + 0x3324) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S1_CFG_2            (ADDR_ISP_BASE + 0x3328) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S1_CFG_3            (ADDR_ISP_BASE + 0x332C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S1_CFG_4            (ADDR_ISP_BASE + 0x3330) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S1_CFG_5            (ADDR_ISP_BASE + 0x3334) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S1_CFG_6            (ADDR_ISP_BASE + 0x3338) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S1_CFG_7            (ADDR_ISP_BASE + 0x333C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
#define ADDR_REG_OECFC_S2_CFG_0            (ADDR_ISP_BASE + 0x3340) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S2_CFG_1            (ADDR_ISP_BASE + 0x3344) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S2_CFG_2            (ADDR_ISP_BASE + 0x3348) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S2_CFG_3            (ADDR_ISP_BASE + 0x334C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S2_CFG_4            (ADDR_ISP_BASE + 0x3350) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S2_CFG_5            (ADDR_ISP_BASE + 0x3354) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S2_CFG_6            (ADDR_ISP_BASE + 0x3358) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S2_CFG_7            (ADDR_ISP_BASE + 0x335C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
#define ADDR_REG_OECFC_S3_CFG_0            (ADDR_ISP_BASE + 0x3360) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_OECFC_S3_CFG_1            (ADDR_ISP_BASE + 0x3364) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_OECFC_S3_CFG_2            (ADDR_ISP_BASE + 0x3368) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_OECFC_S3_CFG_3            (ADDR_ISP_BASE + 0x336C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_OECFC_S3_CFG_4            (ADDR_ISP_BASE + 0x3370) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_OECFC_S3_CFG_5            (ADDR_ISP_BASE + 0x3374) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_OECFC_S3_CFG_6            (ADDR_ISP_BASE + 0x3378) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_OECFC_S3_CFG_7            (ADDR_ISP_BASE + 0x337C) // OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
#define ADDR_REG_SC1_CFG_0                 (ADDR_ISP_BASE + 0x3810) // sc1 frame cropping for sc ae/af
#define ADDR_REG_SC1_CFG_1                 (ADDR_ISP_BASE + 0x3814) // SC1 cfg1 register
#define ADDR_REG_SC1_DEC                   (ADDR_ISP_BASE + 0x3818) // sc1 dec cfg register for sc ae/af, Horizontal/Vertical period/keep
#define ADDR_REG_SC0_CFG_0                 (ADDR_ISP_BASE + 0x3820) // sc0 frame cropping for sc awb
#define ADDR_REG_SC0_CFG_1                 (ADDR_ISP_BASE + 0x3824) // SC0 cfg1 register
#define ADDR_REG_SC0_DEC                   (ADDR_ISP_BASE + 0x3828) // sc0 dec cfg register for sc awb, Horizontal/Vertical period/keep
#define ADDR_REG_CLKGCFG                   (ADDR_ISP_BASE + 0x400C) // module clock gate config register
#define ADDR_REG_SENSORSZ                  (ADDR_ISP_BASE + 0x4028) // Sensor X/Y size
#define ADDR_REG_PMIMR                     (ADDR_ISP_BASE + 0x403C) // Pipeline module interrupt mux register
#define ADDR_REG_ISPINTEN                  (ADDR_ISP_BASE + 0x404C) // ISP Interrupt Enable Register 
#define ADDR_REG_ITIFBC0                   (ADDR_ISP_BASE + 0x4060) // Tiling FBC control0 regsiter
#define ADDR_REG_ITIFBC1                   (ADDR_ISP_BASE + 0x4064) // Tiling FBC control1 regsiter
#define ADDR_REG_ITIDEC0                   (ADDR_ISP_BASE + 0x4068) // tiling write0 DEC register, Horizontal/Vertical period/keep
#define ADDR_REG_ITIDEC1                   (ADDR_ISP_BASE + 0x406C) // tiling write1 DEC register, Horizontal/Vertical period/keep
#define ADDR_REG_ITICROP0                  (ADDR_ISP_BASE + 0x4070) // tiling write 0 cropping register (x/y start location)
#define ADDR_REG_ITICROP1                  (ADDR_ISP_BASE + 0x4074) // tiling write 0 cropping register (x/y end location)
#define ADDR_REG_ITICROP2                  (ADDR_ISP_BASE + 0x4078) // tiling write 1 cropping register (x/y start location)
#define ADDR_REG_ITICROP3                  (ADDR_ISP_BASE + 0x407C) // tiling write 1 cropping register (x/y end location)
#define ADDR_REG_ITIIWSR__                 (ADDR_ISP_BASE + 0x4080) // ITI write 0 Image Window Size Register
#define ADDR_REG_ITIRWSR__                 (ADDR_ISP_BASE + 0x4084) // ITI read Image Window Size Register
#define ADDR_REG_ITIDWLSR__                (ADDR_ISP_BASE + 0x4088) // ITI DRAM WRITE Line Stride Register, 64bit align,
#define ADDR_REG_ITIDRLSR__                (ADDR_ISP_BASE + 0x408C) // ITI DRAM READ Line Stride Register, 64bit align, 
#define ADDR_REG_ITIDWYSAR0__              (ADDR_ISP_BASE + 0x4090) // ITI DRAM Write Y Start Address 0 Register, 64bit align
#define ADDR_REG_ITIDWUSAR0__              (ADDR_ISP_BASE + 0x4094) // ITI DRAM Write UV Start Address 0 Register, 64bit align
#define ADDR_REG_ITIDRYSAR0__              (ADDR_ISP_BASE + 0x4098) // ITI DRAM Read Y Start Address 0  Register, 64bit align
#define ADDR_REG_ITIDRUSAR0__              (ADDR_ISP_BASE + 0x409C) // ITI DRAM Read UV Start Address 0  Register, 64bit align
#define ADDR_REG_ITIBSR__                  (ADDR_ISP_BASE + 0x40A0) // ISP Tiling Interface BUSY Status Register
#define ADDR_REG_ITIWRDFR__                (ADDR_ISP_BASE + 0x40A4) // ITI Write Data Format  Register
#define ADDR_REG_ITIRDDFR__                (ADDR_ISP_BASE + 0x40A8) // ITI  Read Data Format  Register
#define ADDR_REG_ITIDPSR__                 (ADDR_ISP_BASE + 0x40AC) // ISP Tiling Interface  Data Path Select Register
#define ADDR_REG_ITIDWYSAR1__              (ADDR_ISP_BASE + 0x40B0) // ITI DRAM Write Y Start Address 1 Register, 64bit align
#define ADDR_REG_ITIDWUSAR1__              (ADDR_ISP_BASE + 0x40B4) // ITI DRAM Write UV Start Address 1 Register, 64bit align
#define ADDR_REG_ITIDWYSAR2__              (ADDR_ISP_BASE + 0x40B8) // ITI DRAM Write Y Start Address 2 Register, 64bit align
#define ADDR_REG_ITIDWUSAR2__              (ADDR_ISP_BASE + 0x40BC) // ITI DRAM Write UV Start Address 2 Register, 64bit align
#define ADDR_REG_ITIDWYSAR3__              (ADDR_ISP_BASE + 0x40C0) // ITI DRAM Write Y Start Address 3 Register, 64bit align
#define ADDR_REG_ITIDWUSAR3__              (ADDR_ISP_BASE + 0x40C4) // ITI DRAM Write UV Start Address 3 Register, 64bit align
#define ADDR_REG_ITIDRYSAR1__              (ADDR_ISP_BASE + 0x40C8) // ITI DRAM Read Y Start Address 1 Register, 64bit align
#define ADDR_REG_ITIDRUSAR1__              (ADDR_ISP_BASE + 0x40CC) // ITI DRAM Read UV Start Address 1  Register, 64bit align
#define ADDR_REG_ITIDRYSAR2__              (ADDR_ISP_BASE + 0x40D0) // ITI DRAM Read Y Start Address 2 Register, 64bit align
#define ADDR_REG_ITIDRUSAR2__              (ADDR_ISP_BASE + 0x40D4) // ITI DRAM Read UV Start Address 2  Register, 64bit align
#define ADDR_REG_ITIDRYSAR3__              (ADDR_ISP_BASE + 0x40D8) // ITI DRAM Read Y Start Address 3 Register, 64bit align
#define ADDR_REG_ITIDRUSAR3__              (ADDR_ISP_BASE + 0x40DC) // ITI DRAM Read UV Start Address 3  Register, 64bit align
#define ADDR_REG_ITICIWSR__                (ADDR_ISP_BASE + 0x40E0) // ITI Capture Image Window Size Register
#define ADDR_REG_ITICWLSR__                (ADDR_ISP_BASE + 0x40E4) // ITI Capture WRITE Line Stride Register, 64bit align, 
#define ADDR_REG_ITICWYSAR0__              (ADDR_ISP_BASE + 0x40E8) // ITI Capture Write Start Address 0 Register, 64bit align
#define ADDR_REG_ITICWYSAR1__              (ADDR_ISP_BASE + 0x40EC) // ITI Capture Write Start Address 1  Register, 64bit align
#define ADDR_REG_ITICWYSAR2__              (ADDR_ISP_BASE + 0x40F0) // ITI Capture Write Start Address 2  Register, 64bit align
#define ADDR_REG_ITICWYSAR3__              (ADDR_ISP_BASE + 0x40F4) // ITI Capture Write Start Address 3  Register, 64bit align
#define ADDR_REG_ITICPDFR__                (ADDR_ISP_BASE + 0x40F8) // ITI  Capture Package Data Format  Register
#define ADDR_REG_ITICDPSR__                (ADDR_ISP_BASE + 0x40FC) // ITI Capture  Data Path Select Register
#define ADDR_REG_DC_RBADR                  (ADDR_ISP_BASE + 0x4104) // DC Return Buffer Address register
#define ADDR_REG_IGRGB0                    (ADDR_ISP_BASE + 0x4120) // GrGb Filter Mode Register
#define ADDR_REG_IGRGB1                    (ADDR_ISP_BASE + 0x4124) // GrGb Filter threshold 1 Register
#define ADDR_REG_IGRGB2                    (ADDR_ISP_BASE + 0x4128) // GrGb filter threshold 2 Register
#define ADDR_REG_ISLS0                     (ADDR_ISP_BASE + 0x4150) // Lens shading Control 0 register
#define ADDR_REG_ISLSGBA                   (ADDR_ISP_BASE + 0x4154) // Lens Shading Grid Buffer Start Address Register, 64bit align
#define ADDR_REG_ISLSGBS                   (ADDR_ISP_BASE + 0x4158) // Lens Shading Grid Buffer Stride Register
#define ADDR_REG_ISLSEGC                   (ADDR_ISP_BASE + 0x415C) // Lens Shading Eliptic Gating Center Register,CX/CY,each 13bits
#define ADDR_REG_ISLSEGSX                  (ADDR_ISP_BASE + 0x4160) // Lens Shading Eliptic Gating Semi Axis X Register
#define ADDR_REG_ISLSEGSY                  (ADDR_ISP_BASE + 0x4164) // Lens Shading Eliptic Gating Semi Axis Y Register
#define ADDR_REG_ISLSEGW                   (ADDR_ISP_BASE + 0x4168) // Lens Shading Eliptic Gating Center Width Register
#define ADDR_REG_ISLSMRD                   (ADDR_ISP_BASE + 0x416C) // Lens Shading Memory Read Register, axi burst len , fifo threshold (remove id)
#define ADDR_REG_WDR_HOR                   (ADDR_ISP_BASE + 0x4280) // WDR HO register, the offsets of the 1st local window from image top-left corner
#define ADDR_REG_WDR_LWR                   (ADDR_ISP_BASE + 0x4284) // WDR local window  register
#define ADDR_REG_WDR_THR0                  (ADDR_ISP_BASE + 0x4288) // WDR level0 window threshold regiser
#define ADDR_REG_WDR_SCR                   (ADDR_ISP_BASE + 0x428C) // WDR scale regiser
#define ADDR_REG_WDR_IBADDR0               (ADDR_ISP_BASE + 0x4290) // WDR internal buffer0 address register
#define ADDR_REG_WDR_IBADDR1               (ADDR_ISP_BASE + 0x4294) // WDR internal buffer1 address register
#define ADDR_REG_WDR_THR1                  (ADDR_ISP_BASE + 0x4298) // WDR level1 window threshold regiser
#define ADDR_REG_WDR_THR2                  (ADDR_ISP_BASE + 0x429C) // WDR level2 window threshold regiser
#define ADDR_REG_WDR_THR3                  (ADDR_ISP_BASE + 0x42A0) // WDR level3 window threshold regiser
#define ADDR_REG_WDR_WSR                   (ADDR_ISP_BASE + 0x42A4) // WDR spatial weight regiser
#define ADDR_REG_WDR_VR0                   (ADDR_ISP_BASE + 0x42A8) // WDR variance table regiser
#define ADDR_REG_WDR_VR1                   (ADDR_ISP_BASE + 0x42AC) // WDR variance table regiser
#define ADDR_REG_WDR_VR2                   (ADDR_ISP_BASE + 0x42B0) // WDR variance table regiser
#define ADDR_REG_WDR_VR3                   (ADDR_ISP_BASE + 0x42B4) // WDR variance table regiser
#define ADDR_REG_WDR_WR0                   (ADDR_ISP_BASE + 0x42B8) // WDR intensity weight table regiser
#define ADDR_REG_WDR_WR1                   (ADDR_ISP_BASE + 0x42BC) // WDR intensity weight table regiser
#define ADDR_REG_WDR_SR0                   (ADDR_ISP_BASE + 0x42C0) // WDR intensity weigth slope regiser
#define ADDR_REG_WDR_SR1                   (ADDR_ISP_BASE + 0x42C4) // WDR intensity weigth slope regiser
#define ADDR_REG_WDR_SR2                   (ADDR_ISP_BASE + 0x42C8) // WDR intensity weigth slope regiser
#define ADDR_REG_WDR_SR3                   (ADDR_ISP_BASE + 0x42CC) // WDR intensity weigth slope regiser
#define ADDR_REG_WDR_L3HSR                 (ADDR_ISP_BASE + 0x42D0) // WDR L3 histogram sum factor register
#define ADDR_REG_IGRVAL_15                 (ADDR_ISP_BASE + 0x433C) // Forward Gamma table Register 0
#define ADDR_REG_IGRVAL_16                 (ADDR_ISP_BASE + 0x4340) // Forward Gamma table Register 1
#define ADDR_REG_IGRVAL_17                 (ADDR_ISP_BASE + 0x4344) // Forward Gamma table Register 2
#define ADDR_REG_IGRVAL_18                 (ADDR_ISP_BASE + 0x4348) // Forward Gamma table Register 3
#define ADDR_REG_IGRVAL_19                 (ADDR_ISP_BASE + 0x434C) // Forward Gamma table Register 4
#define ADDR_REG_IGRVAL_20                 (ADDR_ISP_BASE + 0x4350) // Forward Gamma table Register 5
#define ADDR_REG_IGRVAL_21                 (ADDR_ISP_BASE + 0x4354) // Forward Gamma table Register 6
#define ADDR_REG_IGRVAL_22                 (ADDR_ISP_BASE + 0x4358) // Forward Gamma table Register 7
#define ADDR_REG_IGRVAL_23                 (ADDR_ISP_BASE + 0x435C) // Forward Gamma table Register 8
#define ADDR_REG_IGRVAL_24                 (ADDR_ISP_BASE + 0x4360) // Forward Gamma table Register 9
#define ADDR_REG_IGRVAL_25                 (ADDR_ISP_BASE + 0x4364) // Forward Gamma table Register 10
#define ADDR_REG_IGRVAL_26                 (ADDR_ISP_BASE + 0x4368) // Forward Gamma table Register 11
#define ADDR_REG_IGRVAL_27                 (ADDR_ISP_BASE + 0x436C) // Forward Gamma table Register 12
#define ADDR_REG_IGRVAL_28                 (ADDR_ISP_BASE + 0x4370) // Forward Gamma table Register 13
#define ADDR_REG_IGRVAL_29                 (ADDR_ISP_BASE + 0x4374) // Forward Gamma table Register 14
#define ADDR_REG_IGRVAL_30                 (ADDR_ISP_BASE + 0x4378) // Reserve Gamma table Register 0
#define ADDR_REG_IGRVAL_31                 (ADDR_ISP_BASE + 0x437C) // Reserve Gamma table Register 1
#define ADDR_REG_IGRVAL_32                 (ADDR_ISP_BASE + 0x4380) // Reserve Gamma table Register 2
#define ADDR_REG_IGRVAL_33                 (ADDR_ISP_BASE + 0x4384) // Reserve Gamma table Register 3
#define ADDR_REG_IGRVAL_34                 (ADDR_ISP_BASE + 0x4388) // Reserve Gamma table Register 4
#define ADDR_REG_IGRVAL_35                 (ADDR_ISP_BASE + 0x438C) // Reserve Gamma table Register 5
#define ADDR_REG_IGRVAL_36                 (ADDR_ISP_BASE + 0x4390) // Reserve Gamma table Register 6
#define ADDR_REG_IGRVAL_37                 (ADDR_ISP_BASE + 0x4394) // Reserve Gamma table Register 7
#define ADDR_REG_IGRVAL_38                 (ADDR_ISP_BASE + 0x4398) // Reserve Gamma table Register 8
#define ADDR_REG_IGRVAL_39                 (ADDR_ISP_BASE + 0x439C) // Reserve Gamma table Register 9
#define ADDR_REG_IGRVAL_40                 (ADDR_ISP_BASE + 0x43A0) // Reserve Gamma table Register 10
#define ADDR_REG_IGRVAL_41                 (ADDR_ISP_BASE + 0x43A4) // Reserve Gamma table Register 11
#define ADDR_REG_IGRVAL_42                 (ADDR_ISP_BASE + 0x43A8) // Reserve Gamma table Register 12
#define ADDR_REG_IGRVAL_43                 (ADDR_ISP_BASE + 0x43AC) // Reserve Gamma table Register 13
#define ADDR_REG_IGRVAL_44                 (ADDR_ISP_BASE + 0x43B0) // Reserve Gamma table Register 14
#define ADDR_REG_IPF0_CB_0                 (ADDR_ISP_BASE + 0x4400) // Purple Fringing Correction Register 0
#define ADDR_REG_IPF0_CB_1                 (ADDR_ISP_BASE + 0x4404) // Purple Fringing Correction Register 0
#define ADDR_REG_IPF0_CB_2                 (ADDR_ISP_BASE + 0x4408) // Purple Fringing Correction Register 1
#define ADDR_REG_IPF0_CB_3                 (ADDR_ISP_BASE + 0x440C) // Purple Fringing Correction Register 1
#define ADDR_REG_IPF0_CB_4                 (ADDR_ISP_BASE + 0x4410) // Purple Fringing Correction Register 2
#define ADDR_REG_IPF0_CB_5                 (ADDR_ISP_BASE + 0x4414) // Purple Fringing Correction Register 2
#define ADDR_REG_IPF0_CB_6                 (ADDR_ISP_BASE + 0x4418) // Purple Fringing Correction Register 3
#define ADDR_REG_IPF0_CB_7                 (ADDR_ISP_BASE + 0x441C) // Purple Fringing Correction Register 3
#define ADDR_REG_IPF0_CB_8                 (ADDR_ISP_BASE + 0x4420) // Purple Fringing Correction Register 4
#define ADDR_REG_IPF0_CB_9                 (ADDR_ISP_BASE + 0x4424) // Purple Fringing Correction Register 4
#define ADDR_REG_IPF0_CB_10                (ADDR_ISP_BASE + 0x4428) // Purple Fringing Correction Register 5
#define ADDR_REG_IPF0_CB_11                (ADDR_ISP_BASE + 0x442C) // Purple Fringing Correction Register 5
#define ADDR_REG_IPF0_CB_12                (ADDR_ISP_BASE + 0x4430) // Purple Fringing Correction Register 6
#define ADDR_REG_IPF0_CB_13                (ADDR_ISP_BASE + 0x4434) // Purple Fringing Correction Register 6
#define ADDR_REG_IPF0_CB_14                (ADDR_ISP_BASE + 0x4438) // Purple Fringing Correction Register 7
#define ADDR_REG_IPF0_CB_15                (ADDR_ISP_BASE + 0x443C) // Purple Fringing Correction Register 7
#define ADDR_REG_IPF0_CB_16                (ADDR_ISP_BASE + 0x4440) // Purple Fringing Correction Register 8
#define ADDR_REG_IPF0_CB_17                (ADDR_ISP_BASE + 0x4444) // Purple Fringing Correction Register 8
#define ADDR_REG_IPF0_CB_18                (ADDR_ISP_BASE + 0x4448) // Purple Fringing Correction Register 9
#define ADDR_REG_IPF0_CB_19                (ADDR_ISP_BASE + 0x444C) // Purple Fringing Correction Register 9
#define ADDR_REG_IPF0_CB_20                (ADDR_ISP_BASE + 0x4450) // Purple Fringing Correction Register 10
#define ADDR_REG_IPF0_CB_21                (ADDR_ISP_BASE + 0x4454) // Purple Fringing Correction Register 10
#define ADDR_REG_IPF0_CB_22                (ADDR_ISP_BASE + 0x4458) // Purple Fringing Correction Register 11
#define ADDR_REG_IPF0_CB_23                (ADDR_ISP_BASE + 0x445C) // Purple Fringing Correction Register 11
#define ADDR_REG_IPF0_CB_24                (ADDR_ISP_BASE + 0x4460) // Purple Fringing Correction Register 12
#define ADDR_REG_IPF0_CB_25                (ADDR_ISP_BASE + 0x4464) // Purple Fringing Correction Register 12
#define ADDR_REG_IPF1_CRG_0                (ADDR_ISP_BASE + 0x4468) // Purple Fringing Correction Register 0
#define ADDR_REG_IPF1_CRG_1                (ADDR_ISP_BASE + 0x446C) // Purple Fringing Correction Register 0
#define ADDR_REG_IPF1_CRG_2                (ADDR_ISP_BASE + 0x4470) // Purple Fringing Correction Register 1
#define ADDR_REG_IPF1_CRG_3                (ADDR_ISP_BASE + 0x4474) // Purple Fringing Correction Register 1
#define ADDR_REG_IPF1_CRG_4                (ADDR_ISP_BASE + 0x4478) // Purple Fringing Correction Register 2
#define ADDR_REG_IPF1_CRG_5                (ADDR_ISP_BASE + 0x447C) // Purple Fringing Correction Register 2
#define ADDR_REG_IPF1_CRG_6                (ADDR_ISP_BASE + 0x4480) // Purple Fringing Correction Register 3
#define ADDR_REG_IPF1_CRG_7                (ADDR_ISP_BASE + 0x4484) // Purple Fringing Correction Register 3
#define ADDR_REG_IPF1_CRG_8                (ADDR_ISP_BASE + 0x4488) // Purple Fringing Correction Register 4
#define ADDR_REG_IPF1_CRG_9                (ADDR_ISP_BASE + 0x448C) // Purple Fringing Correction Register 4
#define ADDR_REG_IPF1_CRG_10               (ADDR_ISP_BASE + 0x4490) // Purple Fringing Correction Register 5
#define ADDR_REG_IPF1_CRG_11               (ADDR_ISP_BASE + 0x4494) // Purple Fringing Correction Register 5
#define ADDR_REG_IPF1_CRG_12               (ADDR_ISP_BASE + 0x4498) // Purple Fringing Correction Register 6
#define ADDR_REG_IPF1_CRG_13               (ADDR_ISP_BASE + 0x449C) // Purple Fringing Correction Register 6
#define ADDR_REG_IPF1_CRG_14               (ADDR_ISP_BASE + 0x44A0) // Purple Fringing Correction Register 7
#define ADDR_REG_IPF1_CRG_15               (ADDR_ISP_BASE + 0x44A4) // Purple Fringing Correction Register 7
#define ADDR_REG_IPF1_CRG_16               (ADDR_ISP_BASE + 0x44A8) // Purple Fringing Correction Register 8
#define ADDR_REG_IPF1_CRG_17               (ADDR_ISP_BASE + 0x44AC) // Purple Fringing Correction Register 8
#define ADDR_REG_IPF1_CRG_18               (ADDR_ISP_BASE + 0x44B0) // Purple Fringing Correction Register 9
#define ADDR_REG_IPF1_CRG_19               (ADDR_ISP_BASE + 0x44B4) // Purple Fringing Correction Register 9
#define ADDR_REG_IPF1_CRG_20               (ADDR_ISP_BASE + 0x44B8) // Purple Fringing Correction Register 10
#define ADDR_REG_IPF1_CRG_21               (ADDR_ISP_BASE + 0x44BC) // Purple Fringing Correction Register 10
#define ADDR_REG_IPF1_CRG_22               (ADDR_ISP_BASE + 0x44C0) // Purple Fringing Correction Register 11
#define ADDR_REG_IPF1_CRG_23               (ADDR_ISP_BASE + 0x44C4) // Purple Fringing Correction Register 11
#define ADDR_REG_IPF1_CRG_24               (ADDR_ISP_BASE + 0x44C8) // Purple Fringing Correction Register 12
#define ADDR_REG_IPF1_CRG_25               (ADDR_ISP_BASE + 0x44CC) // Purple Fringing Correction Register 12
#define ADDR_REG_IPF2_F_0                  (ADDR_ISP_BASE + 0x4500) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_1                  (ADDR_ISP_BASE + 0x4504) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_2                  (ADDR_ISP_BASE + 0x4508) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_3                  (ADDR_ISP_BASE + 0x450C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_4                  (ADDR_ISP_BASE + 0x4510) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_5                  (ADDR_ISP_BASE + 0x4514) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_6                  (ADDR_ISP_BASE + 0x4518) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_7                  (ADDR_ISP_BASE + 0x451C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_8                  (ADDR_ISP_BASE + 0x4520) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_9                  (ADDR_ISP_BASE + 0x4524) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_10                 (ADDR_ISP_BASE + 0x4528) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_11                 (ADDR_ISP_BASE + 0x452C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_12                 (ADDR_ISP_BASE + 0x4530) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_13                 (ADDR_ISP_BASE + 0x4534) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_14                 (ADDR_ISP_BASE + 0x4538) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_15                 (ADDR_ISP_BASE + 0x453C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_16                 (ADDR_ISP_BASE + 0x4540) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_17                 (ADDR_ISP_BASE + 0x4544) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_18                 (ADDR_ISP_BASE + 0x4548) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_19                 (ADDR_ISP_BASE + 0x454C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_20                 (ADDR_ISP_BASE + 0x4550) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_21                 (ADDR_ISP_BASE + 0x4554) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_22                 (ADDR_ISP_BASE + 0x4558) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_23                 (ADDR_ISP_BASE + 0x455C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_24                 (ADDR_ISP_BASE + 0x4560) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_25                 (ADDR_ISP_BASE + 0x4564) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_26                 (ADDR_ISP_BASE + 0x4568) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_27                 (ADDR_ISP_BASE + 0x456C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_28                 (ADDR_ISP_BASE + 0x4570) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_29                 (ADDR_ISP_BASE + 0x4574) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_30                 (ADDR_ISP_BASE + 0x4578) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_31                 (ADDR_ISP_BASE + 0x457C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_32                 (ADDR_ISP_BASE + 0x4580) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_33                 (ADDR_ISP_BASE + 0x4584) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_34                 (ADDR_ISP_BASE + 0x4588) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_35                 (ADDR_ISP_BASE + 0x458C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_36                 (ADDR_ISP_BASE + 0x4590) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_37                 (ADDR_ISP_BASE + 0x4594) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_38                 (ADDR_ISP_BASE + 0x4598) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_39                 (ADDR_ISP_BASE + 0x459C) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_40                 (ADDR_ISP_BASE + 0x45A0) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_41                 (ADDR_ISP_BASE + 0x45A4) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_42                 (ADDR_ISP_BASE + 0x45A8) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_43                 (ADDR_ISP_BASE + 0x45AC) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_44                 (ADDR_ISP_BASE + 0x45B0) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_45                 (ADDR_ISP_BASE + 0x45B4) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_46                 (ADDR_ISP_BASE + 0x45B8) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_47                 (ADDR_ISP_BASE + 0x45BC) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_48                 (ADDR_ISP_BASE + 0x45C0) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_49                 (ADDR_ISP_BASE + 0x45C4) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_50                 (ADDR_ISP_BASE + 0x45C8) // Purple Fringing Correction Register 
#define ADDR_REG_IPF2_F_51                 (ADDR_ISP_BASE + 0x45CC) // Purple Fringing Correction Register 
#define ADDR_REG_IPF3_RG_MD                (ADDR_ISP_BASE + 0x45D0) // Purple Fringing Correction Register 3
#define ADDR_REG_ICA0_CRGX_0               (ADDR_ISP_BASE + 0x4600) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA0_CRGX_1               (ADDR_ISP_BASE + 0x4604) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA0_CRGX_2               (ADDR_ISP_BASE + 0x4608) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA0_CRGX_3               (ADDR_ISP_BASE + 0x460C) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA0_CRGX_4               (ADDR_ISP_BASE + 0x4610) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA0_CRGX_5               (ADDR_ISP_BASE + 0x4614) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA0_CRGX_6               (ADDR_ISP_BASE + 0x4618) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA0_CRGX_7               (ADDR_ISP_BASE + 0x461C) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA0_CRGX_8               (ADDR_ISP_BASE + 0x4620) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA0_CRGX_9               (ADDR_ISP_BASE + 0x4624) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA0_CRGX_10              (ADDR_ISP_BASE + 0x4628) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA0_CRGX_11              (ADDR_ISP_BASE + 0x462C) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA0_CRGX_12              (ADDR_ISP_BASE + 0x4630) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA0_CRGX_13              (ADDR_ISP_BASE + 0x4634) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA0_CRGX_14              (ADDR_ISP_BASE + 0x4638) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA0_CRGX_15              (ADDR_ISP_BASE + 0x463C) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA0_CRGX_16              (ADDR_ISP_BASE + 0x4640) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA0_CRGX_17              (ADDR_ISP_BASE + 0x4644) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA0_CRGX_18              (ADDR_ISP_BASE + 0x4648) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA0_CRGX_19              (ADDR_ISP_BASE + 0x464C) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA0_CRGX_20              (ADDR_ISP_BASE + 0x4650) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA0_CRGX_21              (ADDR_ISP_BASE + 0x4654) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA0_CRGX_22              (ADDR_ISP_BASE + 0x4658) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA0_CRGX_23              (ADDR_ISP_BASE + 0x465C) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA0_CRGX_24              (ADDR_ISP_BASE + 0x4660) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICA0_CRGX_25              (ADDR_ISP_BASE + 0x4664) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICA1_CRGY_0               (ADDR_ISP_BASE + 0x4668) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA1_CRGY_1               (ADDR_ISP_BASE + 0x466C) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA1_CRGY_2               (ADDR_ISP_BASE + 0x4670) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA1_CRGY_3               (ADDR_ISP_BASE + 0x4674) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA1_CRGY_4               (ADDR_ISP_BASE + 0x4678) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA1_CRGY_5               (ADDR_ISP_BASE + 0x467C) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA1_CRGY_6               (ADDR_ISP_BASE + 0x4680) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA1_CRGY_7               (ADDR_ISP_BASE + 0x4684) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA1_CRGY_8               (ADDR_ISP_BASE + 0x4688) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA1_CRGY_9               (ADDR_ISP_BASE + 0x468C) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA1_CRGY_10              (ADDR_ISP_BASE + 0x4690) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA1_CRGY_11              (ADDR_ISP_BASE + 0x4694) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA1_CRGY_12              (ADDR_ISP_BASE + 0x4698) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA1_CRGY_13              (ADDR_ISP_BASE + 0x469C) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA1_CRGY_14              (ADDR_ISP_BASE + 0x46A0) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA1_CRGY_15              (ADDR_ISP_BASE + 0x46A4) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA1_CRGY_16              (ADDR_ISP_BASE + 0x46A8) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA1_CRGY_17              (ADDR_ISP_BASE + 0x46AC) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA1_CRGY_18              (ADDR_ISP_BASE + 0x46B0) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA1_CRGY_19              (ADDR_ISP_BASE + 0x46B4) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA1_CRGY_20              (ADDR_ISP_BASE + 0x46B8) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA1_CRGY_21              (ADDR_ISP_BASE + 0x46BC) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA1_CRGY_22              (ADDR_ISP_BASE + 0x46C0) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA1_CRGY_23              (ADDR_ISP_BASE + 0x46C4) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA1_CRGY_24              (ADDR_ISP_BASE + 0x46C8) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICA1_CRGY_25              (ADDR_ISP_BASE + 0x46CC) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICA2_CBGX_0               (ADDR_ISP_BASE + 0x4700) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA2_CBGX_1               (ADDR_ISP_BASE + 0x4704) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA2_CBGX_2               (ADDR_ISP_BASE + 0x4708) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA2_CBGX_3               (ADDR_ISP_BASE + 0x470C) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA2_CBGX_4               (ADDR_ISP_BASE + 0x4710) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA2_CBGX_5               (ADDR_ISP_BASE + 0x4714) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA2_CBGX_6               (ADDR_ISP_BASE + 0x4718) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA2_CBGX_7               (ADDR_ISP_BASE + 0x471C) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA2_CBGX_8               (ADDR_ISP_BASE + 0x4720) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA2_CBGX_9               (ADDR_ISP_BASE + 0x4724) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA2_CBGX_10              (ADDR_ISP_BASE + 0x4728) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA2_CBGX_11              (ADDR_ISP_BASE + 0x472C) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA2_CBGX_12              (ADDR_ISP_BASE + 0x4730) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA2_CBGX_13              (ADDR_ISP_BASE + 0x4734) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA2_CBGX_14              (ADDR_ISP_BASE + 0x4738) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA2_CBGX_15              (ADDR_ISP_BASE + 0x473C) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA2_CBGX_16              (ADDR_ISP_BASE + 0x4740) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA2_CBGX_17              (ADDR_ISP_BASE + 0x4744) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA2_CBGX_18              (ADDR_ISP_BASE + 0x4748) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA2_CBGX_19              (ADDR_ISP_BASE + 0x474C) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA2_CBGX_20              (ADDR_ISP_BASE + 0x4750) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA2_CBGX_21              (ADDR_ISP_BASE + 0x4754) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA2_CBGX_22              (ADDR_ISP_BASE + 0x4758) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA2_CBGX_23              (ADDR_ISP_BASE + 0x475C) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA2_CBGX_24              (ADDR_ISP_BASE + 0x4760) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICA2_CBGX_25              (ADDR_ISP_BASE + 0x4764) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICA3_CBGY_0               (ADDR_ISP_BASE + 0x4768) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA3_CBGY_1               (ADDR_ISP_BASE + 0x476C) // Chromatic Aberration Correction Register 0
#define ADDR_REG_ICA3_CBGY_2               (ADDR_ISP_BASE + 0x4770) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA3_CBGY_3               (ADDR_ISP_BASE + 0x4774) // Chromatic Aberration Correction Register 1
#define ADDR_REG_ICA3_CBGY_4               (ADDR_ISP_BASE + 0x4778) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA3_CBGY_5               (ADDR_ISP_BASE + 0x477C) // Chromatic Aberration Correction Register 2
#define ADDR_REG_ICA3_CBGY_6               (ADDR_ISP_BASE + 0x4780) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA3_CBGY_7               (ADDR_ISP_BASE + 0x4784) // Chromatic Aberration Correction Register 3
#define ADDR_REG_ICA3_CBGY_8               (ADDR_ISP_BASE + 0x4788) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA3_CBGY_9               (ADDR_ISP_BASE + 0x478C) // Chromatic Aberration Correction Register 4
#define ADDR_REG_ICA3_CBGY_10              (ADDR_ISP_BASE + 0x4790) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA3_CBGY_11              (ADDR_ISP_BASE + 0x4794) // Chromatic Aberration Correction Register 5
#define ADDR_REG_ICA3_CBGY_12              (ADDR_ISP_BASE + 0x4798) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA3_CBGY_13              (ADDR_ISP_BASE + 0x479C) // Chromatic Aberration Correction Register 6
#define ADDR_REG_ICA3_CBGY_14              (ADDR_ISP_BASE + 0x47A0) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA3_CBGY_15              (ADDR_ISP_BASE + 0x47A4) // Chromatic Aberration Correction Register 7
#define ADDR_REG_ICA3_CBGY_16              (ADDR_ISP_BASE + 0x47A8) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA3_CBGY_17              (ADDR_ISP_BASE + 0x47AC) // Chromatic Aberration Correction Register 8
#define ADDR_REG_ICA3_CBGY_18              (ADDR_ISP_BASE + 0x47B0) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA3_CBGY_19              (ADDR_ISP_BASE + 0x47B4) // Chromatic Aberration Correction Register 9
#define ADDR_REG_ICA3_CBGY_20              (ADDR_ISP_BASE + 0x47B8) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA3_CBGY_21              (ADDR_ISP_BASE + 0x47BC) // Chromatic Aberration Correction Register 10
#define ADDR_REG_ICA3_CBGY_22              (ADDR_ISP_BASE + 0x47C0) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA3_CBGY_23              (ADDR_ISP_BASE + 0x47C4) // Chromatic Aberration Correction Register 11
#define ADDR_REG_ICA3_CBGY_24              (ADDR_ISP_BASE + 0x47C8) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICA3_CBGY_25              (ADDR_ISP_BASE + 0x47CC) // Chromatic Aberration Correction Register 12
#define ADDR_REG_ICAMD_XL_CFG0             (ADDR_ISP_BASE + 0x4868) // x coordinates for luminance regiser 0
#define ADDR_REG_ICAMD_XL_CFG1             (ADDR_ISP_BASE + 0x486C) // x coordinates for luminance regiser 1
#define ADDR_REG_ICAMD_FL_CFG0             (ADDR_ISP_BASE + 0x4870) // f coordinates for luminance regiser 0
#define ADDR_REG_ICAMD_FL_CFG1             (ADDR_ISP_BASE + 0x4874) // f coordinates for luminance regiser 1
#define ADDR_REG_ICAMD_SL_CFG0             (ADDR_ISP_BASE + 0x4878) // s (slope) for luminance regiser 0
#define ADDR_REG_ICAMD_SL_CFG1             (ADDR_ISP_BASE + 0x487C) // s (slope) for luminance regiser 1
#define ADDR_REG_ICAMD_XS_CFG0             (ADDR_ISP_BASE + 0x4880) // x coordinates for color saturation regiser 0
#define ADDR_REG_ICAMD_XS_CFG1             (ADDR_ISP_BASE + 0x4884) // x coordinates for color saturation regiser 1
#define ADDR_REG_ICAMD_FS_CFG0             (ADDR_ISP_BASE + 0x4888) // f coordinates for color saturation regiser 0
#define ADDR_REG_ICAMD_FS_CFG1             (ADDR_ISP_BASE + 0x488C) // f coordinates for color saturation regiser 1
#define ADDR_REG_ICAMD_SS_CFG0             (ADDR_ISP_BASE + 0x4890) // s (slope) for color saturation regiser 0
#define ADDR_REG_ICAMD_SS_CFG1             (ADDR_ISP_BASE + 0x4894) // s (slope) for color saturation regiser 1
#define ADDR_REG_ISHRPWS2                  (ADDR_ISP_BASE + 0x4A6C) // Sharpen Wsum 2nd set register
#define ADDR_REG_ISHRPUVSMT                (ADDR_ISP_BASE + 0x4A70) // Sharpen UV Threshold
#define ADDR_REG_ISFRPBUF0                 (ADDR_ISP_BASE + 0x4A74) // Sharpen LPF Buffer 0 Register, 64bit align
#define ADDR_REG_ISFRPBUF1                 (ADDR_ISP_BASE + 0x4A78) // Sharpen LPF Buffer 1 Register, 64bit align
#define ADDR_REG_ISFRPBUFST                (ADDR_ISP_BASE + 0x4A7C) // Sharpen LPF Buffer Status Register
#define ADDR_REG_OBC_SUD                   (ADDR_ISP_BASE + 0x4B00) // OBC shadow register update enable register
#define ADDR_REG_NL3D_SUD                  (ADDR_ISP_BASE + 0x4B04) // NL3D shadow register update enable register
#define ADDR_REG_NL2D_SUD                  (ADDR_ISP_BASE + 0x4B08) // NL2D shadow register update enable register
#define ADDR_REG_GRGB_SUD                  (ADDR_ISP_BASE + 0x4B0C) // GRGB shadow register update enable register
#define ADDR_REG_AWB_SUD                   (ADDR_ISP_BASE + 0x4B10) // AWB shadow register update enable register
#define ADDR_REG_CCM_SUD                   (ADDR_ISP_BASE + 0x4B14) // CCM shadow register update enable register
#define ADDR_REG_LUT_SUD                   (ADDR_ISP_BASE + 0x4B18) // LUT shadow register update enable register
#define ADDR_REG_GAMRGB_SUD                (ADDR_ISP_BASE + 0x4B1C) // GAMRGB shadow register update enable register
#define ADDR_REG_R2Y_SUD                   (ADDR_ISP_BASE + 0x4B20) // R2Y shadow register update enable register
#define ADDR_REG_YCUR_SUD                  (ADDR_ISP_BASE + 0x4B24) // YCUR shadow register update enable register
#define ADDR_REG_NWED_SUD                  (ADDR_ISP_BASE + 0x4B28) // NWED shadow register update enable register
#define ADDR_REG_SHRP_SUD                  (ADDR_ISP_BASE + 0x4B2C) // SHRP shadow register update enable register
#define ADDR_REG_SAT_SUD                   (ADDR_ISP_BASE + 0x4B30) // SAT shadow register update enable register
#define ADDR_REG_SC0_SUD                   (ADDR_ISP_BASE + 0x4B34) // SC0 shadow register update enable register
#define ADDR_REG_SC1_SUD                   (ADDR_ISP_BASE + 0x4B38) // SC1 shadow register update enable register
#define ADDR_REG_YHIST_SUD                 (ADDR_ISP_BASE + 0x4B3C) // YHIST shadow register update enable register
#define ADDR_REG_ITI_SUD                   (ADDR_ISP_BASE + 0x4B40) // Tiling shadow register update enable register
#define ADDR_REG_WDR_SUD                   (ADDR_ISP_BASE + 0x4B44) // WDR shadow register update enable register
#define ADDR_REG_BIYUV_SUD                 (ADDR_ISP_BASE + 0x4B48) // BIYUV shadow register update enable register
#define ADDR_REG_CTM_SUD                   (ADDR_ISP_BASE + 0x4B4C) // CTM shadow register update enable register
#define ADDR_REG_OECF_SUD                  (ADDR_ISP_BASE + 0x4B50) // OECF shadow register update enable register
#endif
#define ADDR_REG_RDMA_ENR                  (ADDR_ISP_BASE + 0x4C00) // RDMA enable register
#define ADDR_REG_RDMA_SACKR                (ADDR_ISP_BASE + 0x4C04) // RDMA Software sint ack register
#define ADDR_REG_RDMA_DADDR                (ADDR_ISP_BASE + 0x4C08) // RDMA Descriptor Start Addresse register
#define ADDR_REG_RDMA_CADDR                (ADDR_ISP_BASE + 0x4C0C) // RDMA Descriptor Current Addresse register
#define ADDR_REG_RDMA_STSR                 (ADDR_ISP_BASE + 0x4C10) // RDMA Status Register
#if 0
#define ADDR_REG_BIYUV_YSWR0               (ADDR_ISP_BASE + 0x4D00) // BiYUV Y channel S weight table register 0
#define ADDR_REG_BIYUV_YSWR1               (ADDR_ISP_BASE + 0x4D04) // BiYUV Y channel S weight table register 1
#define ADDR_REG_BIYUV_UVSWR0              (ADDR_ISP_BASE + 0x4D08) // BiYUV UV channel S weight table register 0
#define ADDR_REG_BIYUV_UVSWR1              (ADDR_ISP_BASE + 0x4D0C) // BiYUV UV channel S weight table register  1
#define ADDR_REG_BIYUV_YCIR                (ADDR_ISP_BASE + 0x4D10) // BiYUV Y Curve I component register
#define ADDR_REG_BIYUV_UVCIR               (ADDR_ISP_BASE + 0x4D14) // BiYUV UV Curve I component register
#define ADDR_REG_BIYUV_YCDR0               (ADDR_ISP_BASE + 0x4D18) // BiYUV Y Curve D component register 0
#define ADDR_REG_BIYUV_YCDR1               (ADDR_ISP_BASE + 0x4D1C) // BiYUV Y Curve D component register 1
#define ADDR_REG_BIYUV_YCDR2               (ADDR_ISP_BASE + 0x4D20) // BiYUV Y Curve D component register 2
#define ADDR_REG_BIYUV_YCDR3               (ADDR_ISP_BASE + 0x4D24) // BiYUV Y Curve D component register 3
#define ADDR_REG_BIYUV_UVCDR0              (ADDR_ISP_BASE + 0x4D28) // BiYUV UV Curve D component register 0
#define ADDR_REG_BIYUV_UVCDR1              (ADDR_ISP_BASE + 0x4D2C) // BiYUV UV Curve D component register 1
#define ADDR_REG_BIYUV_UVCDR2              (ADDR_ISP_BASE + 0x4D30) // BiYUV UV Curve D component register 2
#define ADDR_REG_BIYUV_UVCDR3              (ADDR_ISP_BASE + 0x4D34) // BiYUV UV Curve D component register 3
#define ADDR_REG_BIYUV_YCSR0               (ADDR_ISP_BASE + 0x4D38) // BiYUV Y Curve S component register 0
#define ADDR_REG_BIYUV_YCSR1               (ADDR_ISP_BASE + 0x4D3C) // BiYUV Y Curve S component register 1
#define ADDR_REG_BIYUV_YCSR2               (ADDR_ISP_BASE + 0x4D40) // BiYUV Y Curve S component register 2
#define ADDR_REG_BIYUV_YCSR3               (ADDR_ISP_BASE + 0x4D44) // BiYUV Y Curve S component register 3
#define ADDR_REG_BIYUV_UVCSR0              (ADDR_ISP_BASE + 0x4D48) // BiYUV UV Curve S component register 0
#define ADDR_REG_BIYUV_UVCSR1              (ADDR_ISP_BASE + 0x4D4C) // BiYUV UV Curve S component register 1
#define ADDR_REG_BIYUV_UVCSR2              (ADDR_ISP_BASE + 0x4D50) // BiYUV UV Curve S component register 2
#define ADDR_REG_BIYUV_UVCSR3              (ADDR_ISP_BASE + 0x4D54) // BiYUV UV Curve S component register 3
#define ADDR_REG_CTM_HR0                   (ADDR_ISP_BASE + 0x4E00) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR1                   (ADDR_ISP_BASE + 0x4E04) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR2                   (ADDR_ISP_BASE + 0x4E08) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR3                   (ADDR_ISP_BASE + 0x4E0C) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR4                   (ADDR_ISP_BASE + 0x4E10) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR5                   (ADDR_ISP_BASE + 0x4E14) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR6                   (ADDR_ISP_BASE + 0x4E18) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR7                   (ADDR_ISP_BASE + 0x4E1C) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR8                   (ADDR_ISP_BASE + 0x4E20) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR9                   (ADDR_ISP_BASE + 0x4E24) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR10                  (ADDR_ISP_BASE + 0x4E28) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR11                  (ADDR_ISP_BASE + 0x4E2C) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR12                  (ADDR_ISP_BASE + 0x4E30) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR13                  (ADDR_ISP_BASE + 0x4E34) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR14                  (ADDR_ISP_BASE + 0x4E38) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR15                  (ADDR_ISP_BASE + 0x4E3C) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR16                  (ADDR_ISP_BASE + 0x4E40) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR17                  (ADDR_ISP_BASE + 0x4E44) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR18                  (ADDR_ISP_BASE + 0x4E48) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR19                  (ADDR_ISP_BASE + 0x4E4C) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR20                  (ADDR_ISP_BASE + 0x4E50) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR21                  (ADDR_ISP_BASE + 0x4E54) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR22                  (ADDR_ISP_BASE + 0x4E58) // Color Tone Mapping H register
#define ADDR_REG_CTM_HR23                  (ADDR_ISP_BASE + 0x4E5C) // Color Tone Mapping H register
#define ADDR_REG_CTM_GSR0                  (ADDR_ISP_BASE + 0x4E60) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR1                  (ADDR_ISP_BASE + 0x4E64) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR2                  (ADDR_ISP_BASE + 0x4E68) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR3                  (ADDR_ISP_BASE + 0x4E6C) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR4                  (ADDR_ISP_BASE + 0x4E70) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR5                  (ADDR_ISP_BASE + 0x4E74) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR6                  (ADDR_ISP_BASE + 0x4E78) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR7                  (ADDR_ISP_BASE + 0x4E7C) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR8                  (ADDR_ISP_BASE + 0x4E80) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR9                  (ADDR_ISP_BASE + 0x4E84) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR10                 (ADDR_ISP_BASE + 0x4E88) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR11                 (ADDR_ISP_BASE + 0x4E8C) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR12                 (ADDR_ISP_BASE + 0x4E90) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR13                 (ADDR_ISP_BASE + 0x4E94) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR14                 (ADDR_ISP_BASE + 0x4E98) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR15                 (ADDR_ISP_BASE + 0x4E9C) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR16                 (ADDR_ISP_BASE + 0x4EA0) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR17                 (ADDR_ISP_BASE + 0x4EA4) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR18                 (ADDR_ISP_BASE + 0x4EA8) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR19                 (ADDR_ISP_BASE + 0x4EAC) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR20                 (ADDR_ISP_BASE + 0x4EB0) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR21                 (ADDR_ISP_BASE + 0x4EB4) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR22                 (ADDR_ISP_BASE + 0x4EB8) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GSR23                 (ADDR_ISP_BASE + 0x4EBC) // Color Tone Mapping GS register
#define ADDR_REG_CTM_GVR0                  (ADDR_ISP_BASE + 0x4EC0) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR1                  (ADDR_ISP_BASE + 0x4EC4) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR2                  (ADDR_ISP_BASE + 0x4EC8) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR3                  (ADDR_ISP_BASE + 0x4ECC) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR4                  (ADDR_ISP_BASE + 0x4ED0) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR5                  (ADDR_ISP_BASE + 0x4ED4) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR6                  (ADDR_ISP_BASE + 0x4ED8) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR7                  (ADDR_ISP_BASE + 0x4EDC) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR8                  (ADDR_ISP_BASE + 0x4EE0) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR9                  (ADDR_ISP_BASE + 0x4EE4) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR10                 (ADDR_ISP_BASE + 0x4EE8) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR11                 (ADDR_ISP_BASE + 0x4EEC) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR12                 (ADDR_ISP_BASE + 0x4EF0) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR13                 (ADDR_ISP_BASE + 0x4EF4) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR14                 (ADDR_ISP_BASE + 0x4EF8) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR15                 (ADDR_ISP_BASE + 0x4EFC) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR16                 (ADDR_ISP_BASE + 0x4F00) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR17                 (ADDR_ISP_BASE + 0x4F04) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR18                 (ADDR_ISP_BASE + 0x4F08) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR19                 (ADDR_ISP_BASE + 0x4F0C) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR20                 (ADDR_ISP_BASE + 0x4F10) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR21                 (ADDR_ISP_BASE + 0x4F14) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR22                 (ADDR_ISP_BASE + 0x4F18) // Color Tone Mapping GV register
#define ADDR_REG_CTM_GVR23                 (ADDR_ISP_BASE + 0x4F1C) // Color Tone Mapping GV register
#define ADDR_REG_I3DLUT                    (ADDR_ISP_BASE + 0x8000) // 3D LUT Color Correction Register, 0x8000~0xFFFF(0~8191)
#define ADDR_REG_I3DLUT_END                (ADDR_ISP_BASE + 0xFFFF) // 3D LUT Color Correction Register, 0x8000~0xFFFF(0~8191)
#endif



////////////////////////////////////////////////////////////////////////////////////////////////////
// Register struct define.
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// csi input enable & status register.
// Offset: 0x0000
typedef union _REG_ENABLE_STATUS
{
	UINT32 value;
	struct
	{
		UINT32 csi_en               : 1 ; // [0] CSI enable.
		UINT32 csi_busy             : 1 ; // [1] (Read-Only)
		UINT32 scd_done             : 1 ; // [2] (Read-Only)
		UINT32 itu656_field         : 1 ; // [3] (Read-Only)
		UINT32 itu656_error         : 1 ; // [4] (Read-Only)
		UINT32 vs_done              : 1 ; // [5] Reserved.
		UINT32 scd_error            : 1 ; // [6] (Read-Only).
		UINT32 rsvd7                : 25; // [31:7] Reserved.
	} field;
} REG_ENABLE_STATUS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// input pixel counter register.
// Offset: 0x0004
typedef union _REG_VCNT
{
	UINT32 value;
	struct
	{
		UINT32 cro_vcnt             : 16; // [15:0] V counter.
		UINT32 remainder_wcnt       : 16; // [31:16] Reserved.
	} field;
} REG_VCNT;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Interrupt and Shadow 
// Offset: 0x0008
typedef union _REG_CSIINTS
{
	UINT32 value;
	struct
	{
		UINT32 lint                 : 16; // [15:0] Line interrupt line number
		UINT32 ud                   : 1 ; // [16] Shadow update enable
		UINT32 udm                  : 1 ; // [17] Shadow update mode
	} field;
} REG_CSIINTS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// csi module enable register.
// Offset: 0x0010
typedef union _REG_FUNCTION_MODE
{
	UINT32 value;
	struct
	{
		UINT32 dc_en                : 1 ; // [0] enable DC .
		UINT32 dec_en               : 1 ; // [1] enable Raw Decimation .
		UINT32 obc_en               : 1 ; // [2] enable OBC .
		UINT32 lcbq_en              : 1 ; // [3] enable LCBQ .
		UINT32 oecf_en              : 1 ; // [4] enable OECF .
		UINT32 oecfhm_en            : 1 ; // [5] enable OECF Hermite .
		UINT32 lccf_en              : 1 ; // [6] enable LCCF .
		UINT32 awb_en               : 1 ; // [7] enable AWB WB Gain.
		UINT32 rsvd8                : 8 ; // [15:8] reserved
		UINT32 oba_en               : 1 ; // [16] enable OBA .
		UINT32 sc_en                : 1 ; // [17] enable SC.
		UINT32 vs_en                : 1 ; // [18] Reserved.
		UINT32 dump_en              : 1 ; // [19] enable DUMP.
	} field;
} REG_FUNCTION_MODE;

////////////////////////////////////////////////////////////////////////////////////////////////////
// input dvp format & signal polarity cfg.
// Offset: 0x0014
typedef union _REG_SENSOR
{
	UINT32 value;
	struct
	{
		UINT32 imager_sel           : 1 ; // [0] 
		UINT32 itu656_en            : 1 ; // [1] 
		UINT32 dvp_sync_pol         : 2 ; // [3:2] inveret when set to high
	} field;
} REG_SENSOR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// input RAW format cfg.
// Offset: 0x0018
typedef union _REG_CFA
{
	UINT32 value;
	struct
	{
		UINT32 sym00                : 2 ; // [1:0] Symbol of the 1st Pixel on the 1st Line
		UINT32 sym01                : 2 ; // [3:2] Symbol of the 2nd Pixel on the 1st Line
		UINT32 sym02                : 2 ; // [5:4] Symbol of the 3rd Pixel on the 1st Line
		UINT32 sym03                : 2 ; // [7:6] Symbol of the 4th Pixel on the 1st Line
		UINT32 sym10                : 2 ; // [9:8] Symbol of the 1st Pixel on the 2nd Line
		UINT32 sym11                : 2 ; // [11:10] Symbol of the 2nd Pixel on the 2nd Line
		UINT32 sym12                : 2 ; // [13:12] Symbol of the 3rd Pixel on the 2nd Line
		UINT32 sym13                : 2 ; // [15:14] Symbol of the 4th Pixel on the 2nd Line
		UINT32 reserved             : 16; // [31:16] Reserved.
	} field;
} REG_CFA;

////////////////////////////////////////////////////////////////////////////////////////////////////
// input picture capture start cfg(x/y start location), each 16bit (cropping)
// Offset: 0x001C
typedef union _REG_CAPTURE_WINDOW_START
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 16; // [15:0] Horizontal starting point of capture window
		UINT32 vstart               : 16; // [31:16] Vertical starting point of capture window
	} field;
} REG_CAPTURE_WINDOW_START;

////////////////////////////////////////////////////////////////////////////////////////////////////
// input picture capture end cfg(x/y end location), each 16bit (cropping)
// Offset: 0x0020
typedef union _REG_CAPTURE_WINDOW_END
{
	UINT32 value;
	struct
	{
		UINT32 hend                 : 16; // [15:0] Horizontal ending point of capture window
		UINT32 vend                 : 16; // [31:16] Vertical ending point of capture window
	} field;
} REG_CAPTURE_WINDOW_END;

////////////////////////////////////////////////////////////////////////////////////////////////////
// base address for captured image
// Offset: 0x0024
typedef union _REG_DUMP_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 7 ; // [6:0] 
		UINT32 base_adr             : 25; // [31:7] base address for captured image 8x16 byte aligned
	} field;
} REG_DUMP_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// dump configuration
// Offset: 0x0028
typedef union _REG_DUMP_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 7 ; // [6:0] Reserved.
		UINT32 sd                   : 9 ; // [15:7] Stride address for captured image 8x16 byte aligned.
		UINT32 burst_len            : 2 ; // [17:16] AXI memory write burst length.
		UINT32 rsvd18               : 2 ; // [19:18] Reserved.
		UINT32 sht                  : 3 ; // [22:20] Pixel right shift number.
		UINT32 rsvd23               : 1 ; // [23] Reserved.
		UINT32 id                   : 8 ; // [31:24] AXI memory write ID.
	} field;
} REG_DUMP_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// csi pipeline dec cfg register, Horizontal/Vertical period/keep, must set to odd 
// Offset: 0x0030
typedef union _REG_DEC_CFG
{
	UINT32 value;
	struct
	{
		UINT32 hperiod              : 5 ; // [4:0] Horizontal period(zero base)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 hkeep                : 5 ; // [12:8] Horizontal keep(zero base)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 vperiod              : 5 ; // [20:16] Vertical period(zero base)
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 vkeep                : 5 ; // [28:24] Vertical keep(zero base)
	} field;
} REG_DEC_CFG;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OBC(Optical Black Compensation) window height(2^HEIGHT)/OBC window width(2^WIDTH),
// Offset: 0x0034
typedef union _REG_OBC_CFG
{
	UINT32 value;
	struct
	{
		UINT32 width                : 4 ; // [3:0] OBC window width
		UINT32 height               : 4 ; // [7:4] OBC window height
	} field;
} REG_OBC_CFG;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DC axi base address register
// Offset: 0x0040
typedef union _REG_DC_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] vpos[13:0]/mode[1:0]/hpos[13:0]
		UINT32 base_adr             : 29; // [31:3] DC axi base address (8 byte aligned)
	} field;
} REG_DC_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DC axi id
// Offset: 0x0044
typedef union _REG_DC_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 axi_id               : 8 ; // [7:0] AXI ID
	} field;
} REG_DC_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X/Y distance from capture window(each 15bits)
// Offset: 0x0050
typedef union _REG_LCCF_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 xd                   : 15; // [14:0] X distance from capture window
		UINT32 rsvd15               : 1 ; // [15] 
		UINT32 yd                   : 15; // [30:16] Y distance from capture window
	} field;
} REG_LCCF_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCCF maximum distance register
// Offset: 0x0058
typedef union _REG_LCCF_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 m                    : 4 ; // [3:0] Parameter for typical maximum distance (dM = 2^M), 4bits
	} field;
} REG_LCCF_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ pseudo sub-window register
// Offset: 0x0074
typedef union _REG_LCBQ_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 width                : 4 ; // [11:8] LCBQ Width of pseudo sub-window (2^WIDTH)
		UINT32 height               : 4 ; // [15:12] LCBQ Height of pseudo sub-window (2^HEIGHT)
	} field;
} REG_LCBQ_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ X/Y coordinate register
// Offset: 0x007C
typedef union _REG_LCBQ_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x                    : 12; // [11:0] X coordinate
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 y                    : 12; // [27:16] Y coordinate
	} field;
} REG_LCBQ_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Vertical starting point/Horizontal ending point, each 16bits (black cropping)
// Offset: 0x0090
typedef union _REG_OBA_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 16; // [15:0] Horizontal starting point
		UINT32 vstart               : 16; // [31:16] Vertical starting point
	} field;
} REG_OBA_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Vertical ending point/Horizontal ending point, each 16bits
// Offset: 0x0094
typedef union _REG_OBA_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 hend                 : 16; // [15:0] Horizontal ending point
		UINT32 vend                 : 16; // [31:16] Vertical ending point
	} field;
} REG_OBA_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC dumping base address 
// Offset: 0x0098
typedef union _REG_SCD_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 7 ; // [6:0] 
		UINT32 base_adr             : 25; // [31:7] SC dumping base address(8x16byte align), need use AWB WB frame_start generate interrupt & sync address
	} field;
} REG_SCD_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC dumping axi id
// Offset: 0x009C
typedef union _REG_SCD_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 24; // [23:0] 
		UINT32 axi_id               : 8 ; // [31:24] AXI ID
	} field;
} REG_SCD_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OBA value for symbol 0
// Offset: 0x00A0
typedef union _REG_OBA_ACC_0
{
	UINT32 value;
	struct
	{
		UINT32 acc0                 : 32; // [31:0] oba symbol 0 return acc(read only)
	} field;
} REG_OBA_ACC_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OBA value for symbol 1
// Offset: 0x00A4
typedef union _REG_OBA_ACC_1
{
	UINT32 value;
	struct
	{
		UINT32 acc1                 : 32; // [31:0] oba symbol 1 return acc(read only)
	} field;
} REG_OBA_ACC_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OBA value for symbol 2
// Offset: 0x00A8
typedef union _REG_OBA_ACC_2
{
	UINT32 value;
	struct
	{
		UINT32 acc2                 : 32; // [31:0] oba symbol 2 return acc(read only)
	} field;
} REG_OBA_ACC_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OBA value for symbol 3
// Offset: 0x00AC
typedef union _REG_OBA_ACC_3
{
	UINT32 value;
	struct
	{
		UINT32 acc3                 : 32; // [31:0] oba symbol 3 return acc(read only)
	} field;
} REG_OBA_ACC_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC frame cropping for sc awb
// Offset: 0x00B8
typedef union _REG_SC_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 16; // [15:0] Horizontal starting point for frame cropping
		UINT32 vstart               : 16; // [31:16] Vertical starting point for frame cropping
	} field;
} REG_SC_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC cfg1 register
// Offset: 0x00BC
typedef union _REG_SC_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 width                : 5 ; // [4:0] Width of SC sub-window(SC_WIDTH+1)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 height               : 5 ; // [12:8] Height of SC sub-window(SC_HEIGHT+1)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 awb_ps_grb_ba        : 8 ; // [23:16] [0.4.4] awb b/a value
		UINT32 rsvd24               : 6 ; // [29:24] 
		UINT32 sel                  : 2 ; // [31:30] sc0 input mux for sc awb
	} field;
} REG_SC_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AF register
// Offset: 0x00C0
typedef union _REG_SC_AF
{
	UINT32 value;
	struct
	{
		UINT32 af_es_hm             : 1 ; // [0] Horizontal mode
		UINT32 af_es_sm             : 1 ; // [1] 0:Absolute sum, 1:Squared sum
		UINT32 af_es_he             : 1 ; // [2] Horizontal enable
		UINT32 af_es_ve             : 1 ; // [3] Vertical enable
		UINT32 rsvd4                : 4 ; // [7:4] 
		UINT32 af_es_vthr           : 8 ; // [15:8] Vertical threshold
		UINT32 af_es_hthr           : 9 ; // [24:16] Horizontal threshold
	} field;
} REG_SC_AF;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AWB pixel sum registers0
// Offset: 0x00C4
typedef union _REG_SC_AWB_PS_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ps_rl            : 8 ; // [7:0] [0.8.0]Lower boundary of R value
		UINT32 awb_ps_ru            : 8 ; // [15:8] [0.8.0]Upper boundary of R value
		UINT32 awb_ps_gl            : 8 ; // [23:16] [0.8.0]Lower boundary of G value
		UINT32 awb_ps_gu            : 8 ; // [31:24] [0.8.0]Upper boundary of G value
	} field;
} REG_SC_AWB_PS_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AWB pixel sum registers1
// Offset: 0x00C8
typedef union _REG_SC_AWB_PS_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ps_bl            : 8 ; // [7:0] [0.8.0]Lower boundary of B value
		UINT32 awb_ps_bu            : 8 ; // [15:8] [0.8.0]Upper boundary of B value
		UINT32 awb_ps_yl            : 8 ; // [23:16] [0.8.0]Lower boundary of Y value
		UINT32 awb_ps_yu            : 8 ; // [31:24] [0.8.0]Upper boundary of Y value
	} field;
} REG_SC_AWB_PS_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AWB pixel sum registers2
// Offset: 0x00CC
typedef union _REG_SC_AWB_PS_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 awb_ps_grl           : 16; // [15:0] [0.8.8]Lower boundary of G/R ratio
		UINT32 awb_ps_gru           : 16; // [31:16] [0.8.8]Upper boundary of G/R ratio
	} field;
} REG_SC_AWB_PS_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AWB pixel sum registers3
// Offset: 0x00D0
typedef union _REG_SC_AWB_PS_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 awb_ps_gbl           : 16; // [15:0] [0.8.8]Lower boundary of G/B ratio
		UINT32 awb_ps_gbu           : 16; // [31:16] [0.8.8]Upper boundary of G/B ratio
	} field;
} REG_SC_AWB_PS_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AWB pixel sum registers4
// Offset: 0x00D4
typedef union _REG_SC_AWB_PS_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 awb_ps_grbl          : 16; // [15:0] [0.8.8]Lower boundary of (Gr/R + b/a * Gb/B)
		UINT32 awb_ps_grbu          : 16; // [31:16] [0.8.8]Upper boundary of (Gr/R + b/a * Gb/B)
	} field;
} REG_SC_AWB_PS_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// sc0 dec cfg register for sc awb, Horizontal/Vertical period/keep
// Offset: 0x00D8
typedef union _REG_SC_DEC
{
	UINT32 value;
	struct
	{
		UINT32 hperiod              : 5 ; // [4:0] Horizontal period(zero base)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 hkeep                : 5 ; // [12:8] Horizontal keep(zero base)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 vperiod              : 5 ; // [20:16] Vertical period(zero base)
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 vkeep                : 5 ; // [28:24] Vertical keep(zero base)
	} field;
} REG_SC_DEC;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCCF F parameter for symbol 0 register
// Offset: 0x00E0
typedef union _REG_LCCF_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 f1_s0                : 13; // [12:0] [0.3.10]F1 parameter for symbol 0
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 f2_s0                : 12; // [27:16] [0.2.10]F2 parameter for symbol 0
	} field;
} REG_LCCF_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCCF F parameter for symbol 1 register
// Offset: 0x00E4
typedef union _REG_LCCF_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 f1_s1                : 13; // [12:0] [0.3.10]F1 parameter for symbol 1
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 f2_s1                : 12; // [27:16] [0.2.10]F2 parameter for symbol 1
	} field;
} REG_LCCF_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCCF F parameter for symbol 2 register
// Offset: 0x00E8
typedef union _REG_LCCF_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 f1_s2                : 13; // [12:0] [0.3.10]F1 parameter for symbol 2
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 f2_s2                : 12; // [27:16] [0.2.10]F2 parameter for symbol 2
	} field;
} REG_LCCF_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCCF F parameter for symbol 3 register
// Offset: 0x00EC
typedef union _REG_LCCF_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 f1_s3                : 13; // [12:0] [0.3.10]F1 parameter for symbol 3
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 f2_s3                : 12; // [27:16] [0.2.10]F2 parameter for symbol 3
	} field;
} REG_LCCF_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC read index
// Offset: 0x00F8
typedef union _REG_SCR_ADR
{
	UINT32 value;
	struct
	{
		UINT32 adr                  : 8 ; // [7:0] Select SC data.
		UINT32 rsvd8                : 8 ; // [15:8] 
		UINT32 idx                  : 5 ; // [20:16] Select SC method.
	} field;
} REG_SCR_ADR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC read data
// Offset: 0x00FC
typedef union _REG_SCR_DAT
{
	UINT32 value;
	struct
	{
		UINT32 dat                  : 32; // [31:0] SC data readout.
	} field;
} REG_SCR_DAT;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x0100
typedef union _REG_OECF_X0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s0                : 10; // [9:0] X0 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s0                : 10; // [25:16] X1 for symbol 0
	} field;
} REG_OECF_X0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x0104
typedef union _REG_OECF_X0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s0                : 10; // [9:0] X2 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s0                : 10; // [25:16] X3 for symbol 0
	} field;
} REG_OECF_X0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x0108
typedef union _REG_OECF_X0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s0                : 10; // [9:0] X4 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x5_s0                : 10; // [25:16] X5 for symbol 0
	} field;
} REG_OECF_X0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x010C
typedef union _REG_OECF_X0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s0                : 10; // [9:0] X6 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x7_s0                : 10; // [25:16] X7 for symbol 0
	} field;
} REG_OECF_X0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x0110
typedef union _REG_OECF_X0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s0                : 10; // [9:0] X8 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x9_s0                : 10; // [25:16] X9 for symbol 0
	} field;
} REG_OECF_X0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x0114
typedef union _REG_OECF_X0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s0               : 10; // [9:0] X10 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x11_s0               : 10; // [25:16] X11 for symbol 0
	} field;
} REG_OECF_X0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x0118
typedef union _REG_OECF_X0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s0               : 10; // [9:0] X12 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x13_s0               : 10; // [25:16] X13 for symbol 0
	} field;
} REG_OECF_X0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 0 
// Offset: 0x011C
typedef union _REG_OECF_X0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s0               : 10; // [9:0] X14 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x15_s0               : 10; // [25:16] X15 for symbol 0
	} field;
} REG_OECF_X0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x0120
typedef union _REG_OECF_X1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s1                : 10; // [9:0] X0 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s1                : 10; // [25:16] X1 for symbol 1
	} field;
} REG_OECF_X1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x0124
typedef union _REG_OECF_X1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s1                : 10; // [9:0] X2 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s1                : 10; // [25:16] X3 for symbol 1
	} field;
} REG_OECF_X1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x0128
typedef union _REG_OECF_X1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s1                : 10; // [9:0] X4 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x5_s1                : 10; // [25:16] X5 for symbol 1
	} field;
} REG_OECF_X1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x012C
typedef union _REG_OECF_X1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s1                : 10; // [9:0] X6 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x7_s1                : 10; // [25:16] X7 for symbol 1
	} field;
} REG_OECF_X1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x0130
typedef union _REG_OECF_X1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s1                : 10; // [9:0] X8 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x9_s1                : 10; // [25:16] X9 for symbol 1
	} field;
} REG_OECF_X1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x0134
typedef union _REG_OECF_X1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s1               : 10; // [9:0] X10 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x11_s1               : 10; // [25:16] X11 for symbol 1
	} field;
} REG_OECF_X1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x0138
typedef union _REG_OECF_X1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s1               : 10; // [9:0] X12 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x13_s1               : 10; // [25:16] X13 for symbol 1
	} field;
} REG_OECF_X1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 1 
// Offset: 0x013C
typedef union _REG_OECF_X1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s1               : 10; // [9:0] X14 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x15_s1               : 10; // [25:16] X15 for symbol 1
	} field;
} REG_OECF_X1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x0140
typedef union _REG_OECF_X2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s2                : 10; // [9:0] X0 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s2                : 10; // [25:16] X1 for symbol 2
	} field;
} REG_OECF_X2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x0144
typedef union _REG_OECF_X2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s2                : 10; // [9:0] X2 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s2                : 10; // [25:16] X3 for symbol 2
	} field;
} REG_OECF_X2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x0148
typedef union _REG_OECF_X2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s2                : 10; // [9:0] X4 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x5_s2                : 10; // [25:16] X5 for symbol 2
	} field;
} REG_OECF_X2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x014C
typedef union _REG_OECF_X2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s2                : 10; // [9:0] X6 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x7_s2                : 10; // [25:16] X7 for symbol 2
	} field;
} REG_OECF_X2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x0150
typedef union _REG_OECF_X2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s2                : 10; // [9:0] X8 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x9_s2                : 10; // [25:16] X9 for symbol 2
	} field;
} REG_OECF_X2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x0154
typedef union _REG_OECF_X2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s2               : 10; // [9:0] X10 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x11_s2               : 10; // [25:16] X11 for symbol 2
	} field;
} REG_OECF_X2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x0158
typedef union _REG_OECF_X2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s2               : 10; // [9:0] X12 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x13_s2               : 10; // [25:16] X13 for symbol 2
	} field;
} REG_OECF_X2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 2 
// Offset: 0x015C
typedef union _REG_OECF_X2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s2               : 10; // [9:0] X14 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x15_s2               : 10; // [25:16] X15 for symbol 2
	} field;
} REG_OECF_X2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x0160
typedef union _REG_OECF_X3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s3                : 10; // [9:0] X0 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s3                : 10; // [25:16] X1 for symbol 3
	} field;
} REG_OECF_X3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x0164
typedef union _REG_OECF_X3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s3                : 10; // [9:0] X2 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s3                : 10; // [25:16] X3 for symbol 3
	} field;
} REG_OECF_X3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x0168
typedef union _REG_OECF_X3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s3                : 10; // [9:0] X4 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x5_s3                : 10; // [25:16] X5 for symbol 3
	} field;
} REG_OECF_X3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x016C
typedef union _REG_OECF_X3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s3                : 10; // [9:0] X6 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x7_s3                : 10; // [25:16] X7 for symbol 3
	} field;
} REG_OECF_X3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x0170
typedef union _REG_OECF_X3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s3                : 10; // [9:0] X8 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x9_s3                : 10; // [25:16] X9 for symbol 3
	} field;
} REG_OECF_X3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x0174
typedef union _REG_OECF_X3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s3               : 10; // [9:0] X10 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x11_s3               : 10; // [25:16] X11 for symbol 3
	} field;
} REG_OECF_X3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x0178
typedef union _REG_OECF_X3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s3               : 10; // [9:0] X12 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x13_s3               : 10; // [25:16] X13 for symbol 3
	} field;
} REG_OECF_X3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF X parameter[0.PW.0] register for symbol 3 
// Offset: 0x017C
typedef union _REG_OECF_X3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s3               : 10; // [9:0] X14 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x15_s3               : 10; // [25:16] X15 for symbol 3
	} field;
} REG_OECF_X3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x0180
typedef union _REG_OECF_Y0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s0                : 10; // [9:0] Y0 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s0                : 10; // [25:16] Y1 for symbol 0
	} field;
} REG_OECF_Y0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x0184
typedef union _REG_OECF_Y0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s0                : 10; // [9:0] Y2 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s0                : 10; // [25:16] Y3 for symbol 0
	} field;
} REG_OECF_Y0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x0188
typedef union _REG_OECF_Y0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s0                : 10; // [9:0] Y4 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y5_s0                : 10; // [25:16] Y5 for symbol 0
	} field;
} REG_OECF_Y0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x018C
typedef union _REG_OECF_Y0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s0                : 10; // [9:0] Y6 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y7_s0                : 10; // [25:16] Y7 for symbol 0
	} field;
} REG_OECF_Y0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x0190
typedef union _REG_OECF_Y0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s0                : 10; // [9:0] Y8 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y9_s0                : 10; // [25:16] Y9 for symbol 0
	} field;
} REG_OECF_Y0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x0194
typedef union _REG_OECF_Y0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s0               : 10; // [9:0] Y10 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y11_s0               : 10; // [25:16] Y11 for symbol 0
	} field;
} REG_OECF_Y0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x0198
typedef union _REG_OECF_Y0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s0               : 10; // [9:0] Y12 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y13_s0               : 10; // [25:16] Y13 for symbol 0
	} field;
} REG_OECF_Y0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x019C
typedef union _REG_OECF_Y0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s0               : 10; // [9:0] Y14 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y15_s0               : 10; // [25:16] Y15 for symbol 0
	} field;
} REG_OECF_Y0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01A0
typedef union _REG_OECF_Y1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s1                : 10; // [9:0] Y0 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s1                : 10; // [25:16] Y1 for symbol 1
	} field;
} REG_OECF_Y1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01A4
typedef union _REG_OECF_Y1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s1                : 10; // [9:0] Y2 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s1                : 10; // [25:16] Y3 for symbol 1
	} field;
} REG_OECF_Y1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01A8
typedef union _REG_OECF_Y1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s1                : 10; // [9:0] Y4 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y5_s1                : 10; // [25:16] Y5 for symbol 1
	} field;
} REG_OECF_Y1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01AC
typedef union _REG_OECF_Y1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s1                : 10; // [9:0] Y6 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y7_s1                : 10; // [25:16] Y7 for symbol 1
	} field;
} REG_OECF_Y1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01B0
typedef union _REG_OECF_Y1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s1                : 10; // [9:0] Y8 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y9_s1                : 10; // [25:16] Y9 for symbol 1
	} field;
} REG_OECF_Y1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01B4
typedef union _REG_OECF_Y1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s1               : 10; // [9:0] Y10 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y11_s1               : 10; // [25:16] Y11 for symbol 1
	} field;
} REG_OECF_Y1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01B8
typedef union _REG_OECF_Y1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s1               : 10; // [9:0] Y12 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y13_s1               : 10; // [25:16] Y13 for symbol 1
	} field;
} REG_OECF_Y1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x01BC
typedef union _REG_OECF_Y1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s1               : 10; // [9:0] Y14 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y15_s1               : 10; // [25:16] Y15 for symbol 1
	} field;
} REG_OECF_Y1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01C0
typedef union _REG_OECF_Y2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s2                : 10; // [9:0] Y0 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s2                : 10; // [25:16] Y1 for symbol 2
	} field;
} REG_OECF_Y2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01C4
typedef union _REG_OECF_Y2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s2                : 10; // [9:0] Y2 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s2                : 10; // [25:16] Y3 for symbol 2
	} field;
} REG_OECF_Y2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01C8
typedef union _REG_OECF_Y2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s2                : 10; // [9:0] Y4 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y5_s2                : 10; // [25:16] Y5 for symbol 2
	} field;
} REG_OECF_Y2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01CC
typedef union _REG_OECF_Y2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s2                : 10; // [9:0] Y6 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y7_s2                : 10; // [25:16] Y7 for symbol 2
	} field;
} REG_OECF_Y2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01D0
typedef union _REG_OECF_Y2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s2                : 10; // [9:0] Y8 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y9_s2                : 10; // [25:16] Y9 for symbol 2
	} field;
} REG_OECF_Y2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01D4
typedef union _REG_OECF_Y2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s2               : 10; // [9:0] Y10 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y11_s2               : 10; // [25:16] Y11 for symbol 2
	} field;
} REG_OECF_Y2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01D8
typedef union _REG_OECF_Y2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s2               : 10; // [9:0] Y12 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y13_s2               : 10; // [25:16] Y13 for symbol 2
	} field;
} REG_OECF_Y2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x01DC
typedef union _REG_OECF_Y2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s2               : 10; // [9:0] Y14 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y15_s2               : 10; // [25:16] Y15 for symbol 2
	} field;
} REG_OECF_Y2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01E0
typedef union _REG_OECF_Y3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s3                : 10; // [9:0] Y0 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s3                : 10; // [25:16] Y1 for symbol 3
	} field;
} REG_OECF_Y3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01E4
typedef union _REG_OECF_Y3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s3                : 10; // [9:0] Y2 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s3                : 10; // [25:16] Y3 for symbol 3
	} field;
} REG_OECF_Y3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01E8
typedef union _REG_OECF_Y3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s3                : 10; // [9:0] Y4 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y5_s3                : 10; // [25:16] Y5 for symbol 3
	} field;
} REG_OECF_Y3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01EC
typedef union _REG_OECF_Y3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s3                : 10; // [9:0] Y6 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y7_s3                : 10; // [25:16] Y7 for symbol 3
	} field;
} REG_OECF_Y3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01F0
typedef union _REG_OECF_Y3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s3                : 10; // [9:0] Y8 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y9_s3                : 10; // [25:16] Y9 for symbol 3
	} field;
} REG_OECF_Y3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01F4
typedef union _REG_OECF_Y3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s3               : 10; // [9:0] Y10 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y11_s3               : 10; // [25:16] Y11 for symbol 3
	} field;
} REG_OECF_Y3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01F8
typedef union _REG_OECF_Y3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s3               : 10; // [9:0] Y12 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y13_s3               : 10; // [25:16] Y13 for symbol 3
	} field;
} REG_OECF_Y3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x01FC
typedef union _REG_OECF_Y3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s3               : 10; // [9:0] Y14 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y15_s3               : 10; // [25:16] Y15 for symbol 3
	} field;
} REG_OECF_Y3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x0200
typedef union _REG_OECF_S0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s0                : 10; // [9:0] S0 for symbol 0 [0.3.7]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s0                : 10; // [25:16] S1 for symbol 0
	} field;
} REG_OECF_S0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x0204
typedef union _REG_OECF_S0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s0                : 10; // [9:0] S2 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s0                : 10; // [25:16] S3 for symbol 0
	} field;
} REG_OECF_S0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x0208
typedef union _REG_OECF_S0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s0                : 10; // [9:0] S4 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s5_s0                : 10; // [25:16] S5 for symbol 0
	} field;
} REG_OECF_S0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x020C
typedef union _REG_OECF_S0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s0                : 10; // [9:0] S6 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s7_s0                : 10; // [25:16] S7 for symbol 0
	} field;
} REG_OECF_S0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x0210
typedef union _REG_OECF_S0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s0                : 10; // [9:0] S8 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s9_s0                : 10; // [25:16] S9 for symbol 0
	} field;
} REG_OECF_S0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x0214
typedef union _REG_OECF_S0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s0               : 10; // [9:0] S10 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s11_s0               : 10; // [25:16] S11 for symbol 0
	} field;
} REG_OECF_S0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x0218
typedef union _REG_OECF_S0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s0               : 10; // [9:0] S12 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s13_s0               : 10; // [25:16] S13 for symbol 0
	} field;
} REG_OECF_S0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 0 
// Offset: 0x021C
typedef union _REG_OECF_S0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s0               : 10; // [9:0] S14 for symbol 0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s15_s0               : 10; // [25:16] S15 for symbol 0
	} field;
} REG_OECF_S0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x0220
typedef union _REG_OECF_S1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s1                : 10; // [9:0] S0 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s1                : 10; // [25:16] S1 for symbol 1
	} field;
} REG_OECF_S1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x0224
typedef union _REG_OECF_S1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s1                : 10; // [9:0] S2 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s1                : 10; // [25:16] S3 for symbol 1
	} field;
} REG_OECF_S1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x0228
typedef union _REG_OECF_S1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s1                : 10; // [9:0] S4 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s5_s1                : 10; // [25:16] S5 for symbol 1
	} field;
} REG_OECF_S1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x022C
typedef union _REG_OECF_S1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s1                : 10; // [9:0] S6 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s7_s1                : 10; // [25:16] S7 for symbol 1
	} field;
} REG_OECF_S1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x0230
typedef union _REG_OECF_S1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s1                : 10; // [9:0] S8 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s9_s1                : 10; // [25:16] S9 for symbol 1
	} field;
} REG_OECF_S1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x0234
typedef union _REG_OECF_S1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s1               : 10; // [9:0] S10 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s11_s1               : 10; // [25:16] S11 for symbol 1
	} field;
} REG_OECF_S1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x0238
typedef union _REG_OECF_S1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s1               : 10; // [9:0] S12 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s13_s1               : 10; // [25:16] S13 for symbol 1
	} field;
} REG_OECF_S1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 1 
// Offset: 0x023C
typedef union _REG_OECF_S1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s1               : 10; // [9:0] S14 for symbol 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s15_s1               : 10; // [25:16] S15 for symbol 1
	} field;
} REG_OECF_S1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x0240
typedef union _REG_OECF_S2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s2                : 10; // [9:0] S0 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s2                : 10; // [25:16] S1 for symbol 2
	} field;
} REG_OECF_S2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x0244
typedef union _REG_OECF_S2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s2                : 10; // [9:0] S2 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s2                : 10; // [25:16] S3 for symbol 2
	} field;
} REG_OECF_S2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x0248
typedef union _REG_OECF_S2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s2                : 10; // [9:0] S4 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s5_s2                : 10; // [25:16] S5 for symbol 2
	} field;
} REG_OECF_S2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x024C
typedef union _REG_OECF_S2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s2                : 10; // [9:0] S6 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s7_s2                : 10; // [25:16] S7 for symbol 2
	} field;
} REG_OECF_S2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x0250
typedef union _REG_OECF_S2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s2                : 10; // [9:0] S8 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s9_s2                : 10; // [25:16] S9 for symbol 2
	} field;
} REG_OECF_S2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x0254
typedef union _REG_OECF_S2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s2               : 10; // [9:0] S10 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s11_s2               : 10; // [25:16] S11 for symbol 2
	} field;
} REG_OECF_S2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x0258
typedef union _REG_OECF_S2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s2               : 10; // [9:0] S12 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s13_s2               : 10; // [25:16] S13 for symbol 2
	} field;
} REG_OECF_S2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 2 
// Offset: 0x025C
typedef union _REG_OECF_S2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s2               : 10; // [9:0] S14 for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s15_s2               : 10; // [25:16] S15 for symbol 2
	} field;
} REG_OECF_S2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x0260
typedef union _REG_OECF_S3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s3                : 10; // [9:0] S0 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s3                : 10; // [25:16] S1 for symbol 3
	} field;
} REG_OECF_S3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x0264
typedef union _REG_OECF_S3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s3                : 10; // [9:0] S2 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s3                : 10; // [25:16] S3 for symbol 3
	} field;
} REG_OECF_S3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x0268
typedef union _REG_OECF_S3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s3                : 10; // [9:0] S4 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s5_s3                : 10; // [25:16] S5 for symbol 3
	} field;
} REG_OECF_S3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x026C
typedef union _REG_OECF_S3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s3                : 10; // [9:0] S6 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s7_s3                : 10; // [25:16] S7 for symbol 3
	} field;
} REG_OECF_S3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x0270
typedef union _REG_OECF_S3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s3                : 10; // [9:0] S8 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s9_s3                : 10; // [25:16] S9 for symbol 3
	} field;
} REG_OECF_S3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x0274
typedef union _REG_OECF_S3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s3               : 10; // [9:0] S10 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s11_s3               : 10; // [25:16] S11 for symbol 3
	} field;
} REG_OECF_S3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x0278
typedef union _REG_OECF_S3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s3               : 10; // [9:0] S12 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s13_s3               : 10; // [25:16] S13 for symbol 3
	} field;
} REG_OECF_S3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF [0.3.7] S parameter register for symbol 3 
// Offset: 0x027C
typedef union _REG_OECF_S3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s3               : 10; // [9:0] S14 for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s15_s3               : 10; // [25:16] S15 for symbol 3
	} field;
} REG_OECF_S3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X0/X1 for symbol 0, each 10bits
// Offset: 0x0280
typedef union _REG_AWB_X0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s0                : 10; // [9:0] symbol_0 X0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s0                : 10; // [25:16] symbol_0 X1
	} field;
} REG_AWB_X0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X2/X3 for symbol 0, each 10bits
// Offset: 0x0284
typedef union _REG_AWB_X0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s0                : 10; // [9:0] symbol_0 X2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s0                : 10; // [25:16] symbol_0 X3
	} field;
} REG_AWB_X0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X0/X1 for symbol 1, each 10bits
// Offset: 0x0288
typedef union _REG_AWB_X1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s1                : 10; // [9:0] symbol_1 X0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s1                : 10; // [25:16] symbol_1 X1
	} field;
} REG_AWB_X1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X2/X3 for symbol 1, each 10bits
// Offset: 0x028C
typedef union _REG_AWB_X1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s1                : 10; // [9:0] symbol_1 X2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s1                : 10; // [25:16] symbol_1 X3
	} field;
} REG_AWB_X1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X0/X1 for symbol 2, each 10bits
// Offset: 0x0290
typedef union _REG_AWB_X2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s2                : 10; // [9:0] symbol_2 X0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s2                : 10; // [25:16] symbol_2 X1
	} field;
} REG_AWB_X2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X2/X3 for symbol 2, each 10bits
// Offset: 0x0294
typedef union _REG_AWB_X2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s2                : 10; // [9:0] symbol_2 X2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s2                : 10; // [25:16] symbol_2 X3
	} field;
} REG_AWB_X2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X0/X1 for symbol 3, each 10bits
// Offset: 0x0298
typedef union _REG_AWB_X3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s3                : 10; // [9:0] symbol_3 X0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x1_s3                : 10; // [25:16] symbol_3 X1
	} field;
} REG_AWB_X3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// X2/X3 for symbol 3, each 10bits
// Offset: 0x029C
typedef union _REG_AWB_X3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s3                : 10; // [9:0] symbol_3 X2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 x3_s3                : 10; // [25:16] symbol_3 X3
	} field;
} REG_AWB_X3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y0/Y1 for symbol 0, each 10bits
// Offset: 0x02A0
typedef union _REG_AWB_Y0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s0                : 10; // [9:0] symbol_0 Y0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s0                : 10; // [25:16] symbol_0 Y1
	} field;
} REG_AWB_Y0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y2/Y3 for symbol 0, each 10bits
// Offset: 0x02A4
typedef union _REG_AWB_Y0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s0                : 10; // [9:0] symbol_0 Y2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s0                : 10; // [25:16] symbol_0 Y3
	} field;
} REG_AWB_Y0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y0/Y1 for symbol 1, each 10bits
// Offset: 0x02A8
typedef union _REG_AWB_Y1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s1                : 10; // [9:0] symbol_1 Y0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s1                : 10; // [25:16] symbol_1 Y1
	} field;
} REG_AWB_Y1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y2/Y3 for symbol 1, each 10bits
// Offset: 0x02AC
typedef union _REG_AWB_Y1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s1                : 10; // [9:0] symbol_1 Y2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s1                : 10; // [25:16] symbol_1 Y3
	} field;
} REG_AWB_Y1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y0/Y1 for symbol 2, each 10bits
// Offset: 0x02B0
typedef union _REG_AWB_Y2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s2                : 10; // [9:0] symbol_2 Y0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s2                : 10; // [25:16] symbol_2 Y1
	} field;
} REG_AWB_Y2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y2/Y3 for symbol 2, each 10bits
// Offset: 0x02B4
typedef union _REG_AWB_Y2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s2                : 10; // [9:0] symbol_2 Y2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s2                : 10; // [25:16] symbol_2 Y3
	} field;
} REG_AWB_Y2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y0/Y1 for symbol 3, each 10bits
// Offset: 0x02B8
typedef union _REG_AWB_Y3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s3                : 10; // [9:0] symbol_3 Y0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y1_s3                : 10; // [25:16] symbol_3 Y1
	} field;
} REG_AWB_Y3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y2/Y3 for symbol 3, each 10bits
// Offset: 0x02BC
typedef union _REG_AWB_Y3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s3                : 10; // [9:0] symbol_3 Y2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 y3_s3                : 10; // [25:16] symbol_3 Y3
	} field;
} REG_AWB_Y3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S0/S1 for symbol 0, each 10bits
// Offset: 0x02C0
typedef union _REG_AWB_S0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s0                : 10; // [9:0] symbol_0 S0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s0                : 10; // [25:16] symbol_0 S1
	} field;
} REG_AWB_S0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S2/S3 for symbol 0, each 10bits
// Offset: 0x02C4
typedef union _REG_AWB_S0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s0                : 10; // [9:0] symbol_0 S2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s0                : 10; // [25:16] symbol_0 S3
	} field;
} REG_AWB_S0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S0/S1 for symbol 1, each 10bits
// Offset: 0x02C8
typedef union _REG_AWB_S1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s1                : 10; // [9:0] symbol_1 S0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s1                : 10; // [25:16] symbol_1 S1
	} field;
} REG_AWB_S1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S2/S3 for symbol 1, each 10bits
// Offset: 0x02CC
typedef union _REG_AWB_S1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s1                : 10; // [9:0] symbol_1 S2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s1                : 10; // [25:16] symbol_1 S3
	} field;
} REG_AWB_S1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S0/S1 for symbol 2, each 10bits
// Offset: 0x02D0
typedef union _REG_AWB_S2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s2                : 10; // [9:0] symbol_2 S0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s2                : 10; // [25:16] symbol_2 S1
	} field;
} REG_AWB_S2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S2/S3 for symbol 2, each 10bits
// Offset: 0x02D4
typedef union _REG_AWB_S2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s2                : 10; // [9:0] symbol_2 S2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s2                : 10; // [25:16] symbol_2 S3
	} field;
} REG_AWB_S2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S0/S1 for symbol 3, each 10bits
// Offset: 0x02D8
typedef union _REG_AWB_S3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s3                : 10; // [9:0] symbol_3 S0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s1_s3                : 10; // [25:16] symbol_3 S1
	} field;
} REG_AWB_S3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// [0.3.7] S2/S3 for symbol 3, each 10bits
// Offset: 0x02DC
typedef union _REG_AWB_S3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s3                : 10; // [9:0] symbol_3 S2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 s3_s3                : 10; // [25:16] symbol_3 S3
	} field;
} REG_AWB_S3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 8bit gain register
// Offset: 0x02E0
typedef union _REG_OBCG_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.2.6]Gain at point A for symbol 0
		UINT32 b_s0                 : 8 ; // [15:8] [0.2.6]Gain at point B for symbol 0
		UINT32 c_s0                 : 8 ; // [23:16] [0.2.6]Gain at point C for symbol 0
		UINT32 d_s0                 : 8 ; // [31:24] [0.2.6]Gain at point D for symbol 0
	} field;
} REG_OBCG_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 8bit gain register
// Offset: 0x02E4
typedef union _REG_OBCG_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.2.6]Gain at point A for symbol 1
		UINT32 b_s0                 : 8 ; // [15:8] [0.2.6]Gain at point B for symbol 1
		UINT32 c_s0                 : 8 ; // [23:16] [0.2.6]Gain at point C for symbol 1
		UINT32 d_s0                 : 8 ; // [31:24] [0.2.6]Gain at point D for symbol 1
	} field;
} REG_OBCG_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 8bit gain register
// Offset: 0x02E8
typedef union _REG_OBCG_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.2.6]Gain at point A for symbol 2
		UINT32 b_s0                 : 8 ; // [15:8] [0.2.6]Gain at point B for symbol 2
		UINT32 c_s0                 : 8 ; // [23:16] [0.2.6]Gain at point C for symbol 2
		UINT32 d_s0                 : 8 ; // [31:24] [0.2.6]Gain at point D for symbol 2
	} field;
} REG_OBCG_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 8bit gain register
// Offset: 0x02EC
typedef union _REG_OBCG_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.2.6]Gain at point A for symbol 3
		UINT32 b_s0                 : 8 ; // [15:8] [0.2.6]Gain at point B for symbol 3
		UINT32 c_s0                 : 8 ; // [23:16] [0.2.6]Gain at point C for symbol 3
		UINT32 d_s0                 : 8 ; // [31:24] [0.2.6]Gain at point D for symbol 3
	} field;
} REG_OBCG_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four points
// Offset: 0x02F0
typedef union _REG_OBCO_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.8.0] Offset at point A for symbol 0
		UINT32 b_s0                 : 8 ; // [15:8] [0.8.0] Offset at point B for symbol 0
		UINT32 c_s0                 : 8 ; // [23:16] [0.8.0] Offset at point C for symbol 0
		UINT32 d_s0                 : 8 ; // [31:24] [0.8.0] Offset at point D for symbol 0
	} field;
} REG_OBCO_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four points
// Offset: 0x02F4
typedef union _REG_OBCO_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.8.0] Offset at point A for symbol 1
		UINT32 b_s0                 : 8 ; // [15:8] [0.8.0] Offset at point B for symbol 1
		UINT32 c_s0                 : 8 ; // [23:16] [0.8.0] Offset at point C for symbol 1
		UINT32 d_s0                 : 8 ; // [31:24] [0.8.0] Offset at point D for symbol 1
	} field;
} REG_OBCO_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four points
// Offset: 0x02F8
typedef union _REG_OBCO_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.8.0] Offset at point A for symbol 2
		UINT32 b_s0                 : 8 ; // [15:8] [0.8.0] Offset at point B for symbol 2
		UINT32 c_s0                 : 8 ; // [23:16] [0.8.0] Offset at point C for symbol 2
		UINT32 d_s0                 : 8 ; // [31:24] [0.8.0] Offset at point D for symbol 2
	} field;
} REG_OBCO_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four points
// Offset: 0x02FC
typedef union _REG_OBCO_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 8 ; // [7:0] [0.8.0] Offset at point A for symbol 3
		UINT32 b_s0                 : 8 ; // [15:8] [0.8.0] Offset at point B for symbol 3
		UINT32 c_s0                 : 8 ; // [23:16] [0.8.0] Offset at point C for symbol 3
		UINT32 d_s0                 : 8 ; // [31:24] [0.8.0] Offset at point D for symbol 3
	} field;
} REG_OBCO_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0300
typedef union _REG_LCBQ_GAIN0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 g0_s0                : 9 ; // [8:0] G0 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g1_s0                : 9 ; // [24:16] G1 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0304
typedef union _REG_LCBQ_GAIN0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 g2_s0                : 9 ; // [8:0] G2 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g3_s0                : 9 ; // [24:16] G3 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0308
typedef union _REG_LCBQ_GAIN0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 g4_s0                : 9 ; // [8:0] G4 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g5_s0                : 9 ; // [24:16] G5 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x030C
typedef union _REG_LCBQ_GAIN0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 g6_s0                : 9 ; // [8:0] G6 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g7_s0                : 9 ; // [24:16] G7 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0310
typedef union _REG_LCBQ_GAIN0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 g8_s0                : 9 ; // [8:0] G8 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g9_s0                : 9 ; // [24:16] G9 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0314
typedef union _REG_LCBQ_GAIN0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 g10_s0               : 9 ; // [8:0] G10 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g11_s0               : 9 ; // [24:16] G11 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0318
typedef union _REG_LCBQ_GAIN0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 g12_s0               : 9 ; // [8:0] G12 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g13_s0               : 9 ; // [24:16] G13 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x031C
typedef union _REG_LCBQ_GAIN0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 g14_s0               : 9 ; // [8:0] G14 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g15_s0               : 9 ; // [24:16] G15 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0320
typedef union _REG_LCBQ_GAIN0_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 g16_s0               : 9 ; // [8:0] G16 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g17_s0               : 9 ; // [24:16] G17 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0324
typedef union _REG_LCBQ_GAIN0_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 g18_s0               : 9 ; // [8:0] G18 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g19_s0               : 9 ; // [24:16] G19 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0328
typedef union _REG_LCBQ_GAIN0_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 g20_s0               : 9 ; // [8:0] G20 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g21_s0               : 9 ; // [24:16] G21 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x032C
typedef union _REG_LCBQ_GAIN0_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 g22_s0               : 9 ; // [8:0] G22 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g23_s0               : 9 ; // [24:16] G23 for symbol 0
	} field;
} REG_LCBQ_GAIN0_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 0 
// Offset: 0x0330
typedef union _REG_LCBQ_GAIN0_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 g24_s0               : 9 ; // [8:0] G24 for symbol 0
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_GAIN0_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0334
typedef union _REG_LCBQ_GAIN1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 g0_s1                : 9 ; // [8:0] G0 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g1_s1                : 9 ; // [24:16] G1 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0338
typedef union _REG_LCBQ_GAIN1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 g2_s1                : 9 ; // [8:0] G2 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g3_s1                : 9 ; // [24:16] G3 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x033C
typedef union _REG_LCBQ_GAIN1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 g4_s1                : 9 ; // [8:0] G4 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g5_s1                : 9 ; // [24:16] G5 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0340
typedef union _REG_LCBQ_GAIN1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 g6_s1                : 9 ; // [8:0] G6 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g7_s1                : 9 ; // [24:16] G7 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0344
typedef union _REG_LCBQ_GAIN1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 g8_s1                : 9 ; // [8:0] G8 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g9_s1                : 9 ; // [24:16] G9 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0348
typedef union _REG_LCBQ_GAIN1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 g10_s1               : 9 ; // [8:0] G10 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g11_s1               : 9 ; // [24:16] G11 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x034C
typedef union _REG_LCBQ_GAIN1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 g12_s1               : 9 ; // [8:0] G12 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g13_s1               : 9 ; // [24:16] G13 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0350
typedef union _REG_LCBQ_GAIN1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 g14_s1               : 9 ; // [8:0] G14 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g15_s1               : 9 ; // [24:16] G15 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0354
typedef union _REG_LCBQ_GAIN1_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 g16_s1               : 9 ; // [8:0] G16 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g17_s1               : 9 ; // [24:16] G17 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0358
typedef union _REG_LCBQ_GAIN1_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 g18_s1               : 9 ; // [8:0] G18 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g19_s1               : 9 ; // [24:16] G19 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x035C
typedef union _REG_LCBQ_GAIN1_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 g20_s1               : 9 ; // [8:0] G20 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g21_s1               : 9 ; // [24:16] G21 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0360
typedef union _REG_LCBQ_GAIN1_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 g22_s1               : 9 ; // [8:0] G22 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g23_s1               : 9 ; // [24:16] G23 for symbol 1
	} field;
} REG_LCBQ_GAIN1_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 1 
// Offset: 0x0364
typedef union _REG_LCBQ_GAIN1_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 g24_s1               : 9 ; // [8:0] G24 for symbol 1
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_GAIN1_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0368
typedef union _REG_LCBQ_GAIN2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 g0_s2                : 9 ; // [8:0] G0 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g1_s2                : 9 ; // [24:16] G1 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x036C
typedef union _REG_LCBQ_GAIN2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 g2_s2                : 9 ; // [8:0] G2 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g3_s2                : 9 ; // [24:16] G3 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0370
typedef union _REG_LCBQ_GAIN2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 g4_s2                : 9 ; // [8:0] G4 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g5_s2                : 9 ; // [24:16] G5 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0374
typedef union _REG_LCBQ_GAIN2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 g6_s2                : 9 ; // [8:0] G6 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g7_s2                : 9 ; // [24:16] G7 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0378
typedef union _REG_LCBQ_GAIN2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 g8_s2                : 9 ; // [8:0] G8 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g9_s2                : 9 ; // [24:16] G9 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x037C
typedef union _REG_LCBQ_GAIN2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 g10_s2               : 9 ; // [8:0] G10 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g11_s2               : 9 ; // [24:16] G11 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0380
typedef union _REG_LCBQ_GAIN2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 g12_s2               : 9 ; // [8:0] G12 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g13_s2               : 9 ; // [24:16] G13 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0384
typedef union _REG_LCBQ_GAIN2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 g14_s2               : 9 ; // [8:0] G14 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g15_s2               : 9 ; // [24:16] G15 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0388
typedef union _REG_LCBQ_GAIN2_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 g16_s2               : 9 ; // [8:0] G16 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g17_s2               : 9 ; // [24:16] G17 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x038C
typedef union _REG_LCBQ_GAIN2_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 g18_s2               : 9 ; // [8:0] G18 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g19_s2               : 9 ; // [24:16] G19 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0390
typedef union _REG_LCBQ_GAIN2_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 g20_s2               : 9 ; // [8:0] G20 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g21_s2               : 9 ; // [24:16] G21 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0394
typedef union _REG_LCBQ_GAIN2_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 g22_s2               : 9 ; // [8:0] G22 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g23_s2               : 9 ; // [24:16] G23 for symbol 2
	} field;
} REG_LCBQ_GAIN2_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 2 
// Offset: 0x0398
typedef union _REG_LCBQ_GAIN2_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 g24_s2               : 9 ; // [8:0] G24 for symbol 2
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_GAIN2_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x039C
typedef union _REG_LCBQ_GAIN3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 g0_s3                : 9 ; // [8:0] G0 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g1_s3                : 9 ; // [24:16] G1 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03A0
typedef union _REG_LCBQ_GAIN3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 g2_s3                : 9 ; // [8:0] G2 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g3_s3                : 9 ; // [24:16] G3 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03A4
typedef union _REG_LCBQ_GAIN3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 g4_s3                : 9 ; // [8:0] G4 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g5_s3                : 9 ; // [24:16] G5 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03A8
typedef union _REG_LCBQ_GAIN3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 g6_s3                : 9 ; // [8:0] G6 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g7_s3                : 9 ; // [24:16] G7 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03AC
typedef union _REG_LCBQ_GAIN3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 g8_s3                : 9 ; // [8:0] G8 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g9_s3                : 9 ; // [24:16] G9 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03B0
typedef union _REG_LCBQ_GAIN3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 g10_s3               : 9 ; // [8:0] G10 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g11_s3               : 9 ; // [24:16] G11 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03B4
typedef union _REG_LCBQ_GAIN3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 g12_s3               : 9 ; // [8:0] G12 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g13_s3               : 9 ; // [24:16] G13 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03B8
typedef union _REG_LCBQ_GAIN3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 g14_s3               : 9 ; // [8:0] G14 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g15_s3               : 9 ; // [24:16] G15 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03BC
typedef union _REG_LCBQ_GAIN3_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 g16_s3               : 9 ; // [8:0] G16 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g17_s3               : 9 ; // [24:16] G17 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03C0
typedef union _REG_LCBQ_GAIN3_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 g18_s3               : 9 ; // [8:0] G18 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g19_s3               : 9 ; // [24:16] G19 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03C4
typedef union _REG_LCBQ_GAIN3_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 g20_s3               : 9 ; // [8:0] G20 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g21_s3               : 9 ; // [24:16] G21 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03C8
typedef union _REG_LCBQ_GAIN3_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 g22_s3               : 9 ; // [8:0] G22 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 g23_s3               : 9 ; // [24:16] G23 for symbol 3
	} field;
} REG_LCBQ_GAIN3_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [0.1.8] Gain parameter register for symbol 3 
// Offset: 0x03CC
typedef union _REG_LCBQ_GAIN3_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 g24_s3               : 9 ; // [8:0] G24 for symbol 3
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_GAIN3_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Hermite
// Offset: 0x03D0
typedef union _REG_OECFHM_Y_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0                   : 12; // [11:0] [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 y1                   : 12; // [27:16] [0.12.0]
	} field;
} REG_OECFHM_Y_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Hermite
// Offset: 0x03D4
typedef union _REG_OECFHM_Y_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2                   : 12; // [11:0] [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 y3                   : 12; // [27:16] [0.12.0]
	} field;
} REG_OECFHM_Y_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Hermite
// Offset: 0x03D8
typedef union _REG_OECFHM_Y_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4                   : 12; // [11:0] [0.12.0]
	} field;
} REG_OECFHM_Y_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Hermite
// Offset: 0x03DC
typedef union _REG_OECFHM_S_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0                   : 16; // [15:0] [1.4.11]
		UINT32 s1                   : 16; // [31:16] [1.4.11]
	} field;
} REG_OECFHM_S_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Hermite
// Offset: 0x03E0
typedef union _REG_OECFHM_S_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2                   : 16; // [15:0] [1.4.11]
		UINT32 s3                   : 16; // [31:16] [1.4.11]
	} field;
} REG_OECFHM_S_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF Hermite
// Offset: 0x03E4
typedef union _REG_OECFHM_S_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4                   : 16; // [15:0] [1.4.11]
	} field;
} REG_OECFHM_S_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0400
typedef union _REG_LCBQ_OFFSET0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s0                : 9 ; // [8:0] S0 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s1_s0                : 9 ; // [24:16] S1 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0404
typedef union _REG_LCBQ_OFFSET0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s0                : 9 ; // [8:0] S2 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s3_s0                : 9 ; // [24:16] S3 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0408
typedef union _REG_LCBQ_OFFSET0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s0                : 9 ; // [8:0] S4 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s5_s0                : 9 ; // [24:16] S5 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x040C
typedef union _REG_LCBQ_OFFSET0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s0                : 9 ; // [8:0] S6 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s7_s0                : 9 ; // [24:16] S7 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0410
typedef union _REG_LCBQ_OFFSET0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s0                : 9 ; // [8:0] S8 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s9_s0                : 9 ; // [24:16] S9 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0414
typedef union _REG_LCBQ_OFFSET0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s0               : 9 ; // [8:0] S10 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s11_s0               : 9 ; // [24:16] S11 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0418
typedef union _REG_LCBQ_OFFSET0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s0               : 9 ; // [8:0] S12 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s13_s0               : 9 ; // [24:16] S13 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x041C
typedef union _REG_LCBQ_OFFSET0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s0               : 9 ; // [8:0] S14 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s15_s0               : 9 ; // [24:16] S15 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0420
typedef union _REG_LCBQ_OFFSET0_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 s16_s0               : 9 ; // [8:0] S16 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s17_s0               : 9 ; // [24:16] S17 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0424
typedef union _REG_LCBQ_OFFSET0_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 s18_s0               : 9 ; // [8:0] S18 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s19_s0               : 9 ; // [24:16] S19 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0428
typedef union _REG_LCBQ_OFFSET0_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 s20_s0               : 9 ; // [8:0] S20 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s21_s0               : 9 ; // [24:16] S21 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x042C
typedef union _REG_LCBQ_OFFSET0_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 s22_s0               : 9 ; // [8:0] S22 for symbol 0
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s23_s0               : 9 ; // [24:16] S23 for symbol 0
	} field;
} REG_LCBQ_OFFSET0_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 0 
// Offset: 0x0430
typedef union _REG_LCBQ_OFFSET0_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 s24_s0               : 9 ; // [8:0] S24 for symbol 0
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_OFFSET0_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0434
typedef union _REG_LCBQ_OFFSET1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s1                : 9 ; // [8:0] S0 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s1_s1                : 9 ; // [24:16] S1 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0438
typedef union _REG_LCBQ_OFFSET1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s1                : 9 ; // [8:0] S2 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s3_s1                : 9 ; // [24:16] S3 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x043C
typedef union _REG_LCBQ_OFFSET1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s1                : 9 ; // [8:0] S4 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s5_s1                : 9 ; // [24:16] S5 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0440
typedef union _REG_LCBQ_OFFSET1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s1                : 9 ; // [8:0] S6 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s7_s1                : 9 ; // [24:16] S7 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0444
typedef union _REG_LCBQ_OFFSET1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s1                : 9 ; // [8:0] S8 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s9_s1                : 9 ; // [24:16] S9 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0448
typedef union _REG_LCBQ_OFFSET1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s1               : 9 ; // [8:0] S10 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s11_s1               : 9 ; // [24:16] S11 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x044C
typedef union _REG_LCBQ_OFFSET1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s1               : 9 ; // [8:0] S12 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s13_s1               : 9 ; // [24:16] S13 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0450
typedef union _REG_LCBQ_OFFSET1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s1               : 9 ; // [8:0] S14 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s15_s1               : 9 ; // [24:16] S15 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0454
typedef union _REG_LCBQ_OFFSET1_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 s16_s1               : 9 ; // [8:0] S16 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s17_s1               : 9 ; // [24:16] S17 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0458
typedef union _REG_LCBQ_OFFSET1_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 s18_s1               : 9 ; // [8:0] S18 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s19_s1               : 9 ; // [24:16] S19 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x045C
typedef union _REG_LCBQ_OFFSET1_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 s20_s1               : 9 ; // [8:0] S20 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s21_s1               : 9 ; // [24:16] S21 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0460
typedef union _REG_LCBQ_OFFSET1_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 s22_s1               : 9 ; // [8:0] S22 for symbol 1
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s23_s1               : 9 ; // [24:16] S23 for symbol 1
	} field;
} REG_LCBQ_OFFSET1_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 1 
// Offset: 0x0464
typedef union _REG_LCBQ_OFFSET1_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 s24_s1               : 9 ; // [8:0] S24 for symbol 1
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_OFFSET1_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0468
typedef union _REG_LCBQ_OFFSET2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s2                : 9 ; // [8:0] S0 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s1_s2                : 9 ; // [24:16] S1 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x046C
typedef union _REG_LCBQ_OFFSET2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s2                : 9 ; // [8:0] S2 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s3_s2                : 9 ; // [24:16] S3 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0470
typedef union _REG_LCBQ_OFFSET2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s2                : 9 ; // [8:0] S4 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s5_s2                : 9 ; // [24:16] S5 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0474
typedef union _REG_LCBQ_OFFSET2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s2                : 9 ; // [8:0] S6 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s7_s2                : 9 ; // [24:16] S7 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0478
typedef union _REG_LCBQ_OFFSET2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s2                : 9 ; // [8:0] S8 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s9_s2                : 9 ; // [24:16] S9 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x047C
typedef union _REG_LCBQ_OFFSET2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s2               : 9 ; // [8:0] S10 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s11_s2               : 9 ; // [24:16] S11 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0480
typedef union _REG_LCBQ_OFFSET2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s2               : 9 ; // [8:0] S12 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s13_s2               : 9 ; // [24:16] S13 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0484
typedef union _REG_LCBQ_OFFSET2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s2               : 9 ; // [8:0] S14 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s15_s2               : 9 ; // [24:16] S15 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0488
typedef union _REG_LCBQ_OFFSET2_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 s16_s2               : 9 ; // [8:0] S16 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s17_s2               : 9 ; // [24:16] S17 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x048C
typedef union _REG_LCBQ_OFFSET2_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 s18_s2               : 9 ; // [8:0] S18 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s19_s2               : 9 ; // [24:16] S19 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0490
typedef union _REG_LCBQ_OFFSET2_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 s20_s2               : 9 ; // [8:0] S20 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s21_s2               : 9 ; // [24:16] S21 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0494
typedef union _REG_LCBQ_OFFSET2_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 s22_s2               : 9 ; // [8:0] S22 for symbol 2
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s23_s2               : 9 ; // [24:16] S23 for symbol 2
	} field;
} REG_LCBQ_OFFSET2_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 2 
// Offset: 0x0498
typedef union _REG_LCBQ_OFFSET2_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 s24_s2               : 9 ; // [8:0] S24 for symbol 2
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_OFFSET2_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x049C
typedef union _REG_LCBQ_OFFSET3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s3                : 9 ; // [8:0] S0 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s1_s3                : 9 ; // [24:16] S1 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04A0
typedef union _REG_LCBQ_OFFSET3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s3                : 9 ; // [8:0] S2 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s3_s3                : 9 ; // [24:16] S3 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04A4
typedef union _REG_LCBQ_OFFSET3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s3                : 9 ; // [8:0] S4 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s5_s3                : 9 ; // [24:16] S5 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04A8
typedef union _REG_LCBQ_OFFSET3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s3                : 9 ; // [8:0] S6 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s7_s3                : 9 ; // [24:16] S7 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04AC
typedef union _REG_LCBQ_OFFSET3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s3                : 9 ; // [8:0] S8 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s9_s3                : 9 ; // [24:16] S9 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04B0
typedef union _REG_LCBQ_OFFSET3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s3               : 9 ; // [8:0] S10 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s11_s3               : 9 ; // [24:16] S11 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04B4
typedef union _REG_LCBQ_OFFSET3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s3               : 9 ; // [8:0] S12 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s13_s3               : 9 ; // [24:16] S13 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04B8
typedef union _REG_LCBQ_OFFSET3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s3               : 9 ; // [8:0] S14 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s15_s3               : 9 ; // [24:16] S15 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04BC
typedef union _REG_LCBQ_OFFSET3_CFG_8
{
	UINT32 value;
	struct
	{
		UINT32 s16_s3               : 9 ; // [8:0] S16 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s17_s3               : 9 ; // [24:16] S17 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04C0
typedef union _REG_LCBQ_OFFSET3_CFG_9
{
	UINT32 value;
	struct
	{
		UINT32 s18_s3               : 9 ; // [8:0] S18 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s19_s3               : 9 ; // [24:16] S19 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04C4
typedef union _REG_LCBQ_OFFSET3_CFG_10
{
	UINT32 value;
	struct
	{
		UINT32 s20_s3               : 9 ; // [8:0] S20 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s21_s3               : 9 ; // [24:16] S21 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04C8
typedef union _REG_LCBQ_OFFSET3_CFG_11
{
	UINT32 value;
	struct
	{
		UINT32 s22_s3               : 9 ; // [8:0] S22 for symbol 3
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 s23_s3               : 9 ; // [24:16] S23 for symbol 3
	} field;
} REG_LCBQ_OFFSET3_CFG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LCBQ [1.8.0] Offset parameter register for symbol 3 
// Offset: 0x04CC
typedef union _REG_LCBQ_OFFSET3_CFG_12
{
	UINT32 value;
	struct
	{
		UINT32 s24_s3               : 9 ; // [8:0] S24 for symbol 3
		UINT32 rsvd9                : 23; // [31:9] 
	} field;
} REG_LCBQ_OFFSET3_CFG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(0,0~7), each 4bits
// Offset: 0x04D0
typedef union _REG_SC_AWB_WS_CW0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_0_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(0,0)
		UINT32 awb_ws_cw_w_0_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(0,1)
		UINT32 awb_ws_cw_w_0_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(0,2)
		UINT32 awb_ws_cw_w_0_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(0,3)
		UINT32 awb_ws_cw_w_0_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(0,4)
		UINT32 awb_ws_cw_w_0_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(0,5)
		UINT32 awb_ws_cw_w_0_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(0,6)
		UINT32 awb_ws_cw_w_0_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(0,7), [c][r]
	} field;
} REG_SC_AWB_WS_CW0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(0,8~12), each 4bits
// Offset: 0x04D4
typedef union _REG_SC_AWB_WS_CW0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_0_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(0,8)
		UINT32 awb_ws_cw_w_0_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(0,9)
		UINT32 awb_ws_cw_w_0_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(0,10)
		UINT32 awb_ws_cw_w_0_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(0,11)
		UINT32 awb_ws_cw_w_0_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(0,12)
	} field;
} REG_SC_AWB_WS_CW0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(1,0~7), each 4bits
// Offset: 0x04D8
typedef union _REG_SC_AWB_WS_CW1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_1_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(1,0)
		UINT32 awb_ws_cw_w_1_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(1,1)
		UINT32 awb_ws_cw_w_1_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(1,2)
		UINT32 awb_ws_cw_w_1_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(1,3)
		UINT32 awb_ws_cw_w_1_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(1,4)
		UINT32 awb_ws_cw_w_1_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(1,5)
		UINT32 awb_ws_cw_w_1_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(1,6)
		UINT32 awb_ws_cw_w_1_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(1,7)
	} field;
} REG_SC_AWB_WS_CW1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(1,8~12), each 4bits
// Offset: 0x04DC
typedef union _REG_SC_AWB_WS_CW1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_1_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(1,8)
		UINT32 awb_ws_cw_w_1_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(1,9)
		UINT32 awb_ws_cw_w_1_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(1,10)
		UINT32 awb_ws_cw_w_1_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(1,11)
		UINT32 awb_ws_cw_w_1_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(1,12)
	} field;
} REG_SC_AWB_WS_CW1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(2,0~7), each 4bits
// Offset: 0x04E0
typedef union _REG_SC_AWB_WS_CW2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_2_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(2,0)
		UINT32 awb_ws_cw_w_2_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(2,1)
		UINT32 awb_ws_cw_w_2_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(2,2)
		UINT32 awb_ws_cw_w_2_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(2,3)
		UINT32 awb_ws_cw_w_2_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(2,4)
		UINT32 awb_ws_cw_w_2_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(2,5)
		UINT32 awb_ws_cw_w_2_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(2,6)
		UINT32 awb_ws_cw_w_2_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(2,7)
	} field;
} REG_SC_AWB_WS_CW2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(2,8~12), each 4bits
// Offset: 0x04E4
typedef union _REG_SC_AWB_WS_CW2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_2_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(2,8)
		UINT32 awb_ws_cw_w_2_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(2,9)
		UINT32 awb_ws_cw_w_2_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(2,10)
		UINT32 awb_ws_cw_w_2_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(2,11)
		UINT32 awb_ws_cw_w_2_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(2,12)
	} field;
} REG_SC_AWB_WS_CW2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(3,0~7), each 4bits
// Offset: 0x04E8
typedef union _REG_SC_AWB_WS_CW3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_3_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(3,0)
		UINT32 awb_ws_cw_w_3_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(3,1)
		UINT32 awb_ws_cw_w_3_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(3,2)
		UINT32 awb_ws_cw_w_3_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(3,3)
		UINT32 awb_ws_cw_w_3_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(3,4)
		UINT32 awb_ws_cw_w_3_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(3,5)
		UINT32 awb_ws_cw_w_3_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(3,6)
		UINT32 awb_ws_cw_w_3_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(3,7)
	} field;
} REG_SC_AWB_WS_CW3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(3,8~12), each 4bits
// Offset: 0x04EC
typedef union _REG_SC_AWB_WS_CW3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_3_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(3,8)
		UINT32 awb_ws_cw_w_3_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(3,9)
		UINT32 awb_ws_cw_w_3_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(3,10)
		UINT32 awb_ws_cw_w_3_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(3,11)
		UINT32 awb_ws_cw_w_3_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(3,12)
	} field;
} REG_SC_AWB_WS_CW3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(4,0~7), each 4bits
// Offset: 0x04F0
typedef union _REG_SC_AWB_WS_CW4_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_4_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(4,0)
		UINT32 awb_ws_cw_w_4_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(4,1)
		UINT32 awb_ws_cw_w_4_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(4,2)
		UINT32 awb_ws_cw_w_4_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(4,3)
		UINT32 awb_ws_cw_w_4_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(4,4)
		UINT32 awb_ws_cw_w_4_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(4,5)
		UINT32 awb_ws_cw_w_4_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(4,6)
		UINT32 awb_ws_cw_w_4_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(4,7)
	} field;
} REG_SC_AWB_WS_CW4_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(4,8~12), each 4bits
// Offset: 0x04F4
typedef union _REG_SC_AWB_WS_CW4_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_4_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(4,8)
		UINT32 awb_ws_cw_w_4_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(4,9)
		UINT32 awb_ws_cw_w_4_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(4,10)
		UINT32 awb_ws_cw_w_4_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(4,11)
		UINT32 awb_ws_cw_w_4_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(4,12)
	} field;
} REG_SC_AWB_WS_CW4_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(5,0~7), each 4bits
// Offset: 0x04F8
typedef union _REG_SC_AWB_WS_CW5_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_5_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(5,0)
		UINT32 awb_ws_cw_w_5_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(5,1)
		UINT32 awb_ws_cw_w_5_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(5,2)
		UINT32 awb_ws_cw_w_5_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(5,3)
		UINT32 awb_ws_cw_w_5_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(5,4)
		UINT32 awb_ws_cw_w_5_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(5,5)
		UINT32 awb_ws_cw_w_5_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(5,6)
		UINT32 awb_ws_cw_w_5_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(5,7)
	} field;
} REG_SC_AWB_WS_CW5_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(5,8~12), each 4bits
// Offset: 0x04FC
typedef union _REG_SC_AWB_WS_CW5_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_5_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(5,8)
		UINT32 awb_ws_cw_w_5_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(5,9)
		UINT32 awb_ws_cw_w_5_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(5,10)
		UINT32 awb_ws_cw_w_5_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(5,11)
		UINT32 awb_ws_cw_w_5_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(5,12)
	} field;
} REG_SC_AWB_WS_CW5_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(6,0~7), each 4bits
// Offset: 0x0500
typedef union _REG_SC_AWB_WS_CW6_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_6_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(6,0)
		UINT32 awb_ws_cw_w_6_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(6,1)
		UINT32 awb_ws_cw_w_6_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(6,2)
		UINT32 awb_ws_cw_w_6_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(6,3)
		UINT32 awb_ws_cw_w_6_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(6,4)
		UINT32 awb_ws_cw_w_6_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(6,5)
		UINT32 awb_ws_cw_w_6_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(6,6)
		UINT32 awb_ws_cw_w_6_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(6,7)
	} field;
} REG_SC_AWB_WS_CW6_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(6,8~12), each 4bits
// Offset: 0x0504
typedef union _REG_SC_AWB_WS_CW6_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_6_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(6,8)
		UINT32 awb_ws_cw_w_6_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(6,9)
		UINT32 awb_ws_cw_w_6_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(6,10)
		UINT32 awb_ws_cw_w_6_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(6,11)
		UINT32 awb_ws_cw_w_6_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(6,12)
	} field;
} REG_SC_AWB_WS_CW6_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(7,0~7), each 4bits
// Offset: 0x0508
typedef union _REG_SC_AWB_WS_CW7_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_7_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(7,0)
		UINT32 awb_ws_cw_w_7_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(7,1)
		UINT32 awb_ws_cw_w_7_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(7,2)
		UINT32 awb_ws_cw_w_7_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(7,3)
		UINT32 awb_ws_cw_w_7_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(7,4)
		UINT32 awb_ws_cw_w_7_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(7,5)
		UINT32 awb_ws_cw_w_7_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(7,6)
		UINT32 awb_ws_cw_w_7_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(7,7)
	} field;
} REG_SC_AWB_WS_CW7_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(7,8~12), each 4bits
// Offset: 0x050C
typedef union _REG_SC_AWB_WS_CW7_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_7_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(7,8)
		UINT32 awb_ws_cw_w_7_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(7,9)
		UINT32 awb_ws_cw_w_7_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(7,10)
		UINT32 awb_ws_cw_w_7_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(7,11)
		UINT32 awb_ws_cw_w_7_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(7,12)
	} field;
} REG_SC_AWB_WS_CW7_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(8,0~7), each 4bits
// Offset: 0x0510
typedef union _REG_SC_AWB_WS_CW8_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_8_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(8,0)
		UINT32 awb_ws_cw_w_8_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(8,1)
		UINT32 awb_ws_cw_w_8_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(8,2)
		UINT32 awb_ws_cw_w_8_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(8,3)
		UINT32 awb_ws_cw_w_8_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(8,4)
		UINT32 awb_ws_cw_w_8_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(8,5)
		UINT32 awb_ws_cw_w_8_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(8,6)
		UINT32 awb_ws_cw_w_8_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(8,7)
	} field;
} REG_SC_AWB_WS_CW8_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(8,8~12), each 4bits
// Offset: 0x0514
typedef union _REG_SC_AWB_WS_CW8_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_8_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(8,8)
		UINT32 awb_ws_cw_w_8_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(8,9)
		UINT32 awb_ws_cw_w_8_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(8,10)
		UINT32 awb_ws_cw_w_8_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(8,11)
		UINT32 awb_ws_cw_w_8_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(8,12)
	} field;
} REG_SC_AWB_WS_CW8_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(9,0~7), each 4bits
// Offset: 0x0518
typedef union _REG_SC_AWB_WS_CW9_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_9_0      : 4 ; // [3:0] [0.4.0]Weighting value at point(9,0)
		UINT32 awb_ws_cw_w_9_1      : 4 ; // [7:4] [0.4.0]Weighting value at point(9,1)
		UINT32 awb_ws_cw_w_9_2      : 4 ; // [11:8] [0.4.0]Weighting value at point(9,2)
		UINT32 awb_ws_cw_w_9_3      : 4 ; // [15:12] [0.4.0]Weighting value at point(9,3)
		UINT32 awb_ws_cw_w_9_4      : 4 ; // [19:16] [0.4.0]Weighting value at point(9,4)
		UINT32 awb_ws_cw_w_9_5      : 4 ; // [23:20] [0.4.0]Weighting value at point(9,5)
		UINT32 awb_ws_cw_w_9_6      : 4 ; // [27:24] [0.4.0]Weighting value at point(9,6)
		UINT32 awb_ws_cw_w_9_7      : 4 ; // [31:28] [0.4.0]Weighting value at point(9,7)
	} field;
} REG_SC_AWB_WS_CW9_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(9,8~12), each 4bits
// Offset: 0x051C
typedef union _REG_SC_AWB_WS_CW9_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_9_8      : 4 ; // [3:0] [0.4.0]Weighting value at point(9,8)
		UINT32 awb_ws_cw_w_9_9      : 4 ; // [7:4] [0.4.0]Weighting value at point(9,9)
		UINT32 awb_ws_cw_w_9_10     : 4 ; // [11:8] [0.4.0]Weighting value at point(9,10)
		UINT32 awb_ws_cw_w_9_11     : 4 ; // [15:12] [0.4.0]Weighting value at point(9,11)
		UINT32 awb_ws_cw_w_9_12     : 4 ; // [19:16] [0.4.0]Weighting value at point(9,12)
	} field;
} REG_SC_AWB_WS_CW9_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(10,0~7), each 4bits
// Offset: 0x0520
typedef union _REG_SC_AWB_WS_CW10_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_10_0     : 4 ; // [3:0] [0.4.0]Weighting value at point(10,0)
		UINT32 awb_ws_cw_w_10_1     : 4 ; // [7:4] [0.4.0]Weighting value at point(10,1)
		UINT32 awb_ws_cw_w_10_2     : 4 ; // [11:8] [0.4.0]Weighting value at point(10,2)
		UINT32 awb_ws_cw_w_10_3     : 4 ; // [15:12] [0.4.0]Weighting value at point(10,3)
		UINT32 awb_ws_cw_w_10_4     : 4 ; // [19:16] [0.4.0]Weighting value at point(10,4)
		UINT32 awb_ws_cw_w_10_5     : 4 ; // [23:20] [0.4.0]Weighting value at point(10,5)
		UINT32 awb_ws_cw_w_10_6     : 4 ; // [27:24] [0.4.0]Weighting value at point(10,6)
		UINT32 awb_ws_cw_w_10_7     : 4 ; // [31:28] [0.4.0]Weighting value at point(10,7)
	} field;
} REG_SC_AWB_WS_CW10_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(10,8~12), each 4bits
// Offset: 0x0524
typedef union _REG_SC_AWB_WS_CW10_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_10_8     : 4 ; // [3:0] [0.4.0]Weighting value at point(10,8)
		UINT32 awb_ws_cw_w_10_9     : 4 ; // [7:4] [0.4.0]Weighting value at point(10,9)
		UINT32 awb_ws_cw_w_10_10    : 4 ; // [11:8] [0.4.0]Weighting value at point(10,10)
		UINT32 awb_ws_cw_w_10_11    : 4 ; // [15:12] [0.4.0]Weighting value at point(10,11)
		UINT32 awb_ws_cw_w_10_12    : 4 ; // [19:16] [0.4.0]Weighting value at point(10,12)
	} field;
} REG_SC_AWB_WS_CW10_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(11,0~7), each 4bits
// Offset: 0x0528
typedef union _REG_SC_AWB_WS_CW11_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_11_0     : 4 ; // [3:0] [0.4.0]Weighting value at point(11,0)
		UINT32 awb_ws_cw_w_11_1     : 4 ; // [7:4] [0.4.0]Weighting value at point(11,1)
		UINT32 awb_ws_cw_w_11_2     : 4 ; // [11:8] [0.4.0]Weighting value at point(11,2)
		UINT32 awb_ws_cw_w_11_3     : 4 ; // [15:12] [0.4.0]Weighting value at point(11,3)
		UINT32 awb_ws_cw_w_11_4     : 4 ; // [19:16] [0.4.0]Weighting value at point(11,4)
		UINT32 awb_ws_cw_w_11_5     : 4 ; // [23:20] [0.4.0]Weighting value at point(11,5)
		UINT32 awb_ws_cw_w_11_6     : 4 ; // [27:24] [0.4.0]Weighting value at point(11,6)
		UINT32 awb_ws_cw_w_11_7     : 4 ; // [31:28] [0.4.0]Weighting value at point(11,7)
	} field;
} REG_SC_AWB_WS_CW11_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(11,8~12), each 4bits
// Offset: 0x052C
typedef union _REG_SC_AWB_WS_CW11_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_11_8     : 4 ; // [3:0] [0.4.0]Weighting value at point(11,8)
		UINT32 awb_ws_cw_w_11_9     : 4 ; // [7:4] [0.4.0]Weighting value at point(11,9)
		UINT32 awb_ws_cw_w_11_10    : 4 ; // [11:8] [0.4.0]Weighting value at point(11,10)
		UINT32 awb_ws_cw_w_11_11    : 4 ; // [15:12] [0.4.0]Weighting value at point(11,11)
		UINT32 awb_ws_cw_w_11_12    : 4 ; // [19:16] [0.4.0]Weighting value at point(11,12)
	} field;
} REG_SC_AWB_WS_CW11_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(12,0~7), each 4bits
// Offset: 0x0530
typedef union _REG_SC_AWB_WS_CW12_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_12_0     : 4 ; // [3:0] [0.4.0]Weighting value at point(12,0)
		UINT32 awb_ws_cw_w_12_1     : 4 ; // [7:4] [0.4.0]Weighting value at point(12,1)
		UINT32 awb_ws_cw_w_12_2     : 4 ; // [11:8] [0.4.0]Weighting value at point(12,2)
		UINT32 awb_ws_cw_w_12_3     : 4 ; // [15:12] [0.4.0]Weighting value at point(12,3)
		UINT32 awb_ws_cw_w_12_4     : 4 ; // [19:16] [0.4.0]Weighting value at point(12,4)
		UINT32 awb_ws_cw_w_12_5     : 4 ; // [23:20] [0.4.0]Weighting value at point(12,5)
		UINT32 awb_ws_cw_w_12_6     : 4 ; // [27:24] [0.4.0]Weighting value at point(12,6)
		UINT32 awb_ws_cw_w_12_7     : 4 ; // [31:28] [0.4.0]Weighting value at point(12,7)
	} field;
} REG_SC_AWB_WS_CW12_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(12,8~12), each 4bits
// Offset: 0x0534
typedef union _REG_SC_AWB_WS_CW12_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_cw_w_12_8     : 4 ; // [3:0] [0.4.0]Weighting value at point(12,8)
		UINT32 awb_ws_cw_w_12_9     : 4 ; // [7:4] [0.4.0]Weighting value at point(12,9)
		UINT32 awb_ws_cw_w_12_10    : 4 ; // [11:8] [0.4.0]Weighting value at point(12,10)
		UINT32 awb_ws_cw_w_12_11    : 4 ; // [15:12] [0.4.0]Weighting value at point(12,11)
		UINT32 awb_ws_cw_w_12_12    : 4 ; // [19:16] [0.4.0]Weighting value at point(12,12)
	} field;
} REG_SC_AWB_WS_CW12_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(0~7), each 4bits
// Offset: 0x0538
typedef union _REG_SC_AWB_WS_IWV_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_iw_v_0        : 4 ; // [3:0] [0.4.0]Weighting value at point(0)
		UINT32 awb_ws_iw_v_1        : 4 ; // [7:4] [0.4.0]Weighting value at point(1)
		UINT32 awb_ws_iw_v_2        : 4 ; // [11:8] [0.4.0]Weighting value at point(2)
		UINT32 awb_ws_iw_v_3        : 4 ; // [15:12] [0.4.0]Weighting value at point(3)
		UINT32 awb_ws_iw_v_4        : 4 ; // [19:16] [0.4.0]Weighting value at point(4)
		UINT32 awb_ws_iw_v_5        : 4 ; // [23:20] [0.4.0]Weighting value at point(5)
		UINT32 awb_ws_iw_v_6        : 4 ; // [27:24] [0.4.0]Weighting value at point(6)
		UINT32 awb_ws_iw_v_7        : 4 ; // [31:28] [0.4.0]Weighting value at point(7)
	} field;
} REG_SC_AWB_WS_IWV_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Weighting value at point(8~15), each 4bits
// Offset: 0x053C
typedef union _REG_SC_AWB_WS_IWV_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_iw_v_8        : 4 ; // [3:0] [0.4.0]Weighting value at point(8)
		UINT32 awb_ws_iw_v_9        : 4 ; // [7:4] [0.4.0]Weighting value at point(9)
		UINT32 awb_ws_iw_v_10       : 4 ; // [11:8] [0.4.0]Weighting value at point(10)
		UINT32 awb_ws_iw_v_11       : 4 ; // [15:12] [0.4.0]Weighting value at point(11)
		UINT32 awb_ws_iw_v_12       : 4 ; // [19:16] [0.4.0]Weighting value at point(12)
		UINT32 awb_ws_iw_v_13       : 4 ; // [23:20] [0.4.0]Weighting value at point(13)
		UINT32 awb_ws_iw_v_14       : 4 ; // [27:24] [0.4.0]Weighting value at point(14)
		UINT32 awb_ws_iw_v_15       : 4 ; // [31:28] [0.4.0]Weighting value at point(15)
	} field;
} REG_SC_AWB_WS_IWV_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Slope value at point(0~3), each 8bits
// Offset: 0x0540
typedef union _REG_SC_AWB_WS_IWS_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_iw_s_0        : 8 ; // [7:0] [1.2.5]Slope value at point(0)
		UINT32 awb_ws_iw_s_1        : 8 ; // [15:8] [1.2.5]Slope value at point(1)
		UINT32 awb_ws_iw_s_2        : 8 ; // [23:16] [1.2.5]Slope value at point(2)
		UINT32 awb_ws_iw_s_3        : 8 ; // [31:24] [1.2.5]Slope value at point(3)
	} field;
} REG_SC_AWB_WS_IWS_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Slope value at point(4~7), each 8bits
// Offset: 0x0544
typedef union _REG_SC_AWB_WS_IWS_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_iw_s_4        : 8 ; // [7:0] [1.2.5]Slope value at point(4)
		UINT32 awb_ws_iw_s_5        : 8 ; // [15:8] [1.2.5]Slope value at point(5)
		UINT32 awb_ws_iw_s_6        : 8 ; // [23:16] [1.2.5]Slope value at point(6)
		UINT32 awb_ws_iw_s_7        : 8 ; // [31:24] [1.2.5]Slope value at point(7)
	} field;
} REG_SC_AWB_WS_IWS_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Slope value at point(8~11), each 8bits
// Offset: 0x0548
typedef union _REG_SC_AWB_WS_IWS_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_iw_s_8        : 8 ; // [7:0] [1.2.5]Slope value at point(8)
		UINT32 awb_ws_iw_s_9        : 8 ; // [15:8] [1.2.5]Slope value at point(9)
		UINT32 awb_ws_iw_s_10       : 8 ; // [23:16] [1.2.5]Slope value at point(10)
		UINT32 awb_ws_iw_s_11       : 8 ; // [31:24] [1.2.5]Slope value at point(11)
	} field;
} REG_SC_AWB_WS_IWS_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Slope value at point(12~15), each 8bits
// Offset: 0x054C
typedef union _REG_SC_AWB_WS_IWS_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_iw_s_12       : 8 ; // [7:0] [1.2.5]Slope value at point(12)
		UINT32 awb_ws_iw_s_13       : 8 ; // [15:8] [1.2.5]Slope value at point(13)
		UINT32 awb_ws_iw_s_14       : 8 ; // [23:16] [1.2.5]Slope value at point(14)
		UINT32 awb_ws_iw_s_15       : 8 ; // [31:24] [1.2.5]Slope value at point(15)
	} field;
} REG_SC_AWB_WS_IWS_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AWB weight sum registers0
// Offset: 0x05D0
typedef union _REG_SC_AWB_WS_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_rl            : 8 ; // [7:0] [0.8.0]Lower boundary of R value
		UINT32 awb_ws_ru            : 8 ; // [15:8] [0.8.0]Upper boundary of R value
		UINT32 awb_ws_grl           : 8 ; // [23:16] [0.8.0]Lower boundary of Gr value
		UINT32 awb_ws_gru           : 8 ; // [31:24] [0.8.0]Upper boundary of Gr value
	} field;
} REG_SC_AWB_WS_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC AWB weight sum registers1
// Offset: 0x05D4
typedef union _REG_SC_AWB_WS_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 awb_ws_gbl           : 8 ; // [7:0] [0.8.0]Lower boundary of Gb value
		UINT32 awb_ws_gbu           : 8 ; // [15:8] [0.8.0]Upper boundary of Gb value
		UINT32 awb_ws_bl            : 8 ; // [23:16] [0.8.0]Lower boundary of B value
		UINT32 awb_ws_bu            : 8 ; // [31:24] [0.8.0]Upper boundary of B value
	} field;
} REG_SC_AWB_WS_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Frame Size
// Offset: 0x0600
typedef union _REG_CSICBFS
{
	UINT32 value;
	struct
	{
		UINT32 htotal               : 13; // [12:0] Color bar frame width (xsize)
		UINT32 rsvd13               : 3 ; // [15:13] Reserved
		UINT32 vtotal               : 13; // [28:16] Color bar frame height (ysize)
	} field;
} REG_CSICBFS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Frame Start
// Offset: 0x0604
typedef union _REG_CSICBS
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 13; // [12:0] Horizontal start point
		UINT32 rsvd13               : 3 ; // [15:13] Reserved
		UINT32 vstart               : 13; // [28:16] Vertical start point
	} field;
} REG_CSICBS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Frame End
// Offset: 0x0608
typedef union _REG_CSICBE
{
	UINT32 value;
	struct
	{
		UINT32 hend                 : 13; // [12:0] Pixel value
		UINT32 rsvd13               : 3 ; // [15:13] Reserved
		UINT32 vend                 : 13; // [28:16] Pixel value
	} field;
} REG_CSICBE;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Mode 0
// Offset: 0x060C
typedef union _REG_CSICBMD0
{
	UINT32 value;
	struct
	{
		UINT32 tg_en                : 1 ; // [0] Enable Timing Genrator
		UINT32 rsvd1                : 3 ; // [3:1] Reserved
		UINT32 dvp_en               : 1 ; // [4] Enable DVP Mux (switch to test pattern)
		UINT32 mipi_en              : 1 ; // [5] Enable MIPI Mux (switch to test pattern)
        UINT32 sync_csi             : 1 ; // [6] Wait for CSI enable (Color Bar Generator starts in sync with CSI enable).
        UINT32 rsvd7                : 1 ; // [7] Reserved.
		UINT32 hpolarity            : 1 ; // [8] H Sync Polarity
		UINT32 vpolarity            : 1 ; // [9] V Sync Polarity
		UINT32 rsvd10               : 2 ; // [11:10] Reserved
		UINT32 pattern              : 4 ; // [15:12] Pattern type:
		UINT32 hwidth               : 4 ; // [19:16] Horizontal bar width: 2^(WIDTH+1)
		UINT32 vwidth               : 4 ; // [23:20] Vertical bar width: 2^(WIDTH+1)
	} field;
} REG_CSICBMD0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Mode 1
// Offset: 0x0610
typedef union _REG_CSICBMD1
{
	UINT32 value;
	struct
	{
		UINT32 md                   : 32; // [31:0] Mode
	} field;
} REG_CSICBMD1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel 01
// Offset: 0x0614
typedef union _REG_CSICBP01
{
	UINT32 value;
	struct
	{
		UINT32 p0                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p1                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBP01;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel 23
// Offset: 0x0618
typedef union _REG_CSICBP23
{
	UINT32 value;
	struct
	{
		UINT32 p2                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p3                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBP23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel 45
// Offset: 0x061C
typedef union _REG_CSICBP45
{
	UINT32 value;
	struct
	{
		UINT32 p4                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p5                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBP45;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel 67
// Offset: 0x0620
typedef union _REG_CSICBP67
{
	UINT32 value;
	struct
	{
		UINT32 p6                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p7                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBP67;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel 89
// Offset: 0x0624
typedef union _REG_CSICBP89
{
	UINT32 value;
	struct
	{
		UINT32 p8                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p9                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBP89;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel AB
// Offset: 0x0628
typedef union _REG_CSICBPAB
{
	UINT32 value;
	struct
	{
		UINT32 pa                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 pb                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBPAB;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel CD
// Offset: 0x062C
typedef union _REG_CSICBPCD
{
	UINT32 value;
	struct
	{
		UINT32 pc                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 pd                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBPCD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Pixel EF
// Offset: 0x0630
typedef union _REG_CSICBPEF
{
	UINT32 value;
	struct
	{
		UINT32 pe                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 pf                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBPEF;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel 01
// Offset: 0x0634
typedef union _REG_CSICBL1P01
{
	UINT32 value;
	struct
	{
		UINT32 p0                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p1                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1P01;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel 23
// Offset: 0x0638
typedef union _REG_CSICBL1P23
{
	UINT32 value;
	struct
	{
		UINT32 p2                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p3                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1P23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel 45
// Offset: 0x063C
typedef union _REG_CSICBL1P45
{
	UINT32 value;
	struct
	{
		UINT32 p4                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p5                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1P45;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel 67
// Offset: 0x0640
typedef union _REG_CSICBL1P67
{
	UINT32 value;
	struct
	{
		UINT32 p6                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p7                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1P67;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel 89
// Offset: 0x0644
typedef union _REG_CSICBL1P89
{
	UINT32 value;
	struct
	{
		UINT32 p8                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 p9                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1P89;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel AB
// Offset: 0x0648
typedef union _REG_CSICBL1PAB
{
	UINT32 value;
	struct
	{
		UINT32 pa                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 pb                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1PAB;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel CD
// Offset: 0x064C
typedef union _REG_CSICBL1PCD
{
	UINT32 value;
	struct
	{
		UINT32 pc                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 pd                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1PCD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Bar Line 1 Pixel EF
// Offset: 0x0650
typedef union _REG_CSICBL1PEF
{
	UINT32 value;
	struct
	{
		UINT32 pe                   : 12; // [11:0] Pixel value
		UINT32 rsvd12               : 4 ; // [15:12] Reserved
		UINT32 pf                   : 12; // [27:16] Pixel value
	} field;
} REG_CSICBL1PEF;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP Control Register 0
// Offset: 0x0A00
typedef union _REG_ISPCTRL0
{
	UINT32 value;
	struct
	{
		UINT32 en                   : 1 ; // [0] Enable ISP processor.
		UINT32 rst                  : 1 ; // [1] Reset/initialize ISP processor.
		UINT32 enilc                : 1 ; // [2] Reserved.
		UINT32 rstilc               : 1 ; // [3] Reserved.
		UINT32 envs                 : 1 ; // [4] Reserved.
		UINT32 rstvs                : 1 ; // [5] Reserved.
		UINT32 rsvd6                : 2 ; // [7:6] Reserved.
		UINT32 enlc                 : 1 ; // [8] Reserved.
		UINT32 enov                 : 1 ; // [9] Reserved.
		UINT32 endn                 : 1 ; // [10] Reserved.
		UINT32 enss0                : 1 ; // [11] Enable Scaled Stream 0.
		UINT32 enss1                : 1 ; // [12] Enable Scaled Stream 1.
		UINT32 envsrc               : 1 ; // [13] Reserved.
		UINT32 envsr                : 1 ; // [14] Reserved.
		UINT32 envencl              : 1 ; // [15] Reserved.
		UINT32 enlclb               : 1 ; // [16] Reserved.
		UINT32 enls                 : 1 ; // [17] Enable ISP multiple frame mode.
		UINT32 rsvd18               : 2 ; // [19:18] Reserved. These bits always return zero when read.
		UINT32 enuo                 : 1 ; // [20] Enable Unscaled Output.
		UINT32 rsvd21               : 2 ; // [22:21] Reserved.
		UINT32 rstvencl             : 1 ; // [23] Reserved.
		UINT32 ints                 : 1 ; // [24] ISP module done interrupt. No trigger if none of scalar outputs is enabled.
		UINT32 vsint                : 1 ; // [25] CSI capture end interrupt bit.
		UINT32 vsfwint              : 1 ; // [26] SC dump done interrupt bit. No trigger if SC is disabled.
		UINT32 lberrint             : 1 ; // [27] Line interrupt bit.
		UINT32 rdmaint              : 1 ; // [28] Reserved.
		UINT32 rsvd29               : 3 ; // [31:29] Reserved. These bits always return zero when read.
	} field;
} REG_ISPCTRL0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP status
// Offset: 0x0A04
typedef union _REG_ISPSTAT0
{
	UINT32 value;
	struct
	{
		UINT32 stat0                : 1 ; // [0] ISP run status.
		UINT32 stat_uo              : 1 ; // [1] Unscaled Output run status.
		UINT32 stat_ss0             : 1 ; // [2] Scaler 0 run status.
		UINT32 stat_ss1             : 1 ; // [3] scaler 1 run status.
		UINT32 stat1                : 1 ; // [4] Reserved.
		UINT32 stat2                : 1 ; // [5] Reserved.
		UINT32 rsvd6                : 2 ; // [7:6] Reserved. These bits always return zero when read.
		UINT32 lberr                : 1 ; // [8] Reserved.
		UINT32 ciferr               : 1 ; // [9] CSI interface buffer located in between CSI and ISP status.
		UINT32 rsvd10               : 22; // [31:10] Reserved. These bits always return zero when read.
	} field;
} REG_ISPSTAT0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP Control Register 1
// Offset: 0x0A08
typedef union _REG_ISPCTRL1
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 1 ; // [0] Reserved.
		UINT32 ce                   : 1 ; // [1] CFA filter enable.
		UINT32 ae                   : 1 ; // [2] Color Artifact removal filter enable.
		UINT32 cme                  : 1 ; // [3] Color Correction Matrix enable.
		UINT32 rge                  : 1 ; // [4] RGB Gamma enable.
		UINT32 cce                  : 1 ; // [5] RGB to YUV color space conversion enable.
		UINT32 lne                  : 1 ; // [6] Reserved.
		UINT32 ee                   : 1 ; // [7] Sharpening and Edge Enhancement enable.
		UINT32 sce                  : 1 ; // [8] Hue, Saturation, Brightness, Contrast enable.
		UINT32 cae                  : 1 ; // [9] Reserved.
		UINT32 pfe                  : 1 ; // [10] Reserved.
		UINT32 nwcl                 : 1 ; // [11] Reserved.
		UINT32 fwbg                 : 1 ; // [12] Reserved.
		UINT32 nl2d                 : 1 ; // [13] Reserved.
		UINT32 rwbg                 : 1 ; // [14] Reserved.
		UINT32 lute                 : 1 ; // [15] Reserved.
		UINT32 nwed                 : 1 ; // [16] Reserved.
		UINT32 biyuv                : 1 ; // [17] BiYUV enable
		UINT32 ctm                  : 1 ; // [18] Reserved.
		UINT32 ycurve               : 1 ; // [19] Y Curve  enable
		UINT32 yhist                : 1 ; // [20] Y Histogram enable
		UINT32 ctc                  : 1 ; // [21] CTC filter enable.
		UINT32 dbc                  : 1 ; // [22] DBC filter enable.
		UINT32 rsvd23               : 5 ; // [27:23] 
		UINT32 sat                  : 2 ; // [29:28] This register defines the first component of image sensor array.
	} field;
} REG_ISPCTRL1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// isp pipeline X/Y size, each 13bits(after decimation)
// Offset: 0x0A0C
typedef union _REG_IFSZ
{
	UINT32 value;
	struct
	{
		UINT32 w                    : 13; // [12:0] Active capture area width(xsize)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h                    : 13; // [28:16] Active capture area height(ysize)
		UINT32 rsvd29               : 3 ; // [31:29] 
	} field;
} REG_IFSZ;

////////////////////////////////////////////////////////////////////////////////////////////////////
// GrGb Filter threshold 1 Register
// Offset: 0x0A10
typedef union _REG_ICTC
{
	UINT32 value;
	struct
	{
		UINT32 mingt                : 10; // [9:0] (0.PW.0 format)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 maxgt                : 10; // [25:16] (0.PW.0 format)
		UINT32 rsvd26               : 4 ; // [29:26] 
		UINT32 gf_mode              : 2 ; // [31:30] GrGb filter mode
	} field;
} REG_ICTC;

////////////////////////////////////////////////////////////////////////////////////////////////////
// GrGb filter threshold 2 Register
// Offset: 0x0A14
typedef union _REG_IDBC
{
	UINT32 value;
	struct
	{
		UINT32 badxt                : 10; // [9:0] (0.PW.0 format)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 badgt                : 10; // [25:16] (0.PW.0 format)
	} field;
} REG_IDBC;

////////////////////////////////////////////////////////////////////////////////////////////////////
// CFA Mode Register
// Offset: 0x0A1C
typedef union _REG_ICFAM
{
	UINT32 value;
	struct
	{
		UINT32 hv_width             : 4 ; // [3:0] HW_WIDTH=2**HV_WIDTH(0~3)
		UINT32 cross_cov            : 2 ; // [5:4] Cross covariance weighting
	} field;
} REG_ICFAM;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chroma Saturation Gain
// Offset: 0x0A30
typedef union _REG_ISAT0
{
	UINT32 value;
	struct
	{
		UINT32 cmab                 : 11; // [10:0] Chroma Magnitude Amplification Base (Format: 0.3.8.)
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 cmmd                 : 12; // [27:16] Chroma Magnitude Amplification Delta (Format 1.3.8)
	} field;
} REG_ISAT0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chroma Saturation Threshold
// Offset: 0x0A34
typedef union _REG_ISAT1
{
	UINT32 value;
	struct
	{
		UINT32 cmb                  : 11; // [10:0] Chroma Magnitude Base, Format: 0.11.0
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 cmd                  : 12; // [27:16] Chroma Magnitude Delta, Format: 1.11.0
	} field;
} REG_ISAT1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chroma Saturation UV Offset
// Offset: 0x0A38
typedef union _REG_ISAT2
{
	UINT32 value;
	struct
	{
		UINT32 uoff                 : 11; // [10:0] U offset, Format: 1.10.0
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 voff                 : 11; // [26:16] V offset
	} field;
} REG_ISAT2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chroma Saturation Hue Factor 
// Offset: 0x0A3C
typedef union _REG_ISAT3
{
	UINT32 value;
	struct
	{
		UINT32 cos                  : 9 ; // [8:0] COS hue factor, Hue adjustment rotation factor. Format: 0.1.8
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 sin                  : 10; // [25:16] SIN hue factor,Hue adjustment rotation factor. Format: 1.1.8
	} field;
} REG_ISAT3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chroma Saturation scaling coefficient
// Offset: 0x0A40
typedef union _REG_ISAT4
{
	UINT32 value;
	struct
	{
		UINT32 cmsf                 : 4 ; // [3:0] Chroma Magnitude Scaling Factor
	} field;
} REG_ISAT4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Image engine shadow control Register
// Offset: 0x0A50
typedef union _REG_IESHD
{
	UINT32 value;
	struct
	{
		UINT32 ud                   : 1 ; // [0] Shadow update enable
		UINT32 udm                  : 1 ; // [1] Shadow update mode
	} field;
} REG_IESHD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Adjustment Register 0
// Offset: 0x0A54
typedef union _REG_IYADJ0
{
	UINT32 value;
	struct
	{
		UINT32 yimin                : 10; // [9:0] This register specifies the minimum input Y value. Format: 0.10.0
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yoir                 : 14; // [29:16] This register specifies the ratio of Y output range to input range. Format: 0.4.10
	} field;
} REG_IYADJ0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Adjustment Register 1
// Offset: 0x0A58
typedef union _REG_IYADJ1
{
	UINT32 value;
	struct
	{
		UINT32 yomin                : 10; // [9:0] This register specifies the minimum output Y value. Format 0.10.0.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yomax                : 10; // [25:16] This register specifies the maximum output Y value. Format: 0.10.0.
	} field;
} REG_IYADJ1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Unscaled Output Image Y Plane Start Address Register
// Offset: 0x0A80
typedef union _REG_UOAY
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sad                  : 29; // [31:3] Base address in QWORD (64bit) boundary
	} field;
} REG_UOAY;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Unscaled Output Image UV Plane Start Address Register
// Offset: 0x0A84
typedef union _REG_UOAUV
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sad                  : 29; // [31:3] Base address in QWORD (64bit) boundary
	} field;
} REG_UOAUV;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Unscaled Output Image Stride Register
// Offset: 0x0A88
typedef union _REG_UOS
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sd                   : 10; // [12:3] Image stride QWORD (64bit) granularity
	} field;
} REG_UOS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Unscaled Output Pixel Coordinate Generator Mode Register
// Offset: 0x0A8C
typedef union _REG_UOPGM
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 5 ; // [4:0] Reserved
		UINT32 nv21                 : 1 ; // [5] UO, SS0, and SS1 output UV order
	} field;
} REG_UOPGM;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Unscaled Output AXI Control Register
// Offset: 0x0A90
typedef union _REG_UOAXI
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] Reserved
		UINT32 refwid               : 8 ; // [15:8] Reference image AXI write ID
	} field;
} REG_UOAXI;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS0 Output Image Y Plane Start Address Register
// Offset: 0x0A94
typedef union _REG_SS0AY
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sad                  : 29; // [31:3] Base address in QWORD (64bit) boundary
	} field;
} REG_SS0AY;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS0 Output Image UV Plane Start Address Register
// Offset: 0x0A98
typedef union _REG_SS0AUV
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sad                  : 29; // [31:3] Base address in QWORD (64bit) boundary
	} field;
} REG_SS0AUV;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS0 Output Image Stride Register
// Offset: 0x0A9C
typedef union _REG_SS0S
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sd                   : 10; // [12:3] Image stride QWORD (64bit) granularity
	} field;
} REG_SS0S;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS0 H Scaling Factor Register
// Offset: 0x0AA0
typedef union _REG_SS0HF
{
	UINT32 value;
	struct
	{
		UINT32 sm                   : 2 ; // [1:0] Scaling mode
		UINT32 rsvd2                : 14; // [15:2] Reserved
		UINT32 sf                   : 12; // [27:16] Scaling factor (format 0.0.12)
	} field;
} REG_SS0HF;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS0 V Scaling Factor Register
// Offset: 0x0AA4
typedef union _REG_SS0VF
{
	UINT32 value;
	struct
	{
		UINT32 sm                   : 2 ; // [1:0] Scaling mode
		UINT32 rsvd2                : 14; // [15:2] Reserved
		UINT32 sf                   : 12; // [27:16] Scaling factor (format 0.0.12)
	} field;
} REG_SS0VF;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS0 Output Image Size Register
// Offset: 0x0AA8
typedef union _REG_SS0IW
{
	UINT32 value;
	struct
	{
		UINT32 h                    : 13; // [12:0] Output image height
		UINT32 rsvd13               : 3 ; // [15:13] Reserved
		UINT32 w                    : 13; // [28:16] Output image width
	} field;
} REG_SS0IW;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS1 Output Image Y Plane Start Address Register
// Offset: 0x0AAC
typedef union _REG_SS1AY
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sad                  : 29; // [31:3] Base address in QWORD (64bit) boundary
	} field;
} REG_SS1AY;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS1 Output Image UV Plane Start Address Register
// Offset: 0x0AB0
typedef union _REG_SS1AUV
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sad                  : 29; // [31:3] Base address in QWORD (64bit) boundary
	} field;
} REG_SS1AUV;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS1 Output Image Stride Register
// Offset: 0x0AB4
typedef union _REG_SS1S
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 sd                   : 10; // [12:3] Image stride QWORD (64bit) granularity
	} field;
} REG_SS1S;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS1 H Scaling Factor Register
// Offset: 0x0AB8
typedef union _REG_SS1HF
{
	UINT32 value;
	struct
	{
		UINT32 sm                   : 2 ; // [1:0] Scaling mode
		UINT32 rsvd2                : 14; // [15:2] Reserved
		UINT32 sf                   : 12; // [27:16] Scaling factor (format 0.0.12)
	} field;
} REG_SS1HF;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS1 V Scaling Factor Register
// Offset: 0x0ABC
typedef union _REG_SS1VF
{
	UINT32 value;
	struct
	{
		UINT32 sm                   : 2 ; // [1:0] Scaling mode
		UINT32 rsvd2                : 14; // [15:2] Reserved
		UINT32 sf                   : 12; // [27:16] Scaling factor (format 0.0.12)
	} field;
} REG_SS1VF;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS1 Output Image Size Register
// Offset: 0x0AC0
typedef union _REG_SS1IW
{
	UINT32 value;
	struct
	{
		UINT32 h                    : 13; // [12:0] Output image height
		UINT32 rsvd13               : 3 ; // [15:13] Reserved
		UINT32 w                    : 13; // [28:16] Output image width
	} field;
} REG_SS1IW;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SS AXI Control Register
// Offset: 0x0AC4
typedef union _REG_SSAXI
{
	UINT32 value;
	struct
	{
		UINT32 ss0wid               : 8 ; // [7:0] SS0 image AXI write ID
		UINT32 ss1wid               : 8 ; // [15:8] SS1 image AXI write ID
	} field;
} REG_SSAXI;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI image window size register
// Offset: 0x0B20
typedef union _REG_ITIIWSR
{
	UINT32 value;
	struct
	{
		UINT32 wsize                : 16; // [15:0] The width of image window size
		UINT32 hsize                : 16; // [31:16] The height of image window size
	} field;
} REG_ITIIWSR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM write line stride register
// Offset: 0x0B24
typedef union _REG_ITIDWLSR
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 wstride              : 20; // [22:3] The line stride of the next line address in DRAM buffer (8-byte alignment)
	} field;
} REG_ITIDWLSR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM write Y start address register
// Offset: 0x0B28
typedef union _REG_ITIDWYSAR
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 wyaddr               : 29; // [31:3] Data buffer start address for writing RAW/Y plane in DRAM buffer (8-byte alignment)
	} field;
} REG_ITIDWYSAR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM write UV start address register
// Offset: 0x0B2C
typedef union _REG_ITIDWUSAR
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 wuvaddr              : 29; // [31:3] Data buffer start address for writing UV plane in DRAM buffer (8-byte alignment)
	} field;
} REG_ITIDWUSAR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM read Y start address register
// Offset: 0x0B30
typedef union _REG_ITIDRYSAR
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 ryaddr               : 29; // [31:3] Data buffer start address for reading RAW/Y plane in DRAM buffer (8-byte alignment)
	} field;
} REG_ITIDRYSAR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM read UV start address register
// Offset: 0x0B34
typedef union _REG_ITIDRUSAR
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 ruvaddr              : 29; // [31:3] Data buffer start address for reading UV plane in DRAM buffer (8-byte alignment)
	} field;
} REG_ITIDRUSAR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI package data format register
// Offset: 0x0B38
typedef union _REG_ITIPDFR
{
	UINT32 value;
	struct
	{
		UINT32 wrformat             : 3 ; // [2:0] Data package format type
		UINT32 imgispraw10          : 1 ; // [3] RAW10bit format is changed to IMG ISP RAW 10 bit format (IMG 3 pack in a DW)
		UINT32 wrflexiblebit        : 5 ; // [8:4] The bit number of one RAW for data format is 3'h7 (first pixel offset)
		UINT32 rsvd9                : 7 ; // [15:9] Reserved
		UINT32 rdformat             : 3 ; // [18:16] Data package format type
		UINT32 rdlinebufoff         : 1 ; // [19] Disable UV line buffer function for YUV de-package flow.
		UINT32 rdflexiblebit        : 5 ; // [24:20] The bit number of one RAW for data format is 3'h7 (first pixel offset)
	} field;
} REG_ITIPDFR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM read line stride register
// Offset: 0x0B3C
typedef union _REG_ITIDRLSR
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] Reserved
		UINT32 rstride              : 20; // [22:3] The line stride of the next line address in DRAM buffer (8-byte alignment)
	} field;
} REG_ITIDRLSR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP tiling interface BUSY status register
// Offset: 0x0B40
typedef union _REG_ITIBSR
{
	UINT32 value;
	struct
	{
		UINT32 wbusy                : 1 ; // [0] 1: The ISP tiling interface status is busy for writing processes
		UINT32 rbusy                : 1 ; // [1] 1: The ISP tiling interface status is busy for reading processes
		UINT32 rsvd2                : 30; // [31:2] Reserved
	} field;
} REG_ITIBSR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP tiling interface AXI ID register
// Offset: 0x0B44
typedef union _REG_ITIAIR
{
	UINT32 value;
	struct
	{
		UINT32 ywid                 : 8 ; // [7:0] The AXI ID of the Y AXI write controller
		UINT32 uvwid                : 8 ; // [15:8] The AXI ID of the UV AXI write controller
		UINT32 yrid                 : 8 ; // [23:16] The AXI ID of the Y AXI read controller
		UINT32 uvrid                : 8 ; // [31:24] The AXI ID of the UV AXI read controller
	} field;
} REG_ITIAIR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP tiling interface data path select register
// Offset: 0x0B48
typedef union _REG_ITIDPSR
{
	UINT32 value;
	struct
	{
		UINT32 readindex            : 8 ; // [7:0] The index of the selected module whose input will be selected from DRAM buffer
		UINT32 writeindex           : 8 ; // [15:8] The index of the selected module whose output will be written into DRAM buffer
		UINT32 readdram             : 1 ; // [16] Enable the read function of the ITI interface from DRAM buffer
		UINT32 writedram            : 1 ; // [17] Enable the write function of the ITI interface into DRAM buffer
		UINT32 loopback             : 1 ; // [18] Enable the loop back self test where the write AXI controller obtains the input data from the AXI read controller
		UINT32 movedramdata         : 1 ; // [19] Enable the move data function from the reading address to the writing address. (move data directly from read to write, can be used for copying data)
		UINT32 independentrdrvi     : 1 ; // [20] Enable the independent  READ RVI signal function under  the normal  DRAM read mode.
		UINT32 rsvd21               : 3 ; // [23:21] Reserved
		UINT32 rdnv21format         : 1 ; // [24] Enable  YCrCb 420  NV21 Data format  in DRAM package for the Reading path
		UINT32 wrnv21format         : 1 ; // [25] Enable  YCrCb 420 NV21 Data format in DRAM package for the Writing path
		UINT32 rsvd26               : 6 ; // [31:26] Reserved
	} field;
} REG_ITIDPSR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV Y channel S weight table register 0
// Offset: 0x0C00
typedef union _REG_DNYUV_YSWR0
{
	UINT32 value;
	struct
	{
		UINT32 yswa                 : 3 ; // [2:0] [0.3.0], y channel yeWsa
		UINT32 rsvd3                : 1 ; // [3] 
		UINT32 yswb                 : 3 ; // [6:4] [0.3.0], y channel yeWsb
		UINT32 rsvd7                : 1 ; // [7] 
		UINT32 yswc                 : 3 ; // [10:8] [0.3.0], y channel yeWsc
		UINT32 rsvd11               : 1 ; // [11] 
		UINT32 yswd                 : 3 ; // [14:12] [0.3.0], y channel yeWsd
		UINT32 rsvd15               : 1 ; // [15] 
		UINT32 yswe                 : 3 ; // [18:16] [0.3.0], y channel yeWse
		UINT32 rsvd19               : 1 ; // [19] 
		UINT32 yswf                 : 3 ; // [22:20] [0.3.0], y channel yeWsf
		UINT32 rsvd23               : 9 ; // [31:23] 
	} field;
} REG_DNYUV_YSWR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV Y channel S weight table register 1
// Offset: 0x0C04
typedef union _REG_DNYUV_YSWR1
{
	UINT32 value;
	struct
	{
		UINT32 yswg                 : 3 ; // [2:0] [0.3.0], y channel yeWsg
		UINT32 rsvd3                : 1 ; // [3] 
		UINT32 yswh                 : 3 ; // [6:4] [0.3.0], y channel yeWsh
		UINT32 rsvd7                : 1 ; // [7] 
		UINT32 yswi                 : 3 ; // [10:8] [0.3.0], y channel yeWsi
		UINT32 rsvd11               : 1 ; // [11] 
		UINT32 yswj                 : 4 ; // [15:12] [0.3.0], y channel yeWsj
	} field;
} REG_DNYUV_YSWR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV UV channel S weight table register 0
// Offset: 0x0C08
typedef union _REG_DNYUV_CSWR0
{
	UINT32 value;
	struct
	{
		UINT32 cswa                 : 3 ; // [2:0] [0.3.0], uv channel ceWsa
		UINT32 rsvd3                : 1 ; // [3] 
		UINT32 cswb                 : 3 ; // [6:4] [0.3.0], uv channel ceWsb
		UINT32 rsvd7                : 1 ; // [7] 
		UINT32 cswc                 : 3 ; // [10:8] [0.3.0], uv channel ceWsc
		UINT32 rsvd11               : 1 ; // [11] 
		UINT32 cswd                 : 3 ; // [14:12] [0.3.0], uv channel ceWsd
		UINT32 rsvd15               : 1 ; // [15] 
		UINT32 cswe                 : 3 ; // [18:16] [0.3.0], uv channel ceWse
		UINT32 rsvd19               : 1 ; // [19] 
		UINT32 cswf                 : 3 ; // [22:20] [0.3.0], uv channel ceWsf
		UINT32 rsvd23               : 9 ; // [31:23] 
	} field;
} REG_DNYUV_CSWR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV UV channel S weight table register  1
// Offset: 0x0C0C
typedef union _REG_DNYUV_CSWR1
{
	UINT32 value;
	struct
	{
		UINT32 cswg                 : 3 ; // [2:0] [0.3.0], uv channel ceWsg
		UINT32 rsvd3                : 1 ; // [3] 
		UINT32 cswh                 : 3 ; // [6:4] [0.3.0], uv channel ceWsh
		UINT32 rsvd7                : 1 ; // [7] 
		UINT32 cswi                 : 3 ; // [10:8] [0.3.0], uv channel ceWsi
		UINT32 rsvd11               : 1 ; // [11] 
		UINT32 cswj                 : 3 ; // [14:12] [0.3.0], uv channel ceWsj
	} field;
} REG_DNYUV_CSWR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV Y Curve D component register 0
// Offset: 0x0C10
typedef union _REG_DNYUV_YDR0
{
	UINT32 value;
	struct
	{
		UINT32 yd0                  : 10; // [9:0] [0.10.0], Curve D components for Y
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yd1                  : 10; // [25:16] [0.10.0], Curve D components for Y
	} field;
} REG_DNYUV_YDR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV Y Curve D component register 1
// Offset: 0x0C14
typedef union _REG_DNYUV_YDR1
{
	UINT32 value;
	struct
	{
		UINT32 yd2                  : 10; // [9:0] [0.10.0], Curve D components for Y
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yd3                  : 10; // [25:16] [0.10.0], Curve D components for Y
	} field;
} REG_DNYUV_YDR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV Y Curve D component register 2
// Offset: 0x0C18
typedef union _REG_DNYUV_YDR2
{
	UINT32 value;
	struct
	{
		UINT32 yd4                  : 10; // [9:0] [0.10.0], Curve D components for Y
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yd5                  : 10; // [25:16] [0.10.0], Curve D components for Y
	} field;
} REG_DNYUV_YDR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV UV Curve D component register 0
// Offset: 0x0C1C
typedef union _REG_DNYUV_CDR0
{
	UINT32 value;
	struct
	{
		UINT32 cd0                  : 10; // [9:0] [0.10.0], Curve D components for UV
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 cd1                  : 10; // [25:16] [0.10.0], Curve D components for UV
	} field;
} REG_DNYUV_CDR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV UV Curve D component register 1
// Offset: 0x0C20
typedef union _REG_DNYUV_CDR1
{
	UINT32 value;
	struct
	{
		UINT32 cd2                  : 10; // [9:0] [0.10.0], Curve D components for UV
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 cd3                  : 10; // [25:16] [0.10.0], Curve D components for UV
	} field;
} REG_DNYUV_CDR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DNYUV UV Curve D component register 2
// Offset: 0x0C24
typedef union _REG_DNYUV_CDR2
{
	UINT32 value;
	struct
	{
		UINT32 cd4                  : 10; // [9:0] [0.10.0], Curve D components for UV
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 cd5                  : 10; // [25:16] [0.10.0], Curve D components for UV
	} field;
} REG_DNYUV_CDR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix register
// Offset: 0x0C40
typedef union _REG_ICAMD_0
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter , r1g1_1/smatrix11 [1.3.7]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 dnrm                 : 4 ; // [19:16] Color matrix threshold denormalization factor.
	} field;
} REG_ICAMD_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C44
typedef union _REG_ICAMD_1
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter , r1g2_1/smatrix12 [1.3.7]
	} field;
} REG_ICAMD_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C48
typedef union _REG_ICAMD_2
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r1g3_1/smatrix13 [1.3.7]
	} field;
} REG_ICAMD_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C4C
typedef union _REG_ICAMD_3
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r2g1_1/smatrix21  [1.3.7]
	} field;
} REG_ICAMD_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C50
typedef union _REG_ICAMD_4
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r2g2_1/smatrix22  [1.3.7]
	} field;
} REG_ICAMD_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C54
typedef union _REG_ICAMD_5
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r2g3_1/smatrix23  [1.3.7]
	} field;
} REG_ICAMD_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C58
typedef union _REG_ICAMD_6
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r3g1_1/smatrix31  [1.3.7]
	} field;
} REG_ICAMD_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C5C
typedef union _REG_ICAMD_7
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r3g2_1/smatrix32  [1.3.7]
	} field;
} REG_ICAMD_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C60
typedef union _REG_ICAMD_8
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r3g3_1/smatrix33  [1.3.7]
	} field;
} REG_ICAMD_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C64
typedef union _REG_ICAMD_9
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, k1_1/sk1 [1.10.0]
	} field;
} REG_ICAMD_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C68
typedef union _REG_ICAMD_10
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, k2_1/sk2 [1.10.0]
	} field;
} REG_ICAMD_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C6C
typedef union _REG_ICAMD_11
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, k3_1/sk3 [1.10.0]
	} field;
} REG_ICAMD_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C70
typedef union _REG_ICAMD_12
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r1g1_0 /matrix11 [1.3.7]
	} field;
} REG_ICAMD_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C74
typedef union _REG_ICAMD_13
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r1g2_0 /matrix12 [1.3.7]
	} field;
} REG_ICAMD_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C78
typedef union _REG_ICAMD_14
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, r1g3_0 /matrix13 [1.3.7]
	} field;
} REG_ICAMD_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C7C
typedef union _REG_ICAMD_15
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter,  r2g1_0 /matrix21 [1.3.7]
	} field;
} REG_ICAMD_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C80
typedef union _REG_ICAMD_16
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter,  r2g2_0 /matrix22 [1.3.7]
	} field;
} REG_ICAMD_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C84
typedef union _REG_ICAMD_17
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter,  r2g3_0 /matrix23 [1.3.7]
	} field;
} REG_ICAMD_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C88
typedef union _REG_ICAMD_18
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter,  r3g1_0 /matrix31 [1.3.7]
	} field;
} REG_ICAMD_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C8C
typedef union _REG_ICAMD_19
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter,  r3g2_0 /matrix32 [1.3.7]
	} field;
} REG_ICAMD_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C90
typedef union _REG_ICAMD_20
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter,  r3g3_0 /matrix33 [1.3.7]
	} field;
} REG_ICAMD_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C94
typedef union _REG_ICAMD_21
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, k1_0/k1 [1.10.0]
	} field;
} REG_ICAMD_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C98
typedef union _REG_ICAMD_22
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, k2_0/k2 [1.10.0]
	} field;
} REG_ICAMD_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 
// Offset: 0x0C9C
typedef union _REG_ICAMD_23
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, k3_0/k3 [1.10.0]
	} field;
} REG_ICAMD_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 24, dth
// Offset: 0x0CA0
typedef union _REG_ICAMD_24
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, mdth [1.10.0]
	} field;
} REG_ICAMD_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color correction matrix Register 25, th1
// Offset: 0x0CA4
typedef union _REG_ICAMD_25
{
	UINT32 value;
	struct
	{
		UINT32 ccm_m_dat            : 11; // [10:0] Color correction matrix parameter, mth1 [0.10.0]
	} field;
} REG_ICAMD_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram Start Location Register
// Offset: 0x0CC8
typedef union _REG_YHIST_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 yh_hstart            : 13; // [12:0] 
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yh_vstart            : 13; // [28:16] 
	} field;
} REG_YHIST_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram Size Register
// Offset: 0x0CCC
typedef union _REG_YHIST_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 yh_width             : 13; // [12:0] 
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yh_height            : 13; // [28:16] 
	} field;
} REG_YHIST_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram Decimation Register
// Offset: 0x0CD0
typedef union _REG_YHIST_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 yh_dec_etw           : 3 ; // [2:0] 
		UINT32 rsvd3                : 13; // [15:3] 
		UINT32 yh_dec_eth           : 3 ; // [18:16] 
	} field;
} REG_YHIST_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram mux select register
// Offset: 0x0CD4
typedef union _REG_YHIST_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 32; // [31:0] 
	} field;
} REG_YHIST_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y histogram dumping base address 
// Offset: 0x0CD8
typedef union _REG_YHIST_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 7 ; // [6:0] 
		UINT32 base_adr             : 25; // [31:7] Y histogram dumping base address(8x16byte align), need use Yhistogram frame_start generate interrupt & sync address
	} field;
} REG_YHIST_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 0
// Offset: 0x0D00
typedef union _REG_YHIST_ACC_0
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D04
typedef union _REG_YHIST_ACC_1
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D08
typedef union _REG_YHIST_ACC_2
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D0C
typedef union _REG_YHIST_ACC_3
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D10
typedef union _REG_YHIST_ACC_4
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D14
typedef union _REG_YHIST_ACC_5
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D18
typedef union _REG_YHIST_ACC_6
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D1C
typedef union _REG_YHIST_ACC_7
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D20
typedef union _REG_YHIST_ACC_8
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D24
typedef union _REG_YHIST_ACC_9
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D28
typedef union _REG_YHIST_ACC_10
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D2C
typedef union _REG_YHIST_ACC_11
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D30
typedef union _REG_YHIST_ACC_12
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D34
typedef union _REG_YHIST_ACC_13
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D38
typedef union _REG_YHIST_ACC_14
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D3C
typedef union _REG_YHIST_ACC_15
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D40
typedef union _REG_YHIST_ACC_16
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D44
typedef union _REG_YHIST_ACC_17
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D48
typedef union _REG_YHIST_ACC_18
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D4C
typedef union _REG_YHIST_ACC_19
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D50
typedef union _REG_YHIST_ACC_20
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D54
typedef union _REG_YHIST_ACC_21
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D58
typedef union _REG_YHIST_ACC_22
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D5C
typedef union _REG_YHIST_ACC_23
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D60
typedef union _REG_YHIST_ACC_24
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D64
typedef union _REG_YHIST_ACC_25
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D68
typedef union _REG_YHIST_ACC_26
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_26;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D6C
typedef union _REG_YHIST_ACC_27
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_27;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D70
typedef union _REG_YHIST_ACC_28
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_28;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D74
typedef union _REG_YHIST_ACC_29
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_29;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D78
typedef union _REG_YHIST_ACC_30
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_30;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D7C
typedef union _REG_YHIST_ACC_31
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_31;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D80
typedef union _REG_YHIST_ACC_32
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_32;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D84
typedef union _REG_YHIST_ACC_33
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_33;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D88
typedef union _REG_YHIST_ACC_34
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_34;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D8C
typedef union _REG_YHIST_ACC_35
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_35;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D90
typedef union _REG_YHIST_ACC_36
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_36;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D94
typedef union _REG_YHIST_ACC_37
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_37;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D98
typedef union _REG_YHIST_ACC_38
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_38;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0D9C
typedef union _REG_YHIST_ACC_39
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_39;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DA0
typedef union _REG_YHIST_ACC_40
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_40;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DA4
typedef union _REG_YHIST_ACC_41
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_41;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DA8
typedef union _REG_YHIST_ACC_42
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_42;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DAC
typedef union _REG_YHIST_ACC_43
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_43;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DB0
typedef union _REG_YHIST_ACC_44
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_44;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DB4
typedef union _REG_YHIST_ACC_45
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_45;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DB8
typedef union _REG_YHIST_ACC_46
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_46;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DBC
typedef union _REG_YHIST_ACC_47
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_47;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DC0
typedef union _REG_YHIST_ACC_48
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_48;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DC4
typedef union _REG_YHIST_ACC_49
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_49;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DC8
typedef union _REG_YHIST_ACC_50
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_50;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DCC
typedef union _REG_YHIST_ACC_51
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_51;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DD0
typedef union _REG_YHIST_ACC_52
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_52;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DD4
typedef union _REG_YHIST_ACC_53
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_53;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DD8
typedef union _REG_YHIST_ACC_54
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_54;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DDC
typedef union _REG_YHIST_ACC_55
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_55;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DE0
typedef union _REG_YHIST_ACC_56
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_56;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DE4
typedef union _REG_YHIST_ACC_57
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_57;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DE8
typedef union _REG_YHIST_ACC_58
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_58;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DEC
typedef union _REG_YHIST_ACC_59
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_59;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DF0
typedef union _REG_YHIST_ACC_60
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_60;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DF4
typedef union _REG_YHIST_ACC_61
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_61;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DF8
typedef union _REG_YHIST_ACC_62
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_62;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Histogram result register 
// Offset: 0x0DFC
typedef union _REG_YHIST_ACC_63
{
	UINT32 value;
	struct
	{
		UINT32 acc                  : 18; // [17:0] Y histogram return data
	} field;
} REG_YHIST_ACC_63;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 0
// Offset: 0x0E00
typedef union _REG_IGRVAL_0
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.[1.4.11]
	} field;
} REG_IGRVAL_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 1
// Offset: 0x0E04
typedef union _REG_IGRVAL_1
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.[1.4.11]
	} field;
} REG_IGRVAL_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 2
// Offset: 0x0E08
typedef union _REG_IGRVAL_2
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.[1.4.11]
	} field;
} REG_IGRVAL_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 3
// Offset: 0x0E0C
typedef union _REG_IGRVAL_3
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 4
// Offset: 0x0E10
typedef union _REG_IGRVAL_4
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 5
// Offset: 0x0E14
typedef union _REG_IGRVAL_5
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 6
// Offset: 0x0E18
typedef union _REG_IGRVAL_6
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 7
// Offset: 0x0E1C
typedef union _REG_IGRVAL_7
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 8
// Offset: 0x0E20
typedef union _REG_IGRVAL_8
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 9
// Offset: 0x0E24
typedef union _REG_IGRVAL_9
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 10
// Offset: 0x0E28
typedef union _REG_IGRVAL_10
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 11
// Offset: 0x0E2C
typedef union _REG_IGRVAL_11
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 12
// Offset: 0x0E30
typedef union _REG_IGRVAL_12
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 13
// Offset: 0x0E34
typedef union _REG_IGRVAL_13
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB Gamma table Register 14
// Offset: 0x0E38
typedef union _REG_IGRVAL_14
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 10; // [9:0] RGB gamma value.
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 sgval                : 16; // [31:16] RGB gamma slope value.
	} field;
} REG_IGRVAL_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E40
typedef union _REG_ICCONV_0
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E44
typedef union _REG_ICCONV_1
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E48
typedef union _REG_ICCONV_2
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E4C
typedef union _REG_ICCONV_3
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E50
typedef union _REG_ICCONV_4
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E54
typedef union _REG_ICCONV_5
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E58
typedef union _REG_ICCONV_6
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E5C
typedef union _REG_ICCONV_7
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RGB to YUV color space conversion Register
// Offset: 0x0E60
typedef union _REG_ICCONV_8
{
	UINT32 value;
	struct
	{
		UINT32 csc_m                : 9 ; // [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
	} field;
} REG_ICCONV_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 0
// Offset: 0x0E80
typedef union _REG_ISHRP1_0
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight, Format: 0.4.0.
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level, Format: 0.10.0.
	} field;
} REG_ISHRP1_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 1
// Offset: 0x0E84
typedef union _REG_ISHRP1_1
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level
	} field;
} REG_ISHRP1_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 2
// Offset: 0x0E88
typedef union _REG_ISHRP1_2
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level
	} field;
} REG_ISHRP1_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 3
// Offset: 0x0E8C
typedef union _REG_ISHRP1_3
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level
	} field;
} REG_ISHRP1_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 4
// Offset: 0x0E90
typedef union _REG_ISHRP1_4
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level
	} field;
} REG_ISHRP1_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 5
// Offset: 0x0E94
typedef union _REG_ISHRP1_5
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level
	} field;
} REG_ISHRP1_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 6
// Offset: 0x0E98
typedef union _REG_ISHRP1_6
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level
	} field;
} REG_ISHRP1_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 7
// Offset: 0x0E9C
typedef union _REG_ISHRP1_7
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 diff                 : 10; // [25:16] Edge amplification delta level
	} field;
} REG_ISHRP1_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 8
// Offset: 0x0EA0
typedef union _REG_ISHRP1_8
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 lpff                 : 11; // [26:16] LPFF, [0.3.8]
	} field;
} REG_ISHRP1_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 9
// Offset: 0x0EA4
typedef union _REG_ISHRP1_9
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
	} field;
} REG_ISHRP1_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 10
// Offset: 0x0EA8
typedef union _REG_ISHRP1_10
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
	} field;
} REG_ISHRP1_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 11
// Offset: 0x0EAC
typedef union _REG_ISHRP1_11
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
	} field;
} REG_ISHRP1_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 12
// Offset: 0x0EB0
typedef union _REG_ISHRP1_12
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
	} field;
} REG_ISHRP1_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 13
// Offset: 0x0EB4
typedef union _REG_ISHRP1_13
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
	} field;
} REG_ISHRP1_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight and Difference 14
// Offset: 0x0EB8
typedef union _REG_ISHRP1_14
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 w                    : 4 ; // [11:8] Sharpening filter weight
	} field;
} REG_ISHRP1_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Factor and Slope 0
// Offset: 0x0EBC
typedef union _REG_ISHRP2_0
{
	UINT32 value;
	struct
	{
		UINT32 s                    : 21; // [20:0] Amplification factor slope
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 f                    : 7 ; // [30:24] Amplification factor
	} field;
} REG_ISHRP2_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Factor and Slope 1
// Offset: 0x0EC0
typedef union _REG_ISHRP2_1
{
	UINT32 value;
	struct
	{
		UINT32 s                    : 21; // [20:0] Amplification factor slope
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 f                    : 7 ; // [30:24] Amplification factor
	} field;
} REG_ISHRP2_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Factor and Slope 2
// Offset: 0x0EC4
typedef union _REG_ISHRP2_2
{
	UINT32 value;
	struct
	{
		UINT32 s                    : 21; // [20:0] Amplification factor slope
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 f                    : 7 ; // [30:24] Amplification factor
	} field;
} REG_ISHRP2_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Factor and Slope 3
// Offset: 0x0EC8
typedef union _REG_ISHRP2_3
{
	UINT32 value;
	struct
	{
		UINT32 s                    : 21; // [20:0] Amplification factor slope
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 f                    : 7 ; // [30:24] Amplification factor
	} field;
} REG_ISHRP2_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Factor and Slope 4
// Offset: 0x0ECC
typedef union _REG_ISHRP2_4
{
	UINT32 value;
	struct
	{
		UINT32 s                    : 21; // [20:0] Amplification factor slope
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 f                    : 7 ; // [30:24] Amplification factor
	} field;
} REG_ISHRP2_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Factor and Slope 5
// Offset: 0x0ED0
typedef union _REG_ISHRP2_5
{
	UINT32 value;
	struct
	{
		UINT32 s                    : 21; // [20:0] Amplification factor slope
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 f                    : 7 ; // [30:24] Amplification factor
	} field;
} REG_ISHRP2_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Amplification Weight Normalization
// Offset: 0x0ED4
typedef union _REG_ISHRP3
{
	UINT32 value;
	struct
	{
		UINT32 wsum                 : 22; // [21:0] Amplification filter weight normalization factor
		UINT32 rsvd22               : 2 ; // [23:22] 
		UINT32 ndirf                : 4 ; // [27:24] Negative Factor Multiplier
		UINT32 pdirf                : 4 ; // [31:28] Positive Factor Multiplier
	} field;
} REG_ISHRP3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// UV smoothing Register 1
// Offset: 0x0ED8
typedef union _REG_IUVS1
{
	UINT32 value;
	struct
	{
		UINT32 uvdiff1              : 10; // [9:0] UV smoothing factor delta 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvdiff2              : 10; // [25:16] UV smoothing factor delta 2
	} field;
} REG_IUVS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// UV smoothing Register 2
// Offset: 0x0EDC
typedef union _REG_IUVS2
{
	UINT32 value;
	struct
	{
		UINT32 uvslope              : 18; // [17:0] UV smoothing factor slope
		UINT32 rsvd18               : 6 ; // [23:18] 
		UINT32 uvf                  : 8 ; // [31:24] UV smoothing factor level
	} field;
} REG_IUVS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// UV Color Kill Register 1
// Offset: 0x0EE0
typedef union _REG_IUVCKS1
{
	UINT32 value;
	struct
	{
		UINT32 uvckdiff1            : 10; // [9:0] UV Color kill factor delta 1
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvckdiff2            : 10; // [25:16] UV Color kill factor delta 2
	} field;
} REG_IUVCKS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// UV Color Kill Register 2
// Offset: 0x0EE4
typedef union _REG_IUVCKS2
{
	UINT32 value;
	struct
	{
		UINT32 uvckslope            : 18; // [17:0] UV Color kill factor slope
	} field;
} REG_IUVCKS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Edge Threshold
// Offset: 0x0EE8
typedef union _REG_ISHRPET
{
	UINT32 value;
	struct
	{
		UINT32 en                   : 1 ; // [0] Edge Threshold enable
		UINT32 rsvd1                : 7 ; // [7:1] 
		UINT32 th                   : 16; // [23:8] Threshold (for edge smooth)
	} field;
} REG_ISHRPET;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 0
// Offset: 0x0F00
typedef union _REG_YCURVE_0
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parammeters value. Format: 0.10.0
	} field;
} REG_YCURVE_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F04
typedef union _REG_YCURVE_1
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F08
typedef union _REG_YCURVE_2
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F0C
typedef union _REG_YCURVE_3
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F10
typedef union _REG_YCURVE_4
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F14
typedef union _REG_YCURVE_5
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F18
typedef union _REG_YCURVE_6
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F1C
typedef union _REG_YCURVE_7
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F20
typedef union _REG_YCURVE_8
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F24
typedef union _REG_YCURVE_9
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F28
typedef union _REG_YCURVE_10
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F2C
typedef union _REG_YCURVE_11
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F30
typedef union _REG_YCURVE_12
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F34
typedef union _REG_YCURVE_13
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F38
typedef union _REG_YCURVE_14
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F3C
typedef union _REG_YCURVE_15
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F40
typedef union _REG_YCURVE_16
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F44
typedef union _REG_YCURVE_17
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F48
typedef union _REG_YCURVE_18
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F4C
typedef union _REG_YCURVE_19
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F50
typedef union _REG_YCURVE_20
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F54
typedef union _REG_YCURVE_21
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F58
typedef union _REG_YCURVE_22
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F5C
typedef union _REG_YCURVE_23
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F60
typedef union _REG_YCURVE_24
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F64
typedef union _REG_YCURVE_25
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F68
typedef union _REG_YCURVE_26
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_26;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F6C
typedef union _REG_YCURVE_27
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_27;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F70
typedef union _REG_YCURVE_28
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_28;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F74
typedef union _REG_YCURVE_29
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_29;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F78
typedef union _REG_YCURVE_30
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_30;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F7C
typedef union _REG_YCURVE_31
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_31;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F80
typedef union _REG_YCURVE_32
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_32;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F84
typedef union _REG_YCURVE_33
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_33;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F88
typedef union _REG_YCURVE_34
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_34;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F8C
typedef union _REG_YCURVE_35
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_35;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F90
typedef union _REG_YCURVE_36
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_36;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F94
typedef union _REG_YCURVE_37
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_37;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F98
typedef union _REG_YCURVE_38
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_38;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0F9C
typedef union _REG_YCURVE_39
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_39;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FA0
typedef union _REG_YCURVE_40
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_40;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FA4
typedef union _REG_YCURVE_41
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_41;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FA8
typedef union _REG_YCURVE_42
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_42;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FAC
typedef union _REG_YCURVE_43
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_43;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FB0
typedef union _REG_YCURVE_44
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_44;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FB4
typedef union _REG_YCURVE_45
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_45;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FB8
typedef union _REG_YCURVE_46
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_46;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FBC
typedef union _REG_YCURVE_47
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_47;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FC0
typedef union _REG_YCURVE_48
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_48;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FC4
typedef union _REG_YCURVE_49
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_49;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FC8
typedef union _REG_YCURVE_50
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_50;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FCC
typedef union _REG_YCURVE_51
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_51;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FD0
typedef union _REG_YCURVE_52
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_52;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FD4
typedef union _REG_YCURVE_53
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_53;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FD8
typedef union _REG_YCURVE_54
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_54;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FDC
typedef union _REG_YCURVE_55
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_55;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FE0
typedef union _REG_YCURVE_56
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_56;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FE4
typedef union _REG_YCURVE_57
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_57;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FE8
typedef union _REG_YCURVE_58
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_58;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FEC
typedef union _REG_YCURVE_59
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_59;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FF0
typedef union _REG_YCURVE_60
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_60;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FF4
typedef union _REG_YCURVE_61
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_61;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Y Curve PARAM table Register 
// Offset: 0x0FF8
typedef union _REG_YCURVE_62
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_62;

////////////////////////////////////////////////////////////////////////////////////////////////////
// PARAM table Register 63
// Offset: 0x0FFC
typedef union _REG_YCURVE_63
{
	UINT32 value;
	struct
	{
		UINT32 l_param              : 10; // [9:0] Y curve L parameters value. Format: 0.10.0
	} field;
} REG_YCURVE_63;

#if 0
////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 0
// Offset: 0x1020
typedef union _REG_NL3DGSIGMAX0
{
	UINT32 value;
	struct
	{
		UINT32 gsx0                 : 10; // [9:0] G Sigma X0(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx1                 : 10; // [25:16] G Sigma X1(0.10.0)
	} field;
} REG_NL3DGSIGMAX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 1
// Offset: 0x1024
typedef union _REG_NL3DGSIGMAX1
{
	UINT32 value;
	struct
	{
		UINT32 gsx2                 : 10; // [9:0] G Sigma X2(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx3                 : 10; // [25:16] G Sigma X3(0.10.0)
	} field;
} REG_NL3DGSIGMAX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 2
// Offset: 0x1028
typedef union _REG_NL3DGSIGMAX2
{
	UINT32 value;
	struct
	{
		UINT32 gsx4                 : 10; // [9:0] G Sigma X4(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx5                 : 10; // [25:16] G Sigma X5(0.10.0)
	} field;
} REG_NL3DGSIGMAX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 3
// Offset: 0x102C
typedef union _REG_NL3DGSIGMAX3
{
	UINT32 value;
	struct
	{
		UINT32 gsx6                 : 10; // [9:0] G Sigma X6(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx7                 : 10; // [25:16] G Sigma X7(0.10.0)
	} field;
} REG_NL3DGSIGMAX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 4
// Offset: 0x1030
typedef union _REG_NL3DGSIGMAX4
{
	UINT32 value;
	struct
	{
		UINT32 gsx8                 : 10; // [9:0] G Sigma X8(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx9                 : 10; // [25:16] G Sigma X9(0.10.0)
	} field;
} REG_NL3DGSIGMAX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 5
// Offset: 0x1034
typedef union _REG_NL3DGSIGMAX5
{
	UINT32 value;
	struct
	{
		UINT32 gsx10                : 10; // [9:0] G Sigma X10(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx11                : 10; // [25:16] G Sigma X11(0.10.0)
	} field;
} REG_NL3DGSIGMAX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 6
// Offset: 0x1038
typedef union _REG_NL3DGSIGMAX6
{
	UINT32 value;
	struct
	{
		UINT32 gsx12                : 10; // [9:0] G Sigma X12(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx13                : 10; // [25:16] G Sigma X13(0.10.0)
	} field;
} REG_NL3DGSIGMAX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA X Register 7
// Offset: 0x103C
typedef union _REG_NL3DGSIGMAX7
{
	UINT32 value;
	struct
	{
		UINT32 gsx14                : 10; // [9:0] G Sigma X14(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx15                : 10; // [25:16] G Sigma X15(0.10.0)
	} field;
} REG_NL3DGSIGMAX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 0
// Offset: 0x10A0
typedef union _REG_NL3DGSIGMAY0
{
	UINT32 value;
	struct
	{
		UINT32 gsy0                 : 14; // [13:0] G Sigma Y0(0.14.0)
	} field;
} REG_NL3DGSIGMAY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 1
// Offset: 0x10A4
typedef union _REG_NL3DGSIGMAY1
{
	UINT32 value;
	struct
	{
		UINT32 gsy1                 : 14; // [13:0] G Sigma Y1(0.14.0)
	} field;
} REG_NL3DGSIGMAY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 2
// Offset: 0x10A8
typedef union _REG_NL3DGSIGMAY2
{
	UINT32 value;
	struct
	{
		UINT32 gsy2                 : 14; // [13:0] G Sigma Y2(0.14.0)
	} field;
} REG_NL3DGSIGMAY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 3
// Offset: 0x10AC
typedef union _REG_NL3DGSIGMAY3
{
	UINT32 value;
	struct
	{
		UINT32 gsy3                 : 14; // [13:0] G Sigma Y3(0.14.0)
	} field;
} REG_NL3DGSIGMAY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 4
// Offset: 0x10B0
typedef union _REG_NL3DGSIGMAY4
{
	UINT32 value;
	struct
	{
		UINT32 gsy4                 : 14; // [13:0] G Sigma Y4(0.14.0)
	} field;
} REG_NL3DGSIGMAY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 5
// Offset: 0x10B4
typedef union _REG_NL3DGSIGMAY5
{
	UINT32 value;
	struct
	{
		UINT32 gsy5                 : 14; // [13:0] G Sigma Y5(0.14.0)
	} field;
} REG_NL3DGSIGMAY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 6
// Offset: 0x10B8
typedef union _REG_NL3DGSIGMAY6
{
	UINT32 value;
	struct
	{
		UINT32 gsy6                 : 14; // [13:0] G Sigma Y6(0.14.0)
	} field;
} REG_NL3DGSIGMAY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 7
// Offset: 0x10BC
typedef union _REG_NL3DGSIGMAY7
{
	UINT32 value;
	struct
	{
		UINT32 gsy7                 : 14; // [13:0] G Sigma Y7(0.14.0)
	} field;
} REG_NL3DGSIGMAY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 8
// Offset: 0x10C0
typedef union _REG_NL3DGSIGMAY8
{
	UINT32 value;
	struct
	{
		UINT32 gsy8                 : 14; // [13:0] G Sigma Y8(0.14.0)
	} field;
} REG_NL3DGSIGMAY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 9
// Offset: 0x10C4
typedef union _REG_NL3DGSIGMAY9
{
	UINT32 value;
	struct
	{
		UINT32 gsy9                 : 14; // [13:0] G Sigma Y9(0.14.0)
	} field;
} REG_NL3DGSIGMAY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 10
// Offset: 0x10C8
typedef union _REG_NL3DGSIGMAY10
{
	UINT32 value;
	struct
	{
		UINT32 gsy10                : 14; // [13:0] G Sigma Y10(0.14.0)
	} field;
} REG_NL3DGSIGMAY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 11
// Offset: 0x10CC
typedef union _REG_NL3DGSIGMAY11
{
	UINT32 value;
	struct
	{
		UINT32 gsy11                : 14; // [13:0] G Sigma Y11(0.14.0)
	} field;
} REG_NL3DGSIGMAY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 12
// Offset: 0x10D0
typedef union _REG_NL3DGSIGMAY12
{
	UINT32 value;
	struct
	{
		UINT32 gsy12                : 14; // [13:0] G Sigma Y12(0.14.0)
	} field;
} REG_NL3DGSIGMAY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 13
// Offset: 0x10D4
typedef union _REG_NL3DGSIGMAY13
{
	UINT32 value;
	struct
	{
		UINT32 gsy13                : 14; // [13:0] G Sigma Y13(0.14.0)
	} field;
} REG_NL3DGSIGMAY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 14
// Offset: 0x10D8
typedef union _REG_NL3DGSIGMAY14
{
	UINT32 value;
	struct
	{
		UINT32 gsy14                : 14; // [13:0] G Sigma Y14(0.14.0)
	} field;
} REG_NL3DGSIGMAY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA Y Register 15
// Offset: 0x10DC
typedef union _REG_NL3DGSIGMAY15
{
	UINT32 value;
	struct
	{
		UINT32 gsy15                : 14; // [13:0] G Sigma Y15(0.14.0)
	} field;
} REG_NL3DGSIGMAY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 0
// Offset: 0x1140
typedef union _REG_NL3DGSIGMAS0
{
	UINT32 value;
	struct
	{
		UINT32 gss0                 : 16; // [15:0] G Sigma S0(1.8.7)
		UINT32 gss1                 : 16; // [31:16] G Sigma S1(1.8.7)
	} field;
} REG_NL3DGSIGMAS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 1
// Offset: 0x1144
typedef union _REG_NL3DGSIGMAS1
{
	UINT32 value;
	struct
	{
		UINT32 gss2                 : 16; // [15:0] G Sigma S2(1.8.7)
		UINT32 gss3                 : 16; // [31:16] G Sigma S3(1.8.7)
	} field;
} REG_NL3DGSIGMAS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 2
// Offset: 0x1148
typedef union _REG_NL3DGSIGMAS2
{
	UINT32 value;
	struct
	{
		UINT32 gss4                 : 16; // [15:0] G Sigma S4(1.8.7)
		UINT32 gss5                 : 16; // [31:16] G Sigma S5(1.8.7)
	} field;
} REG_NL3DGSIGMAS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 3
// Offset: 0x114C
typedef union _REG_NL3DGSIGMAS3
{
	UINT32 value;
	struct
	{
		UINT32 gss6                 : 16; // [15:0] G Sigma S6(1.8.7)
		UINT32 gss7                 : 16; // [31:16] G Sigma S7(1.8.7)
	} field;
} REG_NL3DGSIGMAS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 4
// Offset: 0x1150
typedef union _REG_NL3DGSIGMAS4
{
	UINT32 value;
	struct
	{
		UINT32 gss8                 : 16; // [15:0] G Sigma S8(1.8.7)
		UINT32 gss9                 : 16; // [31:16] G Sigma S9(1.8.7)
	} field;
} REG_NL3DGSIGMAS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 5
// Offset: 0x1154
typedef union _REG_NL3DGSIGMAS5
{
	UINT32 value;
	struct
	{
		UINT32 gss10                : 16; // [15:0] G Sigma S10(1.8.7)
		UINT32 gss11                : 16; // [31:16] G Sigma S11(1.8.7)
	} field;
} REG_NL3DGSIGMAS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 6
// Offset: 0x1158
typedef union _REG_NL3DGSIGMAS6
{
	UINT32 value;
	struct
	{
		UINT32 gss12                : 16; // [15:0] G Sigma S12(1.8.7)
		UINT32 gss13                : 16; // [31:16] G Sigma S13(1.8.7)
	} field;
} REG_NL3DGSIGMAS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G SIGMA S Register 7
// Offset: 0x115C
typedef union _REG_NL3DGSIGMAS7
{
	UINT32 value;
	struct
	{
		UINT32 gss14                : 16; // [15:0] G Sigma S14(1.8.7)
		UINT32 gss15                : 16; // [31:16] G Sigma S15(1.8.7)
	} field;
} REG_NL3DGSIGMAS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 0
// Offset: 0x11A0
typedef union _REG_NL3DGFILTPARX0
{
	UINT32 value;
	struct
	{
		UINT32 gfx0                 : 10; // [9:0] G Filtpar X0(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx1                 : 10; // [25:16] G Filtpar X1(0.10.0)
	} field;
} REG_NL3DGFILTPARX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 1
// Offset: 0x11A4
typedef union _REG_NL3DGFILTPARX1
{
	UINT32 value;
	struct
	{
		UINT32 gfx2                 : 10; // [9:0] G Filtpar X2(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx3                 : 10; // [25:16] G Filtpar X3(0.10.0)
	} field;
} REG_NL3DGFILTPARX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 2
// Offset: 0x11A8
typedef union _REG_NL3DGFILTPARX2
{
	UINT32 value;
	struct
	{
		UINT32 gfx4                 : 10; // [9:0] G Filtpar X4(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx5                 : 10; // [25:16] G Filtpar X5(0.10.0)
	} field;
} REG_NL3DGFILTPARX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 3
// Offset: 0x11AC
typedef union _REG_NL3DGFILTPARX3
{
	UINT32 value;
	struct
	{
		UINT32 gfx6                 : 10; // [9:0] G Filtpar X6(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx7                 : 10; // [25:16] G Filtpar X7(0.10.0)
	} field;
} REG_NL3DGFILTPARX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 4
// Offset: 0x11B0
typedef union _REG_NL3DGFILTPARX4
{
	UINT32 value;
	struct
	{
		UINT32 gfx8                 : 10; // [9:0] G Filtpar X8(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx9                 : 10; // [25:16] G Filtpar X9(0.10.0)
	} field;
} REG_NL3DGFILTPARX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 5
// Offset: 0x11B4
typedef union _REG_NL3DGFILTPARX5
{
	UINT32 value;
	struct
	{
		UINT32 gfx10                : 10; // [9:0] G Filtpar X10(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx11                : 10; // [25:16] G Filtpar X11(0.10.0)
	} field;
} REG_NL3DGFILTPARX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 6
// Offset: 0x11B8
typedef union _REG_NL3DGFILTPARX6
{
	UINT32 value;
	struct
	{
		UINT32 gfx12                : 10; // [9:0] G Filtpar X12(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx13                : 10; // [25:16] G Filtpar X13(0.10.0)
	} field;
} REG_NL3DGFILTPARX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR X Register 7
// Offset: 0x11BC
typedef union _REG_NL3DGFILTPARX7
{
	UINT32 value;
	struct
	{
		UINT32 gfx14                : 10; // [9:0] G Filtpar X14(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx15                : 10; // [25:16] G Filtpar X15(0.10.0)
	} field;
} REG_NL3DGFILTPARX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 0
// Offset: 0x1220
typedef union _REG_NL3DGFILTPARY0
{
	UINT32 value;
	struct
	{
		UINT32 gfy0                 : 22; // [21:0] G Filtpar Y0(0.6.16)
	} field;
} REG_NL3DGFILTPARY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 1
// Offset: 0x1224
typedef union _REG_NL3DGFILTPARY1
{
	UINT32 value;
	struct
	{
		UINT32 gfy1                 : 22; // [21:0] G Filtpar Y1(0.6.16)
	} field;
} REG_NL3DGFILTPARY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 2
// Offset: 0x1228
typedef union _REG_NL3DGFILTPARY2
{
	UINT32 value;
	struct
	{
		UINT32 gfy2                 : 22; // [21:0] G Filtpar Y2(0.6.16)
	} field;
} REG_NL3DGFILTPARY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 3
// Offset: 0x122C
typedef union _REG_NL3DGFILTPARY3
{
	UINT32 value;
	struct
	{
		UINT32 gfy3                 : 22; // [21:0] G Filtpar Y3(0.6.16)
	} field;
} REG_NL3DGFILTPARY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 4
// Offset: 0x1230
typedef union _REG_NL3DGFILTPARY4
{
	UINT32 value;
	struct
	{
		UINT32 gfy4                 : 22; // [21:0] G Filtpar Y4(0.6.16)
	} field;
} REG_NL3DGFILTPARY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 5
// Offset: 0x1234
typedef union _REG_NL3DGFILTPARY5
{
	UINT32 value;
	struct
	{
		UINT32 gfy5                 : 22; // [21:0] G Filtpar Y5(0.6.16)
	} field;
} REG_NL3DGFILTPARY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 6
// Offset: 0x1238
typedef union _REG_NL3DGFILTPARY6
{
	UINT32 value;
	struct
	{
		UINT32 gfy6                 : 22; // [21:0] G Filtpar Y6(0.6.16)
	} field;
} REG_NL3DGFILTPARY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 7
// Offset: 0x123C
typedef union _REG_NL3DGFILTPARY7
{
	UINT32 value;
	struct
	{
		UINT32 gfy7                 : 22; // [21:0] G Filtpar Y7(0.6.16)
	} field;
} REG_NL3DGFILTPARY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 8
// Offset: 0x1240
typedef union _REG_NL3DGFILTPARY8
{
	UINT32 value;
	struct
	{
		UINT32 gfy8                 : 22; // [21:0] G Filtpar Y8(0.6.16)
	} field;
} REG_NL3DGFILTPARY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 9
// Offset: 0x1244
typedef union _REG_NL3DGFILTPARY9
{
	UINT32 value;
	struct
	{
		UINT32 gfy9                 : 22; // [21:0] G Filtpar Y9(0.6.16)
	} field;
} REG_NL3DGFILTPARY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 10
// Offset: 0x1248
typedef union _REG_NL3DGFILTPARY10
{
	UINT32 value;
	struct
	{
		UINT32 gfy10                : 22; // [21:0] G Filtpar Y10(0.6.16)
	} field;
} REG_NL3DGFILTPARY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 11
// Offset: 0x124C
typedef union _REG_NL3DGFILTPARY11
{
	UINT32 value;
	struct
	{
		UINT32 gfy11                : 22; // [21:0] G Filtpar Y11(0.6.16)
	} field;
} REG_NL3DGFILTPARY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 12
// Offset: 0x1250
typedef union _REG_NL3DGFILTPARY12
{
	UINT32 value;
	struct
	{
		UINT32 gfy12                : 22; // [21:0] G Filtpar Y12(0.6.16)
	} field;
} REG_NL3DGFILTPARY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 13
// Offset: 0x1254
typedef union _REG_NL3DGFILTPARY13
{
	UINT32 value;
	struct
	{
		UINT32 gfy13                : 22; // [21:0] G Filtpar Y13(0.6.16)
	} field;
} REG_NL3DGFILTPARY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 14
// Offset: 0x1258
typedef union _REG_NL3DGFILTPARY14
{
	UINT32 value;
	struct
	{
		UINT32 gfy14                : 22; // [21:0] G Filtpar Y14(0.6.16)
	} field;
} REG_NL3DGFILTPARY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR Y Register 15
// Offset: 0x125C
typedef union _REG_NL3DGFILTPARY15
{
	UINT32 value;
	struct
	{
		UINT32 gfy15                : 22; // [21:0] G Filtpar Y15(0.6.16)
	} field;
} REG_NL3DGFILTPARY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 0
// Offset: 0x12C0
typedef union _REG_NL3DGFILTPARS0
{
	UINT32 value;
	struct
	{
		UINT32 gfs0                 : 16; // [15:0] G Filtpar S0(1.9.6)
		UINT32 gfs1                 : 16; // [31:16] G Filtpar S1(1.9.6)
	} field;
} REG_NL3DGFILTPARS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 1
// Offset: 0x12C4
typedef union _REG_NL3DGFILTPARS1
{
	UINT32 value;
	struct
	{
		UINT32 gfs2                 : 16; // [15:0] G Filtpar S2(1.9.6)
		UINT32 gfs3                 : 16; // [31:16] G Filtpar S3(1.9.6)
	} field;
} REG_NL3DGFILTPARS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 2
// Offset: 0x12C8
typedef union _REG_NL3DGFILTPARS2
{
	UINT32 value;
	struct
	{
		UINT32 gfs4                 : 16; // [15:0] G Filtpar S4(1.9.6)
		UINT32 gfs5                 : 16; // [31:16] G Filtpar S5(1.9.6)
	} field;
} REG_NL3DGFILTPARS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 3
// Offset: 0x12CC
typedef union _REG_NL3DGFILTPARS3
{
	UINT32 value;
	struct
	{
		UINT32 gfs6                 : 16; // [15:0] G Filtpar S6(1.9.6)
		UINT32 gfs7                 : 16; // [31:16] G Filtpar S7(1.9.6)
	} field;
} REG_NL3DGFILTPARS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 4
// Offset: 0x12D0
typedef union _REG_NL3DGFILTPARS4
{
	UINT32 value;
	struct
	{
		UINT32 gfs8                 : 16; // [15:0] G Filtpar S8(1.9.6)
		UINT32 gfs9                 : 16; // [31:16] G Filtpar S9(1.9.6)
	} field;
} REG_NL3DGFILTPARS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 5
// Offset: 0x12D4
typedef union _REG_NL3DGFILTPARS5
{
	UINT32 value;
	struct
	{
		UINT32 gfs10                : 16; // [15:0] G Filtpar S10(1.9.6)
		UINT32 gfs11                : 16; // [31:16] G Filtpar S11(1.9.6)
	} field;
} REG_NL3DGFILTPARS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 6
// Offset: 0x12D8
typedef union _REG_NL3DGFILTPARS6
{
	UINT32 value;
	struct
	{
		UINT32 gfs12                : 16; // [15:0] G Filtpar S12(1.9.6)
		UINT32 gfs13                : 16; // [31:16] G Filtpar S13(1.9.6)
	} field;
} REG_NL3DGFILTPARS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D G FILTPAR S Register 7
// Offset: 0x12DC
typedef union _REG_NL3DGFILTPARS7
{
	UINT32 value;
	struct
	{
		UINT32 gfs14                : 16; // [15:0] G Filtpar S14(1.9.6)
		UINT32 gfs15                : 16; // [31:16] G Filtpar S15(1.9.6)
	} field;
} REG_NL3DGFILTPARS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL 3D CFG Register
// Offset: 0x1300
typedef union _REG_NL3DCFG
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 2 ; // [1:0] TL - Top Left(read only)
		UINT32 rsvd2                : 2 ; // [3:2] TR - Top Right(read only)
		UINT32 rsvd4                : 2 ; // [5:4] BL - Bottom Left(read only)
		UINT32 rsvd6                : 2 ; // [7:6] BR - Bottom Right(read only)
		UINT32 rsvd8                : 9 ; // [16:8] 
		UINT32 shift                : 3 ; // [19:17] shift (sigma/filtpar scale parameter), bit[2] high indicate left shift for filtpar and right shift for sigma
		UINT32 rsvd20               : 3 ; // [22:20] SHOTNOR - Reject shot noise number for R channel
		UINT32 rsvd23               : 1 ; // [23] 
		UINT32 shotnog              : 3 ; // [26:24] Reject shot noise number for G channel
		UINT32 rsvd27               : 1 ; // [27] 
		UINT32 rsvd28               : 3 ; // [30:28] SHOTNOB - Reject shot noise number for B channel
	} field;
} REG_NL3DCFG;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Input Image Y Plane Start Address Register
// Offset: 0x1304
typedef union _REG_DNRIAY
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] 
		UINT32 sad                  : 29; // [31:3] decompress start address, 128byte align
	} field;
} REG_DNRIAY;

////////////////////////////////////////////////////////////////////////////////////////////////////
// FBDC axi read address status register
// Offset: 0x1308
typedef union _REG_DNRFBDCAR
{
	UINT32 value;
	struct
	{
		UINT32 rsvd                 : 4 ; // [3:0] 
		UINT32 araddr               : 28; // [31:4] axi read address bit[31:4], read only
	} field;
} REG_DNRFBDCAR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Input Image Stride Register, no use
// Offset: 0x130C
typedef union _REG_DNRIS
{
	UINT32 value;
	struct
	{
		UINT32 rsvd                 : 32; // [31:0] 
	} field;
} REG_DNRIS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Output Image Y Plane Start Address Register
// Offset: 0x1310
typedef union _REG_DNROAY
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] 
		UINT32 sad                  : 29; // [31:3] compress start address, 128byte align
	} field;
} REG_DNROAY;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Buffer Compression Control Register 2
// Offset: 0x1314
typedef union _REG_DNRCC2
{
	UINT32 value;
	struct
	{
		UINT32 qt1                  : 16; // [15:0] Quantization parameter
		UINT32 qt2                  : 16; // [31:16] Quantization parameter
	} field;
} REG_DNRCC2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Buffer Compression Control Register 3
// Offset: 0x1318
typedef union _REG_DNRCC3
{
	UINT32 value;
	struct
	{
		UINT32 qt3                  : 16; // [15:0] Quantization parameter
		UINT32 rsvd16               : 16; // [31:16] 
	} field;
} REG_DNRCC3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Input Buffer Size Register, byte unit
// Offset: 0x131C
typedef union _REG_DNRISZ
{
	UINT32 value;
	struct
	{
		UINT32 sz                   : 32; // [31:0] Reference frame buffer size in bytes., no use
	} field;
} REG_DNRISZ;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Output Buffer Size Register, byte unit
// Offset: 0x1320
typedef union _REG_DNROSZ
{
	UINT32 value;
	struct
	{
		UINT32 sz                   : 32; // [31:0] Reference frame buffer size in bytes.
	} field;
} REG_DNROSZ;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Buffer Compression Control Register
// Offset: 0x1324
typedef union _REG_DNRCC
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 2 ; // [1:0] 
		UINT32 ct                   : 2 ; // [3:2] Color transform.
		UINT32 sw                   : 3 ; // [6:4] Sample width.
	} field;
} REG_DNRCC;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Buffer Compression Control Register 1
// Offset: 0x1328
typedef union _REG_DNRCC1
{
	UINT32 value;
	struct
	{
		UINT32 fbe                  : 1 ; // [0] Frame Buffer Compression Enable
		UINT32 tb                   : 1 ; // [1] Frame Buffer Decompression Enable
		UINT32 axie                 : 1 ; // [2] enable read/write data with axi bus. (RSVD, set zero)
		UINT32 format               : 1 ; // [3] It is valid when FBE=0 and TB=0. This bit selects data format in DDR. 0:packed without gap  1: per pixel used 16bits
		UINT32 onecmp               : 1 ; // [4] only enable compression model when FBE=1and TB=1. (RSVD, set zero)
		UINT32 cdconce              : 1 ; // [5] Only once compressed or decompressed. (RSVD, set zero)
		UINT32 fbdcsm               : 1 ; // [6] Control Frame Buffer Decompression to start read data .  1:used register FBCLN to control   0: used input frame end signal
		UINT32 rsvd7                : 1 ; // [7] 
		UINT32 rbstm                : 2 ; // [9:8] fbdc read axi outstanding mode, 0 : 4*1*8*64, 1: 2*2*8*64, 2: 1*4*8*64
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 fbcln                : 13; // [28:16] Frame Buffer Compression had compressed image lines number.
		UINT32 rsvd29               : 2 ; // [30:29] 
		UINT32 trg                  : 1 ; // [31] trigger nl3d control FSM to work(this bit must be configured after nl3d_enable, FBE, TB or AXIE). 1: start work 0: back idle
	} field;
} REG_DNRCC1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Buffer Compression Status Register
// Offset: 0x132C
typedef union _REG_DNRCS
{
	UINT32 value;
	struct
	{
		UINT32 fbcb                 : 1 ; // [0] Frame Buffer Decompression busy.
		UINT32 fbdcb                : 1 ; // [1] Frame Buffer Decompression busy.
		UINT32 rsvd2                : 2 ; // [3:2] 
		UINT32 ctrls                : 2 ; // [5:4] FSM(controlnl3d+compress) value.
	} field;
} REG_DNRCS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DN Reference Buffer Compression had used the max buffer length.
// Offset: 0x1330
typedef union _REG_DNRCL
{
	UINT32 value;
	struct
	{
		UINT32 fbcbl                : 25; // [24:0] Frame Buffer Decompression buffer length value.
	} field;
} REG_DNRCL;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter weight table regsiter
// Offset: 0x1334
typedef union _REG_NL3D_W2D1R
{
	UINT32 value;
	struct
	{
		UINT32 w2d1_0               : 4 ; // [3:0] 1st 2D filter weight [0.4.0]
		UINT32 w2d1_1               : 4 ; // [7:4] 1st 2D filter weight [0.4.0]
		UINT32 w2d1_2               : 4 ; // [11:8] 1st 2D filter weight [0.4.0]
		UINT32 w2d1_3               : 4 ; // [15:12] 1st 2D filter weight [0.4.0]
	} field;
} REG_NL3D_W2D1R;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter difference table regsiter for R
// Offset: 0x1338
typedef union _REG_NL3D_D2D1R0
{
	UINT32 value;
	struct
	{
		UINT32 d2d1_0               : 12; // [11:0] 1st 2D filter difference weight [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 d2d1_1               : 12; // [27:16] 1st 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D1R0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter difference table regsiter for R
// Offset: 0x133C
typedef union _REG_NL3D_D2D1R1
{
	UINT32 value;
	struct
	{
		UINT32 d2d1_2               : 12; // [11:0] 1st 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D1R1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter difference table regsiter for G
// Offset: 0x1340
typedef union _REG_NL3D_D2D1G0
{
	UINT32 value;
	struct
	{
		UINT32 d2d1_0               : 12; // [11:0] 1st 2D filter difference weight [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 d2d1_1               : 12; // [27:16] 1st 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D1G0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter difference table regsiter for G
// Offset: 0x1344
typedef union _REG_NL3D_D2D1G1
{
	UINT32 value;
	struct
	{
		UINT32 d2d1_2               : 12; // [11:0] 1st 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D1G1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter difference table regsiter for B
// Offset: 0x1348
typedef union _REG_NL3D_D2D1B0
{
	UINT32 value;
	struct
	{
		UINT32 d2d1_0               : 12; // [11:0] 1st 2D filter difference weight [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 d2d1_1               : 12; // [27:16] 1st 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D1B0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter difference table regsiter for B
// Offset: 0x134C
typedef union _REG_NL3D_D2D1B1
{
	UINT32 value;
	struct
	{
		UINT32 d2d1_2               : 12; // [11:0] 1st 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D1B1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter spatial weight table regsiter
// Offset: 0x1350
typedef union _REG_NL3D_S2D1R0
{
	UINT32 value;
	struct
	{
		UINT32 s2d1_0               : 4 ; // [3:0] 1st 2D filter spatial weight [0.4.0]
		UINT32 s2d1_1               : 4 ; // [7:4] 1st 2D filter spatial weight [0.4.0]
		UINT32 s2d1_2               : 4 ; // [11:8] 1st 2D filter spatial weight [0.4.0]
		UINT32 s2d1_3               : 4 ; // [15:12] 1st 2D filter spatial weight [0.4.0]
	} field;
} REG_NL3D_S2D1R0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 1st 2D filter spatial weight table regsiter
// Offset: 0x1354
typedef union _REG_NL3D_S2D1R1
{
	UINT32 value;
	struct
	{
		UINT32 s2d1_4               : 4 ; // [3:0] 1st 2D filter spatial weight [0.4.0]
		UINT32 s2d1_5               : 4 ; // [7:4] 1st 2D filter spatial weight [0.4.0]
		UINT32 s2d1_6               : 4 ; // [11:8] 1st 2D filter spatial weight [0.4.0]
		UINT32 s2d1_7               : 4 ; // [15:12] 1st 2D filter spatial weight [0.4.0]
		UINT32 s2d1_8               : 4 ; // [19:16] 1st 2D filter spatial weight [0.4.0]
	} field;
} REG_NL3D_S2D1R1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 2nd 2D filter weight table regsiter
// Offset: 0x1358
typedef union _REG_NL3D_W2D2R
{
	UINT32 value;
	struct
	{
		UINT32 w2d2_0               : 4 ; // [3:0] 2nd 2D filter weight [0.4.0]
		UINT32 w2d2_1               : 4 ; // [7:4] 2nd 2D filter weight [0.4.0]
		UINT32 w2d2_2               : 4 ; // [11:8] 2nd 2D filter weight [0.4.0]
		UINT32 w2d2_3               : 4 ; // [15:12] 2nd 2D filter weight [0.4.0]
	} field;
} REG_NL3D_W2D2R;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 2nd 2D filter difference table regsiter
// Offset: 0x135C
typedef union _REG_NL3D_D2D2R0
{
	UINT32 value;
	struct
	{
		UINT32 d2d2_0               : 12; // [11:0] 2nd 2D filter difference weight [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 d2d2_1               : 12; // [27:16] 2nd 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D2R0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 2nd 2D filter difference table regsiter
// Offset: 0x1360
typedef union _REG_NL3D_D2D2R1
{
	UINT32 value;
	struct
	{
		UINT32 d2d2_2               : 12; // [11:0] 2nd 2D filter difference weight [0.12.0]
	} field;
} REG_NL3D_D2D2R1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 2nd 2D filter spatial weight table regsiter
// Offset: 0x1364
typedef union _REG_NL3D_S2D2R0
{
	UINT32 value;
	struct
	{
		UINT32 s2d2_0               : 4 ; // [3:0] 2nd 2D filter spatial weight [0.4.0]
		UINT32 s2d2_1               : 4 ; // [7:4] 2nd 2D filter spatial weight [0.4.0]
		UINT32 s2d2_2               : 4 ; // [11:8] 2nd 2D filter spatial weight [0.4.0]
		UINT32 s2d2_3               : 4 ; // [15:12] 2nd 2D filter spatial weight [0.4.0]
	} field;
} REG_NL3D_S2D2R0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D 2nd 2D filter spatial weight table regsiter
// Offset: 0x1368
typedef union _REG_NL3D_S2D2R1
{
	UINT32 value;
	struct
	{
		UINT32 s2d2_4               : 4 ; // [3:0] 2nd 2D filter spatial weight [0.4.0]
		UINT32 s2d2_5               : 4 ; // [7:4] 2nd 2D filter spatial weight [0.4.0]
		UINT32 s2d2_6               : 4 ; // [11:8] 2nd 2D filter spatial weight [0.4.0]
		UINT32 s2d2_7               : 4 ; // [15:12] 2nd 2D filter spatial weight [0.4.0]
		UINT32 s2d2_8               : 4 ; // [19:16] 2nd 2D filter spatial weight [0.4.0]
	} field;
} REG_NL3D_S2D2R1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D refw curve x register
// Offset: 0x136C
typedef union _REG_NL3D_REFWCX0
{
	UINT32 value;
	struct
	{
		UINT32 refwcx_0             : 9 ; // [8:0] refw curve x [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 refwcx_1             : 9 ; // [24:16] refw curve x [0.9.0]
	} field;
} REG_NL3D_REFWCX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  refw curve x register
// Offset: 0x1370
typedef union _REG_NL3D_REFWCX1
{
	UINT32 value;
	struct
	{
		UINT32 refwcx_2             : 9 ; // [8:0] refw curve x [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 refwcx_3             : 9 ; // [24:16] refw curve x [0.9.0]
	} field;
} REG_NL3D_REFWCX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  refw curve y register
// Offset: 0x1374
typedef union _REG_NL3D_REFWCY0
{
	UINT32 value;
	struct
	{
		UINT32 refwcy_0             : 9 ; // [8:0] refw curve y [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 refwcy_1             : 9 ; // [24:16] refw curve y [0.9.0]
	} field;
} REG_NL3D_REFWCY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  refw curve y register
// Offset: 0x1378
typedef union _REG_NL3D_REFWCY1
{
	UINT32 value;
	struct
	{
		UINT32 refwcy_2             : 9 ; // [8:0] refw curve y [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 refwcy_3             : 9 ; // [24:16] refw curve y [0.9.0]
	} field;
} REG_NL3D_REFWCY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D movw curve x register
// Offset: 0x137C
typedef union _REG_NL3D_MOVWCX0
{
	UINT32 value;
	struct
	{
		UINT32 movwcx_0             : 9 ; // [8:0] movw curve x [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 movwcx_1             : 9 ; // [24:16] movw curve x [0.9.0]
	} field;
} REG_NL3D_MOVWCX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  movw curve x register
// Offset: 0x1380
typedef union _REG_NL3D_MOVWCX1
{
	UINT32 value;
	struct
	{
		UINT32 movwcx_2             : 9 ; // [8:0] movw curve x [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 movwcx_3             : 9 ; // [24:16] movw curve x [0.9.0]
	} field;
} REG_NL3D_MOVWCX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  movw curve y register
// Offset: 0x1384
typedef union _REG_NL3D_MOVWCY0
{
	UINT32 value;
	struct
	{
		UINT32 movwcy_0             : 9 ; // [8:0] movw curve y [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 movwcy_1             : 9 ; // [24:16] movw curve y [0.9.0]
	} field;
} REG_NL3D_MOVWCY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  movw curve y register
// Offset: 0x1388
typedef union _REG_NL3D_MOVWCY1
{
	UINT32 value;
	struct
	{
		UINT32 movwcy_2             : 9 ; // [8:0] movw curve y [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 movwcy_3             : 9 ; // [24:16] movw curve y [0.9.0]
	} field;
} REG_NL3D_MOVWCY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D snt curve x register
// Offset: 0x138C
typedef union _REG_NL3D_SNTCX0
{
	UINT32 value;
	struct
	{
		UINT32 sntcx_0              : 9 ; // [8:0] snt curve x [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 sntcx_1              : 9 ; // [24:16] snt curve x [0.9.0]
	} field;
} REG_NL3D_SNTCX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  snt curve x register
// Offset: 0x1390
typedef union _REG_NL3D_SNTCX1
{
	UINT32 value;
	struct
	{
		UINT32 sntcx_2              : 9 ; // [8:0] snt curve x [0.9.0]
		UINT32 rsvd9                : 7 ; // [15:9] 
		UINT32 sntcx_3              : 9 ; // [24:16] snt curve x [0.9.0]
	} field;
} REG_NL3D_SNTCX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  snt curve y register
// Offset: 0x1394
typedef union _REG_NL3D_SNTCY0
{
	UINT32 value;
	struct
	{
		UINT32 sntcy_0              : 12; // [11:0] snt curve y [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 sntcy_1              : 12; // [27:16] snt curve y [0.12.0]
	} field;
} REG_NL3D_SNTCY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D  snt curve y register
// Offset: 0x1398
typedef union _REG_NL3D_SNTCY1
{
	UINT32 value;
	struct
	{
		UINT32 sntcy_2              : 12; // [11:0] snt curve y [0.12.0]
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 sntcy_3              : 12; // [27:16] snt curve y [0.12.0]
	} field;
} REG_NL3D_SNTCY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 0
// Offset: 0x2000
typedef union _REG_NL2DRSIGMAX0
{
	UINT32 value;
	struct
	{
		UINT32 rsx0                 : 10; // [9:0] R Sigma X0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx1                 : 10; // [25:16] R Sigma X1(0.10.0)
	} field;
} REG_NL2DRSIGMAX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 1
// Offset: 0x2004
typedef union _REG_NL2DRSIGMAX1
{
	UINT32 value;
	struct
	{
		UINT32 rsx2                 : 10; // [9:0] R Sigma X2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx3                 : 10; // [25:16] R Sigma X3(0.10.0)
	} field;
} REG_NL2DRSIGMAX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 2
// Offset: 0x2008
typedef union _REG_NL2DRSIGMAX2
{
	UINT32 value;
	struct
	{
		UINT32 rsx4                 : 10; // [9:0] R Sigma X4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx5                 : 10; // [25:16] R Sigma X5(0.10.0)
	} field;
} REG_NL2DRSIGMAX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 3
// Offset: 0x200C
typedef union _REG_NL2DRSIGMAX3
{
	UINT32 value;
	struct
	{
		UINT32 rsx6                 : 10; // [9:0] R Sigma X6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx7                 : 10; // [25:16] R Sigma X7(0.10.0)
	} field;
} REG_NL2DRSIGMAX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 4
// Offset: 0x2010
typedef union _REG_NL2DRSIGMAX4
{
	UINT32 value;
	struct
	{
		UINT32 rsx8                 : 10; // [9:0] R Sigma X8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx9                 : 10; // [25:16] R Sigma X9(0.10.0)
	} field;
} REG_NL2DRSIGMAX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 5
// Offset: 0x2014
typedef union _REG_NL2DRSIGMAX5
{
	UINT32 value;
	struct
	{
		UINT32 rsx10                : 10; // [9:0] R Sigma X10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx11                : 10; // [25:16] R Sigma X11(0.10.0)
	} field;
} REG_NL2DRSIGMAX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 6
// Offset: 0x2018
typedef union _REG_NL2DRSIGMAX6
{
	UINT32 value;
	struct
	{
		UINT32 rsx12                : 10; // [9:0] R Sigma X12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx13                : 10; // [25:16] R Sigma X13(0.10.0)
	} field;
} REG_NL2DRSIGMAX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA X Register 7
// Offset: 0x201C
typedef union _REG_NL2DRSIGMAX7
{
	UINT32 value;
	struct
	{
		UINT32 rsx14                : 10; // [9:0] R Sigma X14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rsx15                : 10; // [25:16] R Sigma X15(0.10.0)
	} field;
} REG_NL2DRSIGMAX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 0
// Offset: 0x2020
typedef union _REG_NL2DGSIGMAX0
{
	UINT32 value;
	struct
	{
		UINT32 gsx0                 : 10; // [9:0] G Sigma X0(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx1                 : 10; // [25:16] G Sigma X1(0.10.0)
	} field;
} REG_NL2DGSIGMAX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 1
// Offset: 0x2024
typedef union _REG_NL2DGSIGMAX1
{
	UINT32 value;
	struct
	{
		UINT32 gsx2                 : 10; // [9:0] G Sigma X2(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx3                 : 10; // [25:16] G Sigma X3(0.10.0)
	} field;
} REG_NL2DGSIGMAX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 2
// Offset: 0x2028
typedef union _REG_NL2DGSIGMAX2
{
	UINT32 value;
	struct
	{
		UINT32 gsx4                 : 10; // [9:0] G Sigma X4(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx5                 : 10; // [25:16] G Sigma X5(0.10.0)
	} field;
} REG_NL2DGSIGMAX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 3
// Offset: 0x202C
typedef union _REG_NL2DGSIGMAX3
{
	UINT32 value;
	struct
	{
		UINT32 gsx6                 : 10; // [9:0] G Sigma X6(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx7                 : 10; // [25:16] G Sigma X7(0.10.0)
	} field;
} REG_NL2DGSIGMAX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 4
// Offset: 0x2030
typedef union _REG_NL2DGSIGMAX4
{
	UINT32 value;
	struct
	{
		UINT32 gsx8                 : 10; // [9:0] G Sigma X8(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx9                 : 10; // [25:16] G Sigma X9(0.10.0)
	} field;
} REG_NL2DGSIGMAX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 5
// Offset: 0x2034
typedef union _REG_NL2DGSIGMAX5
{
	UINT32 value;
	struct
	{
		UINT32 gsx10                : 10; // [9:0] G Sigma X10(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx11                : 10; // [25:16] G Sigma X11(0.10.0)
	} field;
} REG_NL2DGSIGMAX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 6
// Offset: 0x2038
typedef union _REG_NL2DGSIGMAX6
{
	UINT32 value;
	struct
	{
		UINT32 gsx12                : 10; // [9:0] G Sigma X12(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx13                : 10; // [25:16] G Sigma X13(0.10.0)
	} field;
} REG_NL2DGSIGMAX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA X Register 7
// Offset: 0x203C
typedef union _REG_NL2DGSIGMAX7
{
	UINT32 value;
	struct
	{
		UINT32 gsx14                : 10; // [9:0] G Sigma X14(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gsx15                : 10; // [25:16] G Sigma X15(0.10.0)
	} field;
} REG_NL2DGSIGMAX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 0
// Offset: 0x2040
typedef union _REG_NL2DBSIGMAX0
{
	UINT32 value;
	struct
	{
		UINT32 bsx0                 : 10; // [9:0] B Sigma X0(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx1                 : 10; // [25:16] B Sigma X1(0.10.0)
	} field;
} REG_NL2DBSIGMAX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 1
// Offset: 0x2044
typedef union _REG_NL2DBSIGMAX1
{
	UINT32 value;
	struct
	{
		UINT32 bsx2                 : 10; // [9:0] B Sigma X2(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx3                 : 10; // [25:16] B Sigma X3(0.10.0)
	} field;
} REG_NL2DBSIGMAX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 2
// Offset: 0x2048
typedef union _REG_NL2DBSIGMAX2
{
	UINT32 value;
	struct
	{
		UINT32 bsx4                 : 10; // [9:0] B Sigma X4(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx5                 : 10; // [25:16] B Sigma X5(0.10.0)
	} field;
} REG_NL2DBSIGMAX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 3
// Offset: 0x204C
typedef union _REG_NL2DBSIGMAX3
{
	UINT32 value;
	struct
	{
		UINT32 bsx6                 : 10; // [9:0] B Sigma X6(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx7                 : 10; // [25:16] B Sigma X7(0.10.0)
	} field;
} REG_NL2DBSIGMAX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 4
// Offset: 0x2050
typedef union _REG_NL2DBSIGMAX4
{
	UINT32 value;
	struct
	{
		UINT32 bsx8                 : 10; // [9:0] B Sigma X8(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx9                 : 10; // [25:16] B Sigma X9(0.10.0)
	} field;
} REG_NL2DBSIGMAX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 5
// Offset: 0x2054
typedef union _REG_NL2DBSIGMAX5
{
	UINT32 value;
	struct
	{
		UINT32 bsx10                : 10; // [9:0] B Sigma X10(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx11                : 10; // [25:16] B Sigma X11(0.10.0)
	} field;
} REG_NL2DBSIGMAX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 6
// Offset: 0x2058
typedef union _REG_NL2DBSIGMAX6
{
	UINT32 value;
	struct
	{
		UINT32 bsx12                : 10; // [9:0] B Sigma X12(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx13                : 10; // [25:16] B Sigma X13(0.10.0)
	} field;
} REG_NL2DBSIGMAX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA X Register 7
// Offset: 0x205C
typedef union _REG_NL2DBSIGMAX7
{
	UINT32 value;
	struct
	{
		UINT32 bsx14                : 10; // [9:0] B Sigma X14(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bsx15                : 10; // [25:16] B Sigma X15(0.10.0)
	} field;
} REG_NL2DBSIGMAX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 0
// Offset: 0x2060
typedef union _REG_NL2DRSIGMAY0
{
	UINT32 value;
	struct
	{
		UINT32 rsy0                 : 14; // [13:0] R Sigma Y0(0.14.0)
	} field;
} REG_NL2DRSIGMAY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 1
// Offset: 0x2064
typedef union _REG_NL2DRSIGMAY1
{
	UINT32 value;
	struct
	{
		UINT32 rsy1                 : 14; // [13:0] R Sigma Y1(0.14.0)
	} field;
} REG_NL2DRSIGMAY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 2
// Offset: 0x2068
typedef union _REG_NL2DRSIGMAY2
{
	UINT32 value;
	struct
	{
		UINT32 rsy2                 : 14; // [13:0] R Sigma Y2(0.14.0)
	} field;
} REG_NL2DRSIGMAY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 3
// Offset: 0x206C
typedef union _REG_NL2DRSIGMAY3
{
	UINT32 value;
	struct
	{
		UINT32 rsy3                 : 14; // [13:0] R Sigma Y3(0.14.0)
	} field;
} REG_NL2DRSIGMAY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 4
// Offset: 0x2070
typedef union _REG_NL2DRSIGMAY4
{
	UINT32 value;
	struct
	{
		UINT32 rsy4                 : 14; // [13:0] R Sigma Y4(0.14.0)
	} field;
} REG_NL2DRSIGMAY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 5
// Offset: 0x2074
typedef union _REG_NL2DRSIGMAY5
{
	UINT32 value;
	struct
	{
		UINT32 rsy5                 : 14; // [13:0] R Sigma Y5(0.14.0)
	} field;
} REG_NL2DRSIGMAY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 6
// Offset: 0x2078
typedef union _REG_NL2DRSIGMAY6
{
	UINT32 value;
	struct
	{
		UINT32 rsy6                 : 14; // [13:0] R Sigma Y6(0.14.0)
	} field;
} REG_NL2DRSIGMAY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 7
// Offset: 0x207C
typedef union _REG_NL2DRSIGMAY7
{
	UINT32 value;
	struct
	{
		UINT32 rsy7                 : 14; // [13:0] R Sigma Y7(0.14.0)
	} field;
} REG_NL2DRSIGMAY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 8
// Offset: 0x2080
typedef union _REG_NL2DRSIGMAY8
{
	UINT32 value;
	struct
	{
		UINT32 rsy8                 : 14; // [13:0] R Sigma Y8(0.14.0)
	} field;
} REG_NL2DRSIGMAY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 9
// Offset: 0x2084
typedef union _REG_NL2DRSIGMAY9
{
	UINT32 value;
	struct
	{
		UINT32 rsy9                 : 14; // [13:0] R Sigma Y9(0.14.0)
	} field;
} REG_NL2DRSIGMAY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 10
// Offset: 0x2088
typedef union _REG_NL2DRSIGMAY10
{
	UINT32 value;
	struct
	{
		UINT32 rsy10                : 14; // [13:0] R Sigma Y10(0.14.0)
	} field;
} REG_NL2DRSIGMAY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 11
// Offset: 0x208C
typedef union _REG_NL2DRSIGMAY11
{
	UINT32 value;
	struct
	{
		UINT32 rsy11                : 14; // [13:0] R Sigma Y11(0.14.0)
	} field;
} REG_NL2DRSIGMAY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 12
// Offset: 0x2090
typedef union _REG_NL2DRSIGMAY12
{
	UINT32 value;
	struct
	{
		UINT32 rsy12                : 14; // [13:0] R Sigma Y12(0.14.0)
	} field;
} REG_NL2DRSIGMAY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 13
// Offset: 0x2094
typedef union _REG_NL2DRSIGMAY13
{
	UINT32 value;
	struct
	{
		UINT32 rsy13                : 14; // [13:0] R Sigma Y13(0.14.0)
	} field;
} REG_NL2DRSIGMAY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 14
// Offset: 0x2098
typedef union _REG_NL2DRSIGMAY14
{
	UINT32 value;
	struct
	{
		UINT32 rsy14                : 14; // [13:0] R Sigma Y14(0.14.0)
	} field;
} REG_NL2DRSIGMAY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA Y Register 15
// Offset: 0x209C
typedef union _REG_NL2DRSIGMAY15
{
	UINT32 value;
	struct
	{
		UINT32 rsy15                : 14; // [13:0] R Sigma Y15(0.14.0)
	} field;
} REG_NL2DRSIGMAY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 0
// Offset: 0x20A0
typedef union _REG_NL2DGSIGMAY0
{
	UINT32 value;
	struct
	{
		UINT32 gsy0                 : 14; // [13:0] G Sigma Y0(0.14.0)
	} field;
} REG_NL2DGSIGMAY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 1
// Offset: 0x20A4
typedef union _REG_NL2DGSIGMAY1
{
	UINT32 value;
	struct
	{
		UINT32 gsy1                 : 14; // [13:0] G Sigma Y1(0.14.0)
	} field;
} REG_NL2DGSIGMAY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 2
// Offset: 0x20A8
typedef union _REG_NL2DGSIGMAY2
{
	UINT32 value;
	struct
	{
		UINT32 gsy2                 : 14; // [13:0] G Sigma Y2(0.14.0)
	} field;
} REG_NL2DGSIGMAY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 3
// Offset: 0x20AC
typedef union _REG_NL2DGSIGMAY3
{
	UINT32 value;
	struct
	{
		UINT32 gsy3                 : 14; // [13:0] G Sigma Y3(0.14.0)
	} field;
} REG_NL2DGSIGMAY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 4
// Offset: 0x20B0
typedef union _REG_NL2DGSIGMAY4
{
	UINT32 value;
	struct
	{
		UINT32 gsy4                 : 14; // [13:0] G Sigma Y4(0.14.0)
	} field;
} REG_NL2DGSIGMAY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 5
// Offset: 0x20B4
typedef union _REG_NL2DGSIGMAY5
{
	UINT32 value;
	struct
	{
		UINT32 gsy5                 : 14; // [13:0] G Sigma Y5(0.14.0)
	} field;
} REG_NL2DGSIGMAY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 6
// Offset: 0x20B8
typedef union _REG_NL2DGSIGMAY6
{
	UINT32 value;
	struct
	{
		UINT32 gsy6                 : 14; // [13:0] G Sigma Y6(0.14.0)
	} field;
} REG_NL2DGSIGMAY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 7
// Offset: 0x20BC
typedef union _REG_NL2DGSIGMAY7
{
	UINT32 value;
	struct
	{
		UINT32 gsy7                 : 14; // [13:0] G Sigma Y7(0.14.0)
	} field;
} REG_NL2DGSIGMAY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 8
// Offset: 0x20C0
typedef union _REG_NL2DGSIGMAY8
{
	UINT32 value;
	struct
	{
		UINT32 gsy8                 : 14; // [13:0] G Sigma Y8(0.14.0)
	} field;
} REG_NL2DGSIGMAY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 9
// Offset: 0x20C4
typedef union _REG_NL2DGSIGMAY9
{
	UINT32 value;
	struct
	{
		UINT32 gsy9                 : 14; // [13:0] G Sigma Y9(0.14.0)
	} field;
} REG_NL2DGSIGMAY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 10
// Offset: 0x20C8
typedef union _REG_NL2DGSIGMAY10
{
	UINT32 value;
	struct
	{
		UINT32 gsy10                : 14; // [13:0] G Sigma Y10(0.14.0)
	} field;
} REG_NL2DGSIGMAY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 11
// Offset: 0x20CC
typedef union _REG_NL2DGSIGMAY11
{
	UINT32 value;
	struct
	{
		UINT32 gsy11                : 14; // [13:0] G Sigma Y11(0.14.0)
	} field;
} REG_NL2DGSIGMAY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 12
// Offset: 0x20D0
typedef union _REG_NL2DGSIGMAY12
{
	UINT32 value;
	struct
	{
		UINT32 gsy12                : 14; // [13:0] G Sigma Y12(0.14.0)
	} field;
} REG_NL2DGSIGMAY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 13
// Offset: 0x20D4
typedef union _REG_NL2DGSIGMAY13
{
	UINT32 value;
	struct
	{
		UINT32 gsy13                : 14; // [13:0] G Sigma Y13(0.14.0)
	} field;
} REG_NL2DGSIGMAY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 14
// Offset: 0x20D8
typedef union _REG_NL2DGSIGMAY14
{
	UINT32 value;
	struct
	{
		UINT32 gsy14                : 14; // [13:0] G Sigma Y14(0.14.0)
	} field;
} REG_NL2DGSIGMAY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA Y Register 15
// Offset: 0x20DC
typedef union _REG_NL2DGSIGMAY15
{
	UINT32 value;
	struct
	{
		UINT32 gsy15                : 14; // [13:0] G Sigma Y15(0.14.0)
	} field;
} REG_NL2DGSIGMAY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 0
// Offset: 0x20E0
typedef union _REG_NL2DBSIGMAY0
{
	UINT32 value;
	struct
	{
		UINT32 bsy0                 : 14; // [13:0] B Sigma Y0(0.14.0)
	} field;
} REG_NL2DBSIGMAY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 1
// Offset: 0x20E4
typedef union _REG_NL2DBSIGMAY1
{
	UINT32 value;
	struct
	{
		UINT32 bsy1                 : 14; // [13:0] B Sigma Y1(0.14.0)
	} field;
} REG_NL2DBSIGMAY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 2
// Offset: 0x20E8
typedef union _REG_NL2DBSIGMAY2
{
	UINT32 value;
	struct
	{
		UINT32 bsy2                 : 14; // [13:0] B Sigma Y2(0.14.0)
	} field;
} REG_NL2DBSIGMAY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 3
// Offset: 0x20EC
typedef union _REG_NL2DBSIGMAY3
{
	UINT32 value;
	struct
	{
		UINT32 bsy3                 : 14; // [13:0] B Sigma Y3(0.14.0)
	} field;
} REG_NL2DBSIGMAY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 4
// Offset: 0x20F0
typedef union _REG_NL2DBSIGMAY4
{
	UINT32 value;
	struct
	{
		UINT32 bsy4                 : 14; // [13:0] B Sigma Y4(0.14.0)
	} field;
} REG_NL2DBSIGMAY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 5
// Offset: 0x20F4
typedef union _REG_NL2DBSIGMAY5
{
	UINT32 value;
	struct
	{
		UINT32 bsy5                 : 14; // [13:0] B Sigma Y5(0.14.0)
	} field;
} REG_NL2DBSIGMAY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 6
// Offset: 0x20F8
typedef union _REG_NL2DBSIGMAY6
{
	UINT32 value;
	struct
	{
		UINT32 bsy6                 : 14; // [13:0] B Sigma Y6(0.14.0)
	} field;
} REG_NL2DBSIGMAY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 7
// Offset: 0x20FC
typedef union _REG_NL2DBSIGMAY7
{
	UINT32 value;
	struct
	{
		UINT32 bsy7                 : 14; // [13:0] B Sigma Y7(0.14.0)
	} field;
} REG_NL2DBSIGMAY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 8
// Offset: 0x2100
typedef union _REG_NL2DBSIGMAY8
{
	UINT32 value;
	struct
	{
		UINT32 bsy8                 : 14; // [13:0] B Sigma Y8(0.14.0)
	} field;
} REG_NL2DBSIGMAY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 9
// Offset: 0x2104
typedef union _REG_NL2DBSIGMAY9
{
	UINT32 value;
	struct
	{
		UINT32 bsy9                 : 14; // [13:0] B Sigma Y9(0.14.0)
	} field;
} REG_NL2DBSIGMAY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 10
// Offset: 0x2108
typedef union _REG_NL2DBSIGMAY10
{
	UINT32 value;
	struct
	{
		UINT32 bsy10                : 14; // [13:0] B Sigma Y10(0.14.0)
	} field;
} REG_NL2DBSIGMAY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 11
// Offset: 0x210C
typedef union _REG_NL2DBSIGMAY11
{
	UINT32 value;
	struct
	{
		UINT32 bsy11                : 14; // [13:0] B Sigma Y11(0.14.0)
	} field;
} REG_NL2DBSIGMAY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 12
// Offset: 0x2110
typedef union _REG_NL2DBSIGMAY12
{
	UINT32 value;
	struct
	{
		UINT32 bsy12                : 14; // [13:0] B Sigma Y12(0.14.0)
	} field;
} REG_NL2DBSIGMAY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 13
// Offset: 0x2114
typedef union _REG_NL2DBSIGMAY13
{
	UINT32 value;
	struct
	{
		UINT32 bsy13                : 14; // [13:0] B Sigma Y13(0.14.0)
	} field;
} REG_NL2DBSIGMAY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 14
// Offset: 0x2118
typedef union _REG_NL2DBSIGMAY14
{
	UINT32 value;
	struct
	{
		UINT32 bsy14                : 14; // [13:0] B Sigma Y14(0.14.0)
	} field;
} REG_NL2DBSIGMAY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA Y Register 15
// Offset: 0x211C
typedef union _REG_NL2DBSIGMAY15
{
	UINT32 value;
	struct
	{
		UINT32 bsy15                : 14; // [13:0] B Sigma Y15(0.14.0)
	} field;
} REG_NL2DBSIGMAY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 0
// Offset: 0x2120
typedef union _REG_NL2DRSIGMAS0
{
	UINT32 value;
	struct
	{
		UINT32 rss0                 : 16; // [15:0] R Sigma S0(1.8.7)
		UINT32 rss1                 : 16; // [31:16] R Sigma S1(1.8.7)
	} field;
} REG_NL2DRSIGMAS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 1
// Offset: 0x2124
typedef union _REG_NL2DRSIGMAS1
{
	UINT32 value;
	struct
	{
		UINT32 rss2                 : 16; // [15:0] R Sigma S2(1.8.7)
		UINT32 rss3                 : 16; // [31:16] R Sigma S3(1.8.7)
	} field;
} REG_NL2DRSIGMAS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 2
// Offset: 0x2128
typedef union _REG_NL2DRSIGMAS2
{
	UINT32 value;
	struct
	{
		UINT32 rss4                 : 16; // [15:0] R Sigma S4(1.8.7)
		UINT32 rss5                 : 16; // [31:16] R Sigma S5(1.8.7)
	} field;
} REG_NL2DRSIGMAS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 3
// Offset: 0x212C
typedef union _REG_NL2DRSIGMAS3
{
	UINT32 value;
	struct
	{
		UINT32 rss6                 : 16; // [15:0] R Sigma S6(1.8.7)
		UINT32 rss7                 : 16; // [31:16] R Sigma S7(1.8.7)
	} field;
} REG_NL2DRSIGMAS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 4
// Offset: 0x2130
typedef union _REG_NL2DRSIGMAS4
{
	UINT32 value;
	struct
	{
		UINT32 rss8                 : 16; // [15:0] R Sigma S8(1.8.7)
		UINT32 rss9                 : 16; // [31:16] R Sigma S9(1.8.7)
	} field;
} REG_NL2DRSIGMAS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 5
// Offset: 0x2134
typedef union _REG_NL2DRSIGMAS5
{
	UINT32 value;
	struct
	{
		UINT32 rss10                : 16; // [15:0] R Sigma S10(1.8.7)
		UINT32 rss11                : 16; // [31:16] R Sigma S11(1.8.7)
	} field;
} REG_NL2DRSIGMAS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 6
// Offset: 0x2138
typedef union _REG_NL2DRSIGMAS6
{
	UINT32 value;
	struct
	{
		UINT32 rss12                : 16; // [15:0] R Sigma S12(1.8.7)
		UINT32 rss13                : 16; // [31:16] R Sigma S13(1.8.7)
	} field;
} REG_NL2DRSIGMAS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R SIGMA S Register 7
// Offset: 0x213C
typedef union _REG_NL2DRSIGMAS7
{
	UINT32 value;
	struct
	{
		UINT32 rss14                : 16; // [15:0] R Sigma S14(1.8.7)
		UINT32 rss15                : 16; // [31:16] R Sigma S15(1.8.7)
	} field;
} REG_NL2DRSIGMAS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 0
// Offset: 0x2140
typedef union _REG_NL2DGSIGMAS0
{
	UINT32 value;
	struct
	{
		UINT32 gss0                 : 16; // [15:0] G Sigma S0(1.8.7)
		UINT32 gss1                 : 16; // [31:16] G Sigma S1(1.8.7)
	} field;
} REG_NL2DGSIGMAS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 1
// Offset: 0x2144
typedef union _REG_NL2DGSIGMAS1
{
	UINT32 value;
	struct
	{
		UINT32 gss2                 : 16; // [15:0] G Sigma S2(1.8.7)
		UINT32 gss3                 : 16; // [31:16] G Sigma S3(1.8.7)
	} field;
} REG_NL2DGSIGMAS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 2
// Offset: 0x2148
typedef union _REG_NL2DGSIGMAS2
{
	UINT32 value;
	struct
	{
		UINT32 gss4                 : 16; // [15:0] G Sigma S4(1.8.7)
		UINT32 gss5                 : 16; // [31:16] G Sigma S5(1.8.7)
	} field;
} REG_NL2DGSIGMAS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 3
// Offset: 0x214C
typedef union _REG_NL2DGSIGMAS3
{
	UINT32 value;
	struct
	{
		UINT32 gss6                 : 16; // [15:0] G Sigma S6(1.8.7)
		UINT32 gss7                 : 16; // [31:16] G Sigma S7(1.8.7)
	} field;
} REG_NL2DGSIGMAS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 4
// Offset: 0x2150
typedef union _REG_NL2DGSIGMAS4
{
	UINT32 value;
	struct
	{
		UINT32 gss8                 : 16; // [15:0] G Sigma S8(1.8.7)
		UINT32 gss9                 : 16; // [31:16] G Sigma S9(1.8.7)
	} field;
} REG_NL2DGSIGMAS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 5
// Offset: 0x2154
typedef union _REG_NL2DGSIGMAS5
{
	UINT32 value;
	struct
	{
		UINT32 gss10                : 16; // [15:0] G Sigma S10(1.8.7)
		UINT32 gss11                : 16; // [31:16] G Sigma S11(1.8.7)
	} field;
} REG_NL2DGSIGMAS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 6
// Offset: 0x2158
typedef union _REG_NL2DGSIGMAS6
{
	UINT32 value;
	struct
	{
		UINT32 gss12                : 16; // [15:0] G Sigma S12(1.8.7)
		UINT32 gss13                : 16; // [31:16] G Sigma S13(1.8.7)
	} field;
} REG_NL2DGSIGMAS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G SIGMA S Register 7
// Offset: 0x215C
typedef union _REG_NL2DGSIGMAS7
{
	UINT32 value;
	struct
	{
		UINT32 gss14                : 16; // [15:0] G Sigma S14(1.8.7)
		UINT32 gss15                : 16; // [31:16] G Sigma S15(1.8.7)
	} field;
} REG_NL2DGSIGMAS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 0
// Offset: 0x2160
typedef union _REG_NL2DBSIGMAS0
{
	UINT32 value;
	struct
	{
		UINT32 bss0                 : 16; // [15:0] B Sigma S0(1.8.7)
		UINT32 bss1                 : 16; // [31:16] B Sigma S1(1.8.7)
	} field;
} REG_NL2DBSIGMAS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 1
// Offset: 0x2164
typedef union _REG_NL2DBSIGMAS1
{
	UINT32 value;
	struct
	{
		UINT32 bss2                 : 16; // [15:0] B Sigma S2(1.8.7)
		UINT32 bss3                 : 16; // [31:16] B Sigma S3(1.8.7)
	} field;
} REG_NL2DBSIGMAS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 2
// Offset: 0x2168
typedef union _REG_NL2DBSIGMAS2
{
	UINT32 value;
	struct
	{
		UINT32 bss4                 : 16; // [15:0] B Sigma S4(1.8.7)
		UINT32 bss5                 : 16; // [31:16] B Sigma S5(1.8.7)
	} field;
} REG_NL2DBSIGMAS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 3
// Offset: 0x216C
typedef union _REG_NL2DBSIGMAS3
{
	UINT32 value;
	struct
	{
		UINT32 bss6                 : 16; // [15:0] B Sigma S6(1.8.7)
		UINT32 bss7                 : 16; // [31:16] B Sigma S7(1.8.7)
	} field;
} REG_NL2DBSIGMAS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 4
// Offset: 0x2170
typedef union _REG_NL2DBSIGMAS4
{
	UINT32 value;
	struct
	{
		UINT32 bss8                 : 16; // [15:0] B Sigma S8(1.8.7)
		UINT32 bss9                 : 16; // [31:16] B Sigma S9(1.8.7)
	} field;
} REG_NL2DBSIGMAS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 5
// Offset: 0x2174
typedef union _REG_NL2DBSIGMAS5
{
	UINT32 value;
	struct
	{
		UINT32 bss10                : 16; // [15:0] B Sigma S10(1.8.7)
		UINT32 bss11                : 16; // [31:16] B Sigma S11(1.8.7)
	} field;
} REG_NL2DBSIGMAS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 6
// Offset: 0x2178
typedef union _REG_NL2DBSIGMAS6
{
	UINT32 value;
	struct
	{
		UINT32 bss12                : 16; // [15:0] B Sigma S12(1.8.7)
		UINT32 bss13                : 16; // [31:16] B Sigma S13(1.8.7)
	} field;
} REG_NL2DBSIGMAS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B SIGMA S Register 7
// Offset: 0x217C
typedef union _REG_NL2DBSIGMAS7
{
	UINT32 value;
	struct
	{
		UINT32 bss14                : 16; // [15:0] B Sigma S14(1.8.7)
		UINT32 bss15                : 16; // [31:16] B Sigma S15(1.8.7)
	} field;
} REG_NL2DBSIGMAS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 0
// Offset: 0x2180
typedef union _REG_NL2DRFILTPARX0
{
	UINT32 value;
	struct
	{
		UINT32 rfx0                 : 10; // [9:0] R Filtpar X0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx1                 : 10; // [25:16] R Filtpar X1(0.10.0)
	} field;
} REG_NL2DRFILTPARX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 1
// Offset: 0x2184
typedef union _REG_NL2DRFILTPARX1
{
	UINT32 value;
	struct
	{
		UINT32 rfx2                 : 10; // [9:0] R Filtpar X2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx3                 : 10; // [25:16] R Filtpar X3(0.10.0)
	} field;
} REG_NL2DRFILTPARX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 2
// Offset: 0x2188
typedef union _REG_NL2DRFILTPARX2
{
	UINT32 value;
	struct
	{
		UINT32 rfx4                 : 10; // [9:0] R Filtpar X4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx5                 : 10; // [25:16] R Filtpar X5(0.10.0)
	} field;
} REG_NL2DRFILTPARX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 3
// Offset: 0x218C
typedef union _REG_NL2DRFILTPARX3
{
	UINT32 value;
	struct
	{
		UINT32 rfx6                 : 10; // [9:0] R Filtpar X6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx7                 : 10; // [25:16] R Filtpar X7(0.10.0)
	} field;
} REG_NL2DRFILTPARX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 4
// Offset: 0x2190
typedef union _REG_NL2DRFILTPARX4
{
	UINT32 value;
	struct
	{
		UINT32 rfx8                 : 10; // [9:0] R Filtpar X8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx9                 : 10; // [25:16] R Filtpar X9(0.10.0)
	} field;
} REG_NL2DRFILTPARX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 5
// Offset: 0x2194
typedef union _REG_NL2DRFILTPARX5
{
	UINT32 value;
	struct
	{
		UINT32 rfx10                : 10; // [9:0] R Filtpar X10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx11                : 10; // [25:16] R Filtpar X11(0.10.0)
	} field;
} REG_NL2DRFILTPARX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 6
// Offset: 0x2198
typedef union _REG_NL2DRFILTPARX6
{
	UINT32 value;
	struct
	{
		UINT32 rfx12                : 10; // [9:0] R Filtpar X12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx13                : 10; // [25:16] R Filtpar X13(0.10.0)
	} field;
} REG_NL2DRFILTPARX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR X Register 7
// Offset: 0x219C
typedef union _REG_NL2DRFILTPARX7
{
	UINT32 value;
	struct
	{
		UINT32 rfx14                : 10; // [9:0] R Filtpar X14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 rfx15                : 10; // [25:16] R Filtpar X15(0.10.0)
	} field;
} REG_NL2DRFILTPARX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 0
// Offset: 0x21A0
typedef union _REG_NL2DGFILTPARX0
{
	UINT32 value;
	struct
	{
		UINT32 gfx0                 : 10; // [9:0] G Filtpar X0(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx1                 : 10; // [25:16] G Filtpar X1(0.10.0)
	} field;
} REG_NL2DGFILTPARX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 1
// Offset: 0x21A4
typedef union _REG_NL2DGFILTPARX1
{
	UINT32 value;
	struct
	{
		UINT32 gfx2                 : 10; // [9:0] G Filtpar X2(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx3                 : 10; // [25:16] G Filtpar X3(0.10.0)
	} field;
} REG_NL2DGFILTPARX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 2
// Offset: 0x21A8
typedef union _REG_NL2DGFILTPARX2
{
	UINT32 value;
	struct
	{
		UINT32 gfx4                 : 10; // [9:0] G Filtpar X4(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx5                 : 10; // [25:16] G Filtpar X5(0.10.0)
	} field;
} REG_NL2DGFILTPARX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 3
// Offset: 0x21AC
typedef union _REG_NL2DGFILTPARX3
{
	UINT32 value;
	struct
	{
		UINT32 gfx6                 : 10; // [9:0] G Filtpar X6(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx7                 : 10; // [25:16] G Filtpar X7(0.10.0)
	} field;
} REG_NL2DGFILTPARX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 4
// Offset: 0x21B0
typedef union _REG_NL2DGFILTPARX4
{
	UINT32 value;
	struct
	{
		UINT32 gfx8                 : 10; // [9:0] G Filtpar X8(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx9                 : 10; // [25:16] G Filtpar X9(0.10.0)
	} field;
} REG_NL2DGFILTPARX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 5
// Offset: 0x21B4
typedef union _REG_NL2DGFILTPARX5
{
	UINT32 value;
	struct
	{
		UINT32 gfx10                : 10; // [9:0] G Filtpar X10(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx11                : 10; // [25:16] G Filtpar X11(0.10.0)
	} field;
} REG_NL2DGFILTPARX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 6
// Offset: 0x21B8
typedef union _REG_NL2DGFILTPARX6
{
	UINT32 value;
	struct
	{
		UINT32 gfx12                : 10; // [9:0] G Filtpar X12(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx13                : 10; // [25:16] G Filtpar X13(0.10.0)
	} field;
} REG_NL2DGFILTPARX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR X Register 7
// Offset: 0x21BC
typedef union _REG_NL2DGFILTPARX7
{
	UINT32 value;
	struct
	{
		UINT32 gfx14                : 10; // [9:0] G Filtpar X14(0.10.0)
		UINT32 gsvd10               : 6 ; // [15:10] 
		UINT32 gfx15                : 10; // [25:16] G Filtpar X15(0.10.0)
	} field;
} REG_NL2DGFILTPARX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 0
// Offset: 0x21C0
typedef union _REG_NL2DBFILTPARX0
{
	UINT32 value;
	struct
	{
		UINT32 bfx0                 : 10; // [9:0] B Filtpar X0(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx1                 : 10; // [25:16] B Filtpar X1(0.10.0)
	} field;
} REG_NL2DBFILTPARX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 1
// Offset: 0x21C4
typedef union _REG_NL2DBFILTPARX1
{
	UINT32 value;
	struct
	{
		UINT32 bfx2                 : 10; // [9:0] B Filtpar X2(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx3                 : 10; // [25:16] B Filtpar X3(0.10.0)
	} field;
} REG_NL2DBFILTPARX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 2
// Offset: 0x21C8
typedef union _REG_NL2DBFILTPARX2
{
	UINT32 value;
	struct
	{
		UINT32 bfx4                 : 10; // [9:0] B Filtpar X4(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx5                 : 10; // [25:16] B Filtpar X5(0.10.0)
	} field;
} REG_NL2DBFILTPARX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 3
// Offset: 0x21CC
typedef union _REG_NL2DBFILTPARX3
{
	UINT32 value;
	struct
	{
		UINT32 bfx6                 : 10; // [9:0] B Filtpar X6(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx7                 : 10; // [25:16] B Filtpar X7(0.10.0)
	} field;
} REG_NL2DBFILTPARX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 4
// Offset: 0x21D0
typedef union _REG_NL2DBFILTPARX4
{
	UINT32 value;
	struct
	{
		UINT32 bfx8                 : 10; // [9:0] B Filtpar X8(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx9                 : 10; // [25:16] B Filtpar X9(0.10.0)
	} field;
} REG_NL2DBFILTPARX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 5
// Offset: 0x21D4
typedef union _REG_NL2DBFILTPARX5
{
	UINT32 value;
	struct
	{
		UINT32 bfx10                : 10; // [9:0] B Filtpar X10(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx11                : 10; // [25:16] B Filtpar X11(0.10.0)
	} field;
} REG_NL2DBFILTPARX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 6
// Offset: 0x21D8
typedef union _REG_NL2DBFILTPARX6
{
	UINT32 value;
	struct
	{
		UINT32 bfx12                : 10; // [9:0] B Filtpar X12(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx13                : 10; // [25:16] B Filtpar X13(0.10.0)
	} field;
} REG_NL2DBFILTPARX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR X Register 7
// Offset: 0x21DC
typedef union _REG_NL2DBFILTPARX7
{
	UINT32 value;
	struct
	{
		UINT32 bfx14                : 10; // [9:0] B Filtpar X14(0.10.0)
		UINT32 bsvd10               : 6 ; // [15:10] 
		UINT32 bfx15                : 10; // [25:16] B Filtpar X15(0.10.0)
	} field;
} REG_NL2DBFILTPARX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 0
// Offset: 0x21E0
typedef union _REG_NL2DRFILTPARY0
{
	UINT32 value;
	struct
	{
		UINT32 rfy0                 : 22; // [21:0] R Filtpar Y0(0.14.8)
	} field;
} REG_NL2DRFILTPARY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 1
// Offset: 0x21E4
typedef union _REG_NL2DRFILTPARY1
{
	UINT32 value;
	struct
	{
		UINT32 rfy1                 : 22; // [21:0] R Filtpar Y1(0.14.8)
	} field;
} REG_NL2DRFILTPARY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 2
// Offset: 0x21E8
typedef union _REG_NL2DRFILTPARY2
{
	UINT32 value;
	struct
	{
		UINT32 rfy2                 : 22; // [21:0] R Filtpar Y2(0.14.8)
	} field;
} REG_NL2DRFILTPARY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 3
// Offset: 0x21EC
typedef union _REG_NL2DRFILTPARY3
{
	UINT32 value;
	struct
	{
		UINT32 rfy3                 : 22; // [21:0] R Filtpar Y3(0.14.8)
	} field;
} REG_NL2DRFILTPARY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 4
// Offset: 0x21F0
typedef union _REG_NL2DRFILTPARY4
{
	UINT32 value;
	struct
	{
		UINT32 rfy4                 : 22; // [21:0] R Filtpar Y4(0.14.8)
	} field;
} REG_NL2DRFILTPARY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 5
// Offset: 0x21F4
typedef union _REG_NL2DRFILTPARY5
{
	UINT32 value;
	struct
	{
		UINT32 rfy5                 : 22; // [21:0] R Filtpar Y5(0.14.8)
	} field;
} REG_NL2DRFILTPARY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 6
// Offset: 0x21F8
typedef union _REG_NL2DRFILTPARY6
{
	UINT32 value;
	struct
	{
		UINT32 rfy6                 : 22; // [21:0] R Filtpar Y6(0.14.8)
	} field;
} REG_NL2DRFILTPARY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 7
// Offset: 0x21FC
typedef union _REG_NL2DRFILTPARY7
{
	UINT32 value;
	struct
	{
		UINT32 rfy7                 : 22; // [21:0] R Filtpar Y7(0.14.8)
	} field;
} REG_NL2DRFILTPARY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 8
// Offset: 0x2200
typedef union _REG_NL2DRFILTPARY8
{
	UINT32 value;
	struct
	{
		UINT32 rfy8                 : 22; // [21:0] R Filtpar Y8(0.14.8)
	} field;
} REG_NL2DRFILTPARY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 9
// Offset: 0x2204
typedef union _REG_NL2DRFILTPARY9
{
	UINT32 value;
	struct
	{
		UINT32 rfy9                 : 22; // [21:0] R Filtpar Y9(0.14.8)
	} field;
} REG_NL2DRFILTPARY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 10
// Offset: 0x2208
typedef union _REG_NL2DRFILTPARY10
{
	UINT32 value;
	struct
	{
		UINT32 rfy10                : 22; // [21:0] R Filtpar Y10(0.14.8)
	} field;
} REG_NL2DRFILTPARY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 11
// Offset: 0x220C
typedef union _REG_NL2DRFILTPARY11
{
	UINT32 value;
	struct
	{
		UINT32 rfy11                : 22; // [21:0] R Filtpar Y11(0.14.8)
	} field;
} REG_NL2DRFILTPARY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 12
// Offset: 0x2210
typedef union _REG_NL2DRFILTPARY12
{
	UINT32 value;
	struct
	{
		UINT32 rfy12                : 22; // [21:0] R Filtpar Y12(0.14.8)
	} field;
} REG_NL2DRFILTPARY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 13
// Offset: 0x2214
typedef union _REG_NL2DRFILTPARY13
{
	UINT32 value;
	struct
	{
		UINT32 rfy13                : 22; // [21:0] R Filtpar Y13(0.14.8)
	} field;
} REG_NL2DRFILTPARY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 14
// Offset: 0x2218
typedef union _REG_NL2DRFILTPARY14
{
	UINT32 value;
	struct
	{
		UINT32 rfy14                : 22; // [21:0] R Filtpar Y14(0.14.8)
	} field;
} REG_NL2DRFILTPARY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR Y Register 15
// Offset: 0x221C
typedef union _REG_NL2DRFILTPARY15
{
	UINT32 value;
	struct
	{
		UINT32 rfy15                : 22; // [21:0] R Filtpar Y15(0.14.8)
	} field;
} REG_NL2DRFILTPARY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 0
// Offset: 0x2220
typedef union _REG_NL2DGFILTPARY0
{
	UINT32 value;
	struct
	{
		UINT32 gfy0                 : 22; // [21:0] G Filtpar Y0(0.14.8)
	} field;
} REG_NL2DGFILTPARY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 1
// Offset: 0x2224
typedef union _REG_NL2DGFILTPARY1
{
	UINT32 value;
	struct
	{
		UINT32 gfy1                 : 22; // [21:0] G Filtpar Y1(0.14.8)
	} field;
} REG_NL2DGFILTPARY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 2
// Offset: 0x2228
typedef union _REG_NL2DGFILTPARY2
{
	UINT32 value;
	struct
	{
		UINT32 gfy2                 : 22; // [21:0] G Filtpar Y2(0.14.8)
	} field;
} REG_NL2DGFILTPARY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 3
// Offset: 0x222C
typedef union _REG_NL2DGFILTPARY3
{
	UINT32 value;
	struct
	{
		UINT32 gfy3                 : 22; // [21:0] G Filtpar Y3(0.14.8)
	} field;
} REG_NL2DGFILTPARY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 4
// Offset: 0x2230
typedef union _REG_NL2DGFILTPARY4
{
	UINT32 value;
	struct
	{
		UINT32 gfy4                 : 22; // [21:0] G Filtpar Y4(0.14.8)
	} field;
} REG_NL2DGFILTPARY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 5
// Offset: 0x2234
typedef union _REG_NL2DGFILTPARY5
{
	UINT32 value;
	struct
	{
		UINT32 gfy5                 : 22; // [21:0] G Filtpar Y5(0.14.8)
	} field;
} REG_NL2DGFILTPARY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 6
// Offset: 0x2238
typedef union _REG_NL2DGFILTPARY6
{
	UINT32 value;
	struct
	{
		UINT32 gfy6                 : 22; // [21:0] G Filtpar Y6(0.14.8)
	} field;
} REG_NL2DGFILTPARY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 7
// Offset: 0x223C
typedef union _REG_NL2DGFILTPARY7
{
	UINT32 value;
	struct
	{
		UINT32 gfy7                 : 22; // [21:0] G Filtpar Y7(0.14.8)
	} field;
} REG_NL2DGFILTPARY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 8
// Offset: 0x2240
typedef union _REG_NL2DGFILTPARY8
{
	UINT32 value;
	struct
	{
		UINT32 gfy8                 : 22; // [21:0] G Filtpar Y8(0.14.8)
	} field;
} REG_NL2DGFILTPARY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 9
// Offset: 0x2244
typedef union _REG_NL2DGFILTPARY9
{
	UINT32 value;
	struct
	{
		UINT32 gfy9                 : 22; // [21:0] G Filtpar Y9(0.14.8)
	} field;
} REG_NL2DGFILTPARY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 10
// Offset: 0x2248
typedef union _REG_NL2DGFILTPARY10
{
	UINT32 value;
	struct
	{
		UINT32 gfy10                : 22; // [21:0] G Filtpar Y10(0.14.8)
	} field;
} REG_NL2DGFILTPARY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 11
// Offset: 0x224C
typedef union _REG_NL2DGFILTPARY11
{
	UINT32 value;
	struct
	{
		UINT32 gfy11                : 22; // [21:0] G Filtpar Y11(0.14.8)
	} field;
} REG_NL2DGFILTPARY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 12
// Offset: 0x2250
typedef union _REG_NL2DGFILTPARY12
{
	UINT32 value;
	struct
	{
		UINT32 gfy12                : 22; // [21:0] G Filtpar Y12(0.14.8)
	} field;
} REG_NL2DGFILTPARY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 13
// Offset: 0x2254
typedef union _REG_NL2DGFILTPARY13
{
	UINT32 value;
	struct
	{
		UINT32 gfy13                : 22; // [21:0] G Filtpar Y13(0.14.8)
	} field;
} REG_NL2DGFILTPARY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 14
// Offset: 0x2258
typedef union _REG_NL2DGFILTPARY14
{
	UINT32 value;
	struct
	{
		UINT32 gfy14                : 22; // [21:0] G Filtpar Y14(0.14.8)
	} field;
} REG_NL2DGFILTPARY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR Y Register 15
// Offset: 0x225C
typedef union _REG_NL2DGFILTPARY15
{
	UINT32 value;
	struct
	{
		UINT32 gfy15                : 22; // [21:0] G Filtpar Y15(0.14.8)
	} field;
} REG_NL2DGFILTPARY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 0
// Offset: 0x2260
typedef union _REG_NL2DBFILTPARY0
{
	UINT32 value;
	struct
	{
		UINT32 bfy0                 : 22; // [21:0] B Filtpar Y0(0.14.8)
	} field;
} REG_NL2DBFILTPARY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 1
// Offset: 0x2264
typedef union _REG_NL2DBFILTPARY1
{
	UINT32 value;
	struct
	{
		UINT32 bfy1                 : 22; // [21:0] B Filtpar Y1(0.14.8)
	} field;
} REG_NL2DBFILTPARY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 2
// Offset: 0x2268
typedef union _REG_NL2DBFILTPARY2
{
	UINT32 value;
	struct
	{
		UINT32 bfy2                 : 22; // [21:0] B Filtpar Y2(0.14.8)
	} field;
} REG_NL2DBFILTPARY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 3
// Offset: 0x226C
typedef union _REG_NL2DBFILTPARY3
{
	UINT32 value;
	struct
	{
		UINT32 bfy3                 : 22; // [21:0] B Filtpar Y3(0.14.8)
	} field;
} REG_NL2DBFILTPARY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 4
// Offset: 0x2270
typedef union _REG_NL2DBFILTPARY4
{
	UINT32 value;
	struct
	{
		UINT32 bfy4                 : 22; // [21:0] B Filtpar Y4(0.14.8)
	} field;
} REG_NL2DBFILTPARY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 5
// Offset: 0x2274
typedef union _REG_NL2DBFILTPARY5
{
	UINT32 value;
	struct
	{
		UINT32 bfy5                 : 22; // [21:0] B Filtpar Y5(0.14.8)
	} field;
} REG_NL2DBFILTPARY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 6
// Offset: 0x2278
typedef union _REG_NL2DBFILTPARY6
{
	UINT32 value;
	struct
	{
		UINT32 bfy6                 : 22; // [21:0] B Filtpar Y6(0.14.8)
	} field;
} REG_NL2DBFILTPARY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 7
// Offset: 0x227C
typedef union _REG_NL2DBFILTPARY7
{
	UINT32 value;
	struct
	{
		UINT32 bfy7                 : 22; // [21:0] B Filtpar Y7(0.14.8)
	} field;
} REG_NL2DBFILTPARY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 8
// Offset: 0x2280
typedef union _REG_NL2DBFILTPARY8
{
	UINT32 value;
	struct
	{
		UINT32 bfy8                 : 22; // [21:0] B Filtpar Y8(0.14.8)
	} field;
} REG_NL2DBFILTPARY8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 9
// Offset: 0x2284
typedef union _REG_NL2DBFILTPARY9
{
	UINT32 value;
	struct
	{
		UINT32 bfy9                 : 22; // [21:0] B Filtpar Y9(0.14.8)
	} field;
} REG_NL2DBFILTPARY9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 10
// Offset: 0x2288
typedef union _REG_NL2DBFILTPARY10
{
	UINT32 value;
	struct
	{
		UINT32 bfy10                : 22; // [21:0] B Filtpar Y10(0.14.8)
	} field;
} REG_NL2DBFILTPARY10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 11
// Offset: 0x228C
typedef union _REG_NL2DBFILTPARY11
{
	UINT32 value;
	struct
	{
		UINT32 bfy11                : 22; // [21:0] B Filtpar Y11(0.14.8)
	} field;
} REG_NL2DBFILTPARY11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 12
// Offset: 0x2290
typedef union _REG_NL2DBFILTPARY12
{
	UINT32 value;
	struct
	{
		UINT32 bfy12                : 22; // [21:0] B Filtpar Y12(0.14.8)
	} field;
} REG_NL2DBFILTPARY12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 13
// Offset: 0x2294
typedef union _REG_NL2DBFILTPARY13
{
	UINT32 value;
	struct
	{
		UINT32 bfy13                : 22; // [21:0] B Filtpar Y13(0.14.8)
	} field;
} REG_NL2DBFILTPARY13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 14
// Offset: 0x2298
typedef union _REG_NL2DBFILTPARY14
{
	UINT32 value;
	struct
	{
		UINT32 bfy14                : 22; // [21:0] B Filtpar Y14(0.14.8)
	} field;
} REG_NL2DBFILTPARY14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR Y Register 15
// Offset: 0x229C
typedef union _REG_NL2DBFILTPARY15
{
	UINT32 value;
	struct
	{
		UINT32 bfy15                : 22; // [21:0] B Filtpar Y15(0.14.8)
	} field;
} REG_NL2DBFILTPARY15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 0
// Offset: 0x22A0
typedef union _REG_NL2DRFILTPARS0
{
	UINT32 value;
	struct
	{
		UINT32 rfs0                 : 16; // [15:0] R Filtpar S0(1.9.6)
		UINT32 rfs1                 : 16; // [31:16] R Filtpar S1(1.9.6)
	} field;
} REG_NL2DRFILTPARS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 1
// Offset: 0x22A4
typedef union _REG_NL2DRFILTPARS1
{
	UINT32 value;
	struct
	{
		UINT32 rfs2                 : 16; // [15:0] R Filtpar S2(1.9.6)
		UINT32 rfs3                 : 16; // [31:16] R Filtpar S3(1.9.6)
	} field;
} REG_NL2DRFILTPARS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 2
// Offset: 0x22A8
typedef union _REG_NL2DRFILTPARS2
{
	UINT32 value;
	struct
	{
		UINT32 rfs4                 : 16; // [15:0] R Filtpar S4(1.9.6)
		UINT32 rfs5                 : 16; // [31:16] R Filtpar S5(1.9.6)
	} field;
} REG_NL2DRFILTPARS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 3
// Offset: 0x22AC
typedef union _REG_NL2DRFILTPARS3
{
	UINT32 value;
	struct
	{
		UINT32 rfs6                 : 16; // [15:0] R Filtpar S6(1.9.6)
		UINT32 rfs7                 : 16; // [31:16] R Filtpar S7(1.9.6)
	} field;
} REG_NL2DRFILTPARS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 4
// Offset: 0x22B0
typedef union _REG_NL2DRFILTPARS4
{
	UINT32 value;
	struct
	{
		UINT32 rfs8                 : 16; // [15:0] R Filtpar S8(1.9.6)
		UINT32 rfs9                 : 16; // [31:16] R Filtpar S9(1.9.6)
	} field;
} REG_NL2DRFILTPARS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 5
// Offset: 0x22B4
typedef union _REG_NL2DRFILTPARS5
{
	UINT32 value;
	struct
	{
		UINT32 rfs10                : 16; // [15:0] R Filtpar S10(1.9.6)
		UINT32 rfs11                : 16; // [31:16] R Filtpar S11(1.9.6)
	} field;
} REG_NL2DRFILTPARS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 6
// Offset: 0x22B8
typedef union _REG_NL2DRFILTPARS6
{
	UINT32 value;
	struct
	{
		UINT32 rfs12                : 16; // [15:0] R Filtpar S12(1.9.6)
		UINT32 rfs13                : 16; // [31:16] R Filtpar S13(1.9.6)
	} field;
} REG_NL2DRFILTPARS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D R FILTPAR S Register 7
// Offset: 0x22BC
typedef union _REG_NL2DRFILTPARS7
{
	UINT32 value;
	struct
	{
		UINT32 rfs14                : 16; // [15:0] R Filtpar S14(1.9.6)
		UINT32 rfs15                : 16; // [31:16] R Filtpar S15(1.9.6)
	} field;
} REG_NL2DRFILTPARS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 0
// Offset: 0x22C0
typedef union _REG_NL2DGFILTPARS0
{
	UINT32 value;
	struct
	{
		UINT32 gfs0                 : 16; // [15:0] G Filtpar S0(1.9.6)
		UINT32 gfs1                 : 16; // [31:16] G Filtpar S1(1.9.6)
	} field;
} REG_NL2DGFILTPARS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 1
// Offset: 0x22C4
typedef union _REG_NL2DGFILTPARS1
{
	UINT32 value;
	struct
	{
		UINT32 gfs2                 : 16; // [15:0] G Filtpar S2(1.9.6)
		UINT32 gfs3                 : 16; // [31:16] G Filtpar S3(1.9.6)
	} field;
} REG_NL2DGFILTPARS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 2
// Offset: 0x22C8
typedef union _REG_NL2DGFILTPARS2
{
	UINT32 value;
	struct
	{
		UINT32 gfs4                 : 16; // [15:0] G Filtpar S4(1.9.6)
		UINT32 gfs5                 : 16; // [31:16] G Filtpar S5(1.9.6)
	} field;
} REG_NL2DGFILTPARS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 3
// Offset: 0x22CC
typedef union _REG_NL2DGFILTPARS3
{
	UINT32 value;
	struct
	{
		UINT32 gfs6                 : 16; // [15:0] G Filtpar S6(1.9.6)
		UINT32 gfs7                 : 16; // [31:16] G Filtpar S7(1.9.6)
	} field;
} REG_NL2DGFILTPARS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 4
// Offset: 0x22D0
typedef union _REG_NL2DGFILTPARS4
{
	UINT32 value;
	struct
	{
		UINT32 gfs8                 : 16; // [15:0] G Filtpar S8(1.9.6)
		UINT32 gfs9                 : 16; // [31:16] G Filtpar S9(1.9.6)
	} field;
} REG_NL2DGFILTPARS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 5
// Offset: 0x22D4
typedef union _REG_NL2DGFILTPARS5
{
	UINT32 value;
	struct
	{
		UINT32 gfs10                : 16; // [15:0] G Filtpar S10(1.9.6)
		UINT32 gfs11                : 16; // [31:16] G Filtpar S11(1.9.6)
	} field;
} REG_NL2DGFILTPARS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 6
// Offset: 0x22D8
typedef union _REG_NL2DGFILTPARS6
{
	UINT32 value;
	struct
	{
		UINT32 gfs12                : 16; // [15:0] G Filtpar S12(1.9.6)
		UINT32 gfs13                : 16; // [31:16] G Filtpar S13(1.9.6)
	} field;
} REG_NL2DGFILTPARS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D G FILTPAR S Register 7
// Offset: 0x22DC
typedef union _REG_NL2DGFILTPARS7
{
	UINT32 value;
	struct
	{
		UINT32 gfs14                : 16; // [15:0] G Filtpar S14(1.9.6)
		UINT32 gfs15                : 16; // [31:16] G Filtpar S15(1.9.6)
	} field;
} REG_NL2DGFILTPARS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 0
// Offset: 0x22E0
typedef union _REG_NL2DBFILTPARS0
{
	UINT32 value;
	struct
	{
		UINT32 bfs0                 : 16; // [15:0] B Filtpar S0(1.9.6)
		UINT32 bfs1                 : 16; // [31:16] B Filtpar S1(1.9.6)
	} field;
} REG_NL2DBFILTPARS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 1
// Offset: 0x22E4
typedef union _REG_NL2DBFILTPARS1
{
	UINT32 value;
	struct
	{
		UINT32 bfs2                 : 16; // [15:0] B Filtpar S2(1.9.6)
		UINT32 bfs3                 : 16; // [31:16] B Filtpar S3(1.9.6)
	} field;
} REG_NL2DBFILTPARS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 2
// Offset: 0x22E8
typedef union _REG_NL2DBFILTPARS2
{
	UINT32 value;
	struct
	{
		UINT32 bfs4                 : 16; // [15:0] B Filtpar S4(1.9.6)
		UINT32 bfs5                 : 16; // [31:16] B Filtpar S5(1.9.6)
	} field;
} REG_NL2DBFILTPARS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 3
// Offset: 0x22EC
typedef union _REG_NL2DBFILTPARS3
{
	UINT32 value;
	struct
	{
		UINT32 bfs6                 : 16; // [15:0] B Filtpar S6(1.9.6)
		UINT32 bfs7                 : 16; // [31:16] B Filtpar S7(1.9.6)
	} field;
} REG_NL2DBFILTPARS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 4
// Offset: 0x22F0
typedef union _REG_NL2DBFILTPARS4
{
	UINT32 value;
	struct
	{
		UINT32 bfs8                 : 16; // [15:0] B Filtpar S8(1.9.6)
		UINT32 bfs9                 : 16; // [31:16] B Filtpar S9(1.9.6)
	} field;
} REG_NL2DBFILTPARS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 5
// Offset: 0x22F4
typedef union _REG_NL2DBFILTPARS5
{
	UINT32 value;
	struct
	{
		UINT32 bfs10                : 16; // [15:0] B Filtpar S10(1.9.6)
		UINT32 bfs11                : 16; // [31:16] B Filtpar S11(1.9.6)
	} field;
} REG_NL2DBFILTPARS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 6
// Offset: 0x22F8
typedef union _REG_NL2DBFILTPARS6
{
	UINT32 value;
	struct
	{
		UINT32 bfs12                : 16; // [15:0] B Filtpar S12(1.9.6)
		UINT32 bfs13                : 16; // [31:16] B Filtpar S13(1.9.6)
	} field;
} REG_NL2DBFILTPARS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D B FILTPAR S Register 7
// Offset: 0x22FC
typedef union _REG_NL2DBFILTPARS7
{
	UINT32 value;
	struct
	{
		UINT32 bfs14                : 16; // [15:0] B Filtpar S14(1.9.6)
		UINT32 bfs15                : 16; // [31:16] B Filtpar S15(1.9.6)
	} field;
} REG_NL2DBFILTPARS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D CFG Register
// Offset: 0x2300
typedef union _REG_NL2DCFG
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 2 ; // [1:0] TL - Top Left(read-only)
		UINT32 rsvd2                : 2 ; // [3:2] TR - Top Right(read-only)
		UINT32 rsvd4                : 2 ; // [5:4] BL - Bottom Left(read-only)
		UINT32 rsvd6                : 2 ; // [7:6] BR - Bottom Right(read-only)
		UINT32 minw                 : 9 ; // [16:8] min W
		UINT32 shift                : 3 ; // [19:17] shift
	} field;
} REG_NL2DCFG;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold X Register 0
// Offset: 0x2400
typedef union _REG_NWEDYS1THX0
{
	UINT32 value;
	struct
	{
		UINT32 ytx0                 : 10; // [9:0] Y Threshold X0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx1                 : 10; // [25:16] Y Threshold X1(0.10.0)
	} field;
} REG_NWEDYS1THX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1Threshold X Register 1
// Offset: 0x2404
typedef union _REG_NWEDYS1THX1
{
	UINT32 value;
	struct
	{
		UINT32 ytx2                 : 10; // [9:0] Y Threshold X2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx3                 : 10; // [25:16] Y Threshold X3(0.10.0)
	} field;
} REG_NWEDYS1THX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold X Register 2
// Offset: 0x2408
typedef union _REG_NWEDYS1THX2
{
	UINT32 value;
	struct
	{
		UINT32 ytx4                 : 10; // [9:0] Y Threshold X4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx5                 : 10; // [25:16] Y Threshold X5(0.10.0)
	} field;
} REG_NWEDYS1THX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold X Register 3
// Offset: 0x240C
typedef union _REG_NWEDYS1THX3
{
	UINT32 value;
	struct
	{
		UINT32 ytx6                 : 10; // [9:0] Y Threshold X6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx7                 : 10; // [25:16] Y Threshold X7(0.10.0)
	} field;
} REG_NWEDYS1THX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold X Register 4
// Offset: 0x2410
typedef union _REG_NWEDYS1THX4
{
	UINT32 value;
	struct
	{
		UINT32 ytx8                 : 10; // [9:0] Y Threshold X8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx9                 : 10; // [25:16] Y Threshold X9(0.10.0)
	} field;
} REG_NWEDYS1THX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold X Register 5
// Offset: 0x2414
typedef union _REG_NWEDYS1THX5
{
	UINT32 value;
	struct
	{
		UINT32 ytx10                : 10; // [9:0] Y Threshold X10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx11                : 10; // [25:16] Y Threshold X11(0.10.0)
	} field;
} REG_NWEDYS1THX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold X Register 6
// Offset: 0x2418
typedef union _REG_NWEDYS1THX6
{
	UINT32 value;
	struct
	{
		UINT32 ytx12                : 10; // [9:0] Y Threshold X12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx13                : 10; // [25:16] Y Threshold X13(0.10.0)
	} field;
} REG_NWEDYS1THX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold X Register 7
// Offset: 0x241C
typedef union _REG_NWEDYS1THX7
{
	UINT32 value;
	struct
	{
		UINT32 ytx14                : 10; // [9:0] Y Threshold X14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx15                : 10; // [25:16] Y Threshold X15(0.10.0)
	} field;
} REG_NWEDYS1THX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 0
// Offset: 0x2420
typedef union _REG_NWEDYS6THX0
{
	UINT32 value;
	struct
	{
		UINT32 ytx0                 : 10; // [9:0] Y Threshold X0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx1                 : 10; // [25:16] Y Threshold X1(0.10.0)
	} field;
} REG_NWEDYS6THX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 1
// Offset: 0x2424
typedef union _REG_NWEDYS6THX1
{
	UINT32 value;
	struct
	{
		UINT32 ytx2                 : 10; // [9:0] Y Threshold X2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx3                 : 10; // [25:16] Y Threshold X3(0.10.0)
	} field;
} REG_NWEDYS6THX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 2
// Offset: 0x2428
typedef union _REG_NWEDYS6THX2
{
	UINT32 value;
	struct
	{
		UINT32 ytx4                 : 10; // [9:0] Y Threshold X4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx5                 : 10; // [25:16] Y Threshold X5(0.10.0)
	} field;
} REG_NWEDYS6THX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 3
// Offset: 0x242C
typedef union _REG_NWEDYS6THX3
{
	UINT32 value;
	struct
	{
		UINT32 ytx6                 : 10; // [9:0] Y Threshold X6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx7                 : 10; // [25:16] Y Threshold X7(0.10.0)
	} field;
} REG_NWEDYS6THX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 4
// Offset: 0x2430
typedef union _REG_NWEDYS6THX4
{
	UINT32 value;
	struct
	{
		UINT32 ytx8                 : 10; // [9:0] Y Threshold X8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx9                 : 10; // [25:16] Y Threshold X9(0.10.0)
	} field;
} REG_NWEDYS6THX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 5
// Offset: 0x2434
typedef union _REG_NWEDYS6THX5
{
	UINT32 value;
	struct
	{
		UINT32 ytx10                : 10; // [9:0] Y Threshold X10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx11                : 10; // [25:16] Y Threshold X11(0.10.0)
	} field;
} REG_NWEDYS6THX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 6
// Offset: 0x2438
typedef union _REG_NWEDYS6THX6
{
	UINT32 value;
	struct
	{
		UINT32 ytx12                : 10; // [9:0] Y Threshold X12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx13                : 10; // [25:16] Y Threshold X13(0.10.0)
	} field;
} REG_NWEDYS6THX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold X Register 7
// Offset: 0x243C
typedef union _REG_NWEDYS6THX7
{
	UINT32 value;
	struct
	{
		UINT32 ytx14                : 10; // [9:0] Y Threshold X14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ytx15                : 10; // [25:16] Y Threshold X15(0.10.0)
	} field;
} REG_NWEDYS6THX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold X Register 0
// Offset: 0x2440
typedef union _REG_NWEDUVS1THX0
{
	UINT32 value;
	struct
	{
		UINT32 uvtx0                : 10; // [9:0] UV  Threshold X0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx1                : 10; // [25:16] UV  Threshold X1(0.10.0)
	} field;
} REG_NWEDUVS1THX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold X Register 1
// Offset: 0x2444
typedef union _REG_NWEDUVS1THX1
{
	UINT32 value;
	struct
	{
		UINT32 uvtx2                : 10; // [9:0] UV  Threshold X2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx3                : 10; // [25:16] UV  Threshold X3(0.10.0)
	} field;
} REG_NWEDUVS1THX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV  S1 Threshold X Register 2
// Offset: 0x2448
typedef union _REG_NWEDUVS1THX2
{
	UINT32 value;
	struct
	{
		UINT32 uvtx4                : 10; // [9:0] UV  Threshold X4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx5                : 10; // [25:16] UV  Threshold X5(0.10.0)
	} field;
} REG_NWEDUVS1THX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV  S1 Threshold X Register 3
// Offset: 0x244C
typedef union _REG_NWEDUVS1THX3
{
	UINT32 value;
	struct
	{
		UINT32 uvtx6                : 10; // [9:0] UV  Threshold X6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx7                : 10; // [25:16] UV  Threshold X7(0.10.0)
	} field;
} REG_NWEDUVS1THX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold X Register 4
// Offset: 0x2450
typedef union _REG_NWEDUVS1THX4
{
	UINT32 value;
	struct
	{
		UINT32 uvtx8                : 10; // [9:0] UV  Threshold X8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx9                : 10; // [25:16] UV  Threshold X9(0.10.0)
	} field;
} REG_NWEDUVS1THX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV  S1 Threshold X Register 5
// Offset: 0x2454
typedef union _REG_NWEDUVS1THX5
{
	UINT32 value;
	struct
	{
		UINT32 uvtx10               : 10; // [9:0] UV  Threshold X10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx11               : 10; // [25:16] UV  Threshold X11(0.10.0)
	} field;
} REG_NWEDUVS1THX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV  S1 Threshold X Register 6
// Offset: 0x2458
typedef union _REG_NWEDUVS1THX6
{
	UINT32 value;
	struct
	{
		UINT32 uvtx12               : 10; // [9:0] UV  Threshold X12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx13               : 10; // [25:16] UV  Threshold X13(0.10.0)
	} field;
} REG_NWEDUVS1THX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold X Register 7
// Offset: 0x245C
typedef union _REG_NWEDUVS1THX7
{
	UINT32 value;
	struct
	{
		UINT32 uvtx14               : 10; // [9:0] UV  Threshold X14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx15               : 10; // [25:16] UV  Threshold X15(0.10.0)
	} field;
} REG_NWEDUVS1THX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV  S6 Threshold X Register 0
// Offset: 0x2460
typedef union _REG_NWEDUVS6THX0
{
	UINT32 value;
	struct
	{
		UINT32 uvtx0                : 10; // [9:0] UV  Threshold X0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx1                : 10; // [25:16] UV  Threshold X1(0.10.0)
	} field;
} REG_NWEDUVS6THX0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV  S6 Threshold X Register 1
// Offset: 0x2464
typedef union _REG_NWEDUVS6THX1
{
	UINT32 value;
	struct
	{
		UINT32 uvtx2                : 10; // [9:0] UV  Threshold X2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx3                : 10; // [25:16] UV  Threshold X3(0.10.0)
	} field;
} REG_NWEDUVS6THX1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold X Register 2
// Offset: 0x2468
typedef union _REG_NWEDUVS6THX2
{
	UINT32 value;
	struct
	{
		UINT32 uvtx4                : 10; // [9:0] UV  Threshold X4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx5                : 10; // [25:16] UV  Threshold X5(0.10.0)
	} field;
} REG_NWEDUVS6THX2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold X Register 3
// Offset: 0x246C
typedef union _REG_NWEDUVS6THX3
{
	UINT32 value;
	struct
	{
		UINT32 uvtx6                : 10; // [9:0] UV  Threshold X6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx7                : 10; // [25:16] UV  Threshold X7(0.10.0)
	} field;
} REG_NWEDUVS6THX3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold X Register 4
// Offset: 0x2470
typedef union _REG_NWEDUVS6THX4
{
	UINT32 value;
	struct
	{
		UINT32 uvtx8                : 10; // [9:0] UV  Threshold X8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx9                : 10; // [25:16] UV  Threshold X9(0.10.0)
	} field;
} REG_NWEDUVS6THX4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold X Register 5
// Offset: 0x2474
typedef union _REG_NWEDUVS6THX5
{
	UINT32 value;
	struct
	{
		UINT32 uvtx10               : 10; // [9:0] UV  Threshold X10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx11               : 10; // [25:16] UV  Threshold X11(0.10.0)
	} field;
} REG_NWEDUVS6THX5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold X Register 6
// Offset: 0x2478
typedef union _REG_NWEDUVS6THX6
{
	UINT32 value;
	struct
	{
		UINT32 uvtx12               : 10; // [9:0] UV  Threshold X12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx13               : 10; // [25:16] UV  Threshold X13(0.10.0)
	} field;
} REG_NWEDUVS6THX6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold X Register 7
// Offset: 0x247C
typedef union _REG_NWEDUVS6THX7
{
	UINT32 value;
	struct
	{
		UINT32 uvtx14               : 10; // [9:0] UV  Threshold X14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvtx15               : 10; // [25:16] UV  Threshold X15(0.10.0)
	} field;
} REG_NWEDUVS6THX7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 0
// Offset: 0x2480
typedef union _REG_NWEDYS1THY0
{
	UINT32 value;
	struct
	{
		UINT32 yty0                 : 10; // [9:0] Y Threshold Y0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty1                 : 10; // [25:16] Y Threshold Y1(0.10.0)
	} field;
} REG_NWEDYS1THY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 1
// Offset: 0x2484
typedef union _REG_NWEDYS1THY1
{
	UINT32 value;
	struct
	{
		UINT32 yty2                 : 10; // [9:0] Y Threshold Y2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty3                 : 10; // [25:16] Y Threshold Y3(0.10.0)
	} field;
} REG_NWEDYS1THY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 2
// Offset: 0x2488
typedef union _REG_NWEDYS1THY2
{
	UINT32 value;
	struct
	{
		UINT32 yty4                 : 10; // [9:0] Y Threshold Y4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty5                 : 10; // [25:16] Y Threshold Y5(0.10.0)
	} field;
} REG_NWEDYS1THY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 3
// Offset: 0x248C
typedef union _REG_NWEDYS1THY3
{
	UINT32 value;
	struct
	{
		UINT32 yty6                 : 10; // [9:0] Y Threshold Y6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty7                 : 10; // [25:16] Y Threshold Y7(0.10.0)
	} field;
} REG_NWEDYS1THY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 4
// Offset: 0x2490
typedef union _REG_NWEDYS1THY4
{
	UINT32 value;
	struct
	{
		UINT32 yty8                 : 10; // [9:0] Y Threshold Y8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty9                 : 10; // [25:16] Y Threshold Y9(0.10.0)
	} field;
} REG_NWEDYS1THY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 5
// Offset: 0x2494
typedef union _REG_NWEDYS1THY5
{
	UINT32 value;
	struct
	{
		UINT32 yty10                : 10; // [9:0] Y Threshold Y10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty11                : 10; // [25:16] Y Threshold Y11(0.10.0)
	} field;
} REG_NWEDYS1THY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 6
// Offset: 0x2498
typedef union _REG_NWEDYS1THY6
{
	UINT32 value;
	struct
	{
		UINT32 yty12                : 10; // [9:0] Y Threshold Y12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty13                : 10; // [25:16] Y Threshold Y13(0.10.0)
	} field;
} REG_NWEDYS1THY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold Y Register 7
// Offset: 0x249C
typedef union _REG_NWEDYS1THY7
{
	UINT32 value;
	struct
	{
		UINT32 yty14                : 10; // [9:0] Y Threshold Y14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty15                : 10; // [25:16] Y Threshold Y15(0.10.0)
	} field;
} REG_NWEDYS1THY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 0
// Offset: 0x24A0
typedef union _REG_NWEDYS6THY0
{
	UINT32 value;
	struct
	{
		UINT32 yty0                 : 10; // [9:0] Y Threshold Y0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty1                 : 10; // [25:16] Y Threshold Y1(0.10.0)
	} field;
} REG_NWEDYS6THY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 1
// Offset: 0x24A4
typedef union _REG_NWEDYS6THY1
{
	UINT32 value;
	struct
	{
		UINT32 yty2                 : 10; // [9:0] Y Threshold Y2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty3                 : 10; // [25:16] Y Threshold Y3(0.10.0)
	} field;
} REG_NWEDYS6THY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 2
// Offset: 0x24A8
typedef union _REG_NWEDYS6THY2
{
	UINT32 value;
	struct
	{
		UINT32 yty4                 : 10; // [9:0] Y Threshold Y4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty5                 : 10; // [25:16] Y Threshold Y5(0.10.0)
	} field;
} REG_NWEDYS6THY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 3
// Offset: 0x24AC
typedef union _REG_NWEDYS6THY3
{
	UINT32 value;
	struct
	{
		UINT32 yty6                 : 10; // [9:0] Y Threshold Y6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty7                 : 10; // [25:16] Y Threshold Y7(0.10.0)
	} field;
} REG_NWEDYS6THY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 4
// Offset: 0x24B0
typedef union _REG_NWEDYS6THY4
{
	UINT32 value;
	struct
	{
		UINT32 yty8                 : 10; // [9:0] Y Threshold Y8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty9                 : 10; // [25:16] Y Threshold Y9(0.10.0)
	} field;
} REG_NWEDYS6THY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 5
// Offset: 0x24B4
typedef union _REG_NWEDYS6THY5
{
	UINT32 value;
	struct
	{
		UINT32 yty10                : 10; // [9:0] Y Threshold Y10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty11                : 10; // [25:16] Y Threshold Y11(0.10.0)
	} field;
} REG_NWEDYS6THY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 6
// Offset: 0x24B8
typedef union _REG_NWEDYS6THY6
{
	UINT32 value;
	struct
	{
		UINT32 yty12                : 10; // [9:0] Y Threshold Y12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty13                : 10; // [25:16] Y Threshold Y13(0.10.0)
	} field;
} REG_NWEDYS6THY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold Y Register 7
// Offset: 0x24BC
typedef union _REG_NWEDYS6THY7
{
	UINT32 value;
	struct
	{
		UINT32 yty14                : 10; // [9:0] Y Threshold Y14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 yty15                : 10; // [25:16] Y Threshold Y15(0.10.0)
	} field;
} REG_NWEDYS6THY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV ChannelS1 Threshold Y Register 0
// Offset: 0x24C0
typedef union _REG_NWEDUVS1THY0
{
	UINT32 value;
	struct
	{
		UINT32 uvty0                : 10; // [9:0] UV  Threshold Y0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty1                : 10; // [25:16] UV  Threshold Y1(0.10.0)
	} field;
} REG_NWEDUVS1THY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold Y Register 1
// Offset: 0x24C4
typedef union _REG_NWEDUVS1THY1
{
	UINT32 value;
	struct
	{
		UINT32 uvty2                : 10; // [9:0] UV  Threshold Y2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty3                : 10; // [25:16] UV  Threshold Y3(0.10.0)
	} field;
} REG_NWEDUVS1THY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold Y Register 2
// Offset: 0x24C8
typedef union _REG_NWEDUVS1THY2
{
	UINT32 value;
	struct
	{
		UINT32 uvty4                : 10; // [9:0] UV  Threshold Y4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty5                : 10; // [25:16] UV  Threshold Y5(0.10.0)
	} field;
} REG_NWEDUVS1THY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold Y Register 3
// Offset: 0x24CC
typedef union _REG_NWEDUVS1THY3
{
	UINT32 value;
	struct
	{
		UINT32 uvty6                : 10; // [9:0] UV  Threshold Y6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty7                : 10; // [25:16] UV  Threshold Y7(0.10.0)
	} field;
} REG_NWEDUVS1THY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold Y Register 4
// Offset: 0x24D0
typedef union _REG_NWEDUVS1THY4
{
	UINT32 value;
	struct
	{
		UINT32 uvty8                : 10; // [9:0] UV  Threshold Y8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty9                : 10; // [25:16] UV  Threshold Y9(0.10.0)
	} field;
} REG_NWEDUVS1THY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold Y Register 5
// Offset: 0x24D4
typedef union _REG_NWEDUVS1THY5
{
	UINT32 value;
	struct
	{
		UINT32 uvty10               : 10; // [9:0] UV  Threshold Y10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty11               : 10; // [25:16] UV  Threshold Y11(0.10.0)
	} field;
} REG_NWEDUVS1THY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold Y Register 6
// Offset: 0x24D8
typedef union _REG_NWEDUVS1THY6
{
	UINT32 value;
	struct
	{
		UINT32 uvty12               : 10; // [9:0] UV  Threshold Y12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty13               : 10; // [25:16] UV  Threshold Y13(0.10.0)
	} field;
} REG_NWEDUVS1THY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold Y Register 7
// Offset: 0x24DC
typedef union _REG_NWEDUVS1THY7
{
	UINT32 value;
	struct
	{
		UINT32 uvty14               : 10; // [9:0] UV  Threshold Y14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty15               : 10; // [25:16] UV  Threshold Y15(0.10.0)
	} field;
} REG_NWEDUVS1THY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV ChannelS6 Threshold Y Register 0
// Offset: 0x24E0
typedef union _REG_NWEDUVS6THY0
{
	UINT32 value;
	struct
	{
		UINT32 uvty0                : 10; // [9:0] UV  Threshold Y0(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty1                : 10; // [25:16] UV  Threshold Y1(0.10.0)
	} field;
} REG_NWEDUVS6THY0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold Y Register 1
// Offset: 0x24E4
typedef union _REG_NWEDUVS6THY1
{
	UINT32 value;
	struct
	{
		UINT32 uvty2                : 10; // [9:0] UV  Threshold Y2(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty3                : 10; // [25:16] UV  Threshold Y3(0.10.0)
	} field;
} REG_NWEDUVS6THY1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold Y Register 2
// Offset: 0x24E8
typedef union _REG_NWEDUVS6THY2
{
	UINT32 value;
	struct
	{
		UINT32 uvty4                : 10; // [9:0] UV  Threshold Y4(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty5                : 10; // [25:16] UV  Threshold Y5(0.10.0)
	} field;
} REG_NWEDUVS6THY2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold Y Register 3
// Offset: 0x24EC
typedef union _REG_NWEDUVS6THY3
{
	UINT32 value;
	struct
	{
		UINT32 uvty6                : 10; // [9:0] UV  Threshold Y6(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty7                : 10; // [25:16] UV  Threshold Y7(0.10.0)
	} field;
} REG_NWEDUVS6THY3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold Y Register 4
// Offset: 0x24F0
typedef union _REG_NWEDUVS6THY4
{
	UINT32 value;
	struct
	{
		UINT32 uvty8                : 10; // [9:0] UV  Threshold Y8(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty9                : 10; // [25:16] UV  Threshold Y9(0.10.0)
	} field;
} REG_NWEDUVS6THY4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold Y Register 5
// Offset: 0x24F4
typedef union _REG_NWEDUVS6THY5
{
	UINT32 value;
	struct
	{
		UINT32 uvty10               : 10; // [9:0] UV  Threshold Y10(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty11               : 10; // [25:16] UV  Threshold Y11(0.10.0)
	} field;
} REG_NWEDUVS6THY5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold Y Register 6
// Offset: 0x24F8
typedef union _REG_NWEDUVS6THY6
{
	UINT32 value;
	struct
	{
		UINT32 uvty12               : 10; // [9:0] UV  Threshold Y12(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty13               : 10; // [25:16] UV  Threshold Y13(0.10.0)
	} field;
} REG_NWEDUVS6THY6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold Y Register 7
// Offset: 0x24FC
typedef union _REG_NWEDUVS6THY7
{
	UINT32 value;
	struct
	{
		UINT32 uvty14               : 10; // [9:0] UV  Threshold Y14(0.10.0)
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvty15               : 10; // [25:16] UV  Threshold Y15(0.10.0)
	} field;
} REG_NWEDUVS6THY7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 0
// Offset: 0x2500
typedef union _REG_NWEDYS1THS0
{
	UINT32 value;
	struct
	{
		UINT32 yts0                 : 13; // [12:0] Y Threshold S0(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts1                 : 13; // [28:16] Y Threshold S1(1.4.8)
	} field;
} REG_NWEDYS1THS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 1
// Offset: 0x2504
typedef union _REG_NWEDYS1THS1
{
	UINT32 value;
	struct
	{
		UINT32 yts2                 : 13; // [12:0] Y Threshold S2(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts3                 : 13; // [28:16] Y Threshold S3(1.4.8)
	} field;
} REG_NWEDYS1THS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 2
// Offset: 0x2508
typedef union _REG_NWEDYS1THS2
{
	UINT32 value;
	struct
	{
		UINT32 yts4                 : 13; // [12:0] Y Threshold S4(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts5                 : 13; // [28:16] Y Threshold S5(1.4.8)
	} field;
} REG_NWEDYS1THS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 3
// Offset: 0x250C
typedef union _REG_NWEDYS1THS3
{
	UINT32 value;
	struct
	{
		UINT32 yts6                 : 13; // [12:0] Y Threshold S6(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts7                 : 13; // [28:16] Y Threshold S7(1.4.8)
	} field;
} REG_NWEDYS1THS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 4
// Offset: 0x2510
typedef union _REG_NWEDYS1THS4
{
	UINT32 value;
	struct
	{
		UINT32 yts8                 : 13; // [12:0] Y Threshold S8(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts9                 : 13; // [28:16] Y Threshold S9(1.4.8)
	} field;
} REG_NWEDYS1THS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 5
// Offset: 0x2514
typedef union _REG_NWEDYS1THS5
{
	UINT32 value;
	struct
	{
		UINT32 yts10                : 13; // [12:0] Y Threshold S10(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts11                : 13; // [28:16] Y Threshold S11(1.4.8)
	} field;
} REG_NWEDYS1THS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 6
// Offset: 0x2518
typedef union _REG_NWEDYS1THS6
{
	UINT32 value;
	struct
	{
		UINT32 yts12                : 13; // [12:0] Y Threshold S12(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts13                : 13; // [28:16] Y Threshold S13(1.4.8)
	} field;
} REG_NWEDYS1THS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S1 Threshold S Register 7
// Offset: 0x251C
typedef union _REG_NWEDYS1THS7
{
	UINT32 value;
	struct
	{
		UINT32 yts14                : 13; // [12:0] Y Threshold S14(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts15                : 13; // [28:16] Y Threshold S15(1.4.8)
	} field;
} REG_NWEDYS1THS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 0
// Offset: 0x2520
typedef union _REG_NWEDYS6THS0
{
	UINT32 value;
	struct
	{
		UINT32 yts0                 : 13; // [12:0] Y Threshold S0(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts1                 : 13; // [28:16] Y Threshold S1(1.4.8)
	} field;
} REG_NWEDYS6THS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 1
// Offset: 0x2524
typedef union _REG_NWEDYS6THS1
{
	UINT32 value;
	struct
	{
		UINT32 yts2                 : 13; // [12:0] Y Threshold S2(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts3                 : 13; // [28:16] Y Threshold S3(1.4.8)
	} field;
} REG_NWEDYS6THS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 2
// Offset: 0x2528
typedef union _REG_NWEDYS6THS2
{
	UINT32 value;
	struct
	{
		UINT32 yts4                 : 13; // [12:0] Y Threshold S4(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts5                 : 13; // [28:16] Y Threshold S5(1.4.8)
	} field;
} REG_NWEDYS6THS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 3
// Offset: 0x252C
typedef union _REG_NWEDYS6THS3
{
	UINT32 value;
	struct
	{
		UINT32 yts6                 : 13; // [12:0] Y Threshold S6(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts7                 : 13; // [28:16] Y Threshold S7(1.4.8)
	} field;
} REG_NWEDYS6THS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 4
// Offset: 0x2530
typedef union _REG_NWEDYS6THS4
{
	UINT32 value;
	struct
	{
		UINT32 yts8                 : 13; // [12:0] Y Threshold S8(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts9                 : 13; // [28:16] Y Threshold S9(1.4.8)
	} field;
} REG_NWEDYS6THS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 5
// Offset: 0x2534
typedef union _REG_NWEDYS6THS5
{
	UINT32 value;
	struct
	{
		UINT32 yts10                : 13; // [12:0] Y Threshold S10(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts11                : 13; // [28:16] Y Threshold S11(1.4.8)
	} field;
} REG_NWEDYS6THS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 6
// Offset: 0x2538
typedef union _REG_NWEDYS6THS6
{
	UINT32 value;
	struct
	{
		UINT32 yts12                : 13; // [12:0] Y Threshold S12(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts13                : 13; // [28:16] Y Threshold S13(1.4.8)
	} field;
} REG_NWEDYS6THS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED Y Channel S6 Threshold S Register 7
// Offset: 0x253C
typedef union _REG_NWEDYS6THS7
{
	UINT32 value;
	struct
	{
		UINT32 yts14                : 13; // [12:0] Y Threshold S14(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 yts15                : 13; // [28:16] Y Threshold S15(1.4.8)
	} field;
} REG_NWEDYS6THS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 0
// Offset: 0x2540
typedef union _REG_NWEDUVS1THS0
{
	UINT32 value;
	struct
	{
		UINT32 uvts0                : 13; // [12:0] UV Threshold S0(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts1                : 13; // [28:16] UV Threshold S1(1.4.8)
	} field;
} REG_NWEDUVS1THS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 1
// Offset: 0x2544
typedef union _REG_NWEDUVS1THS1
{
	UINT32 value;
	struct
	{
		UINT32 uvts2                : 13; // [12:0] UV Threshold S2(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts3                : 13; // [28:16] UV Threshold S3(1.4.8)
	} field;
} REG_NWEDUVS1THS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 2
// Offset: 0x2548
typedef union _REG_NWEDUVS1THS2
{
	UINT32 value;
	struct
	{
		UINT32 uvts4                : 13; // [12:0] UV Threshold S4(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts5                : 13; // [28:16] UV Threshold S5(1.4.8)
	} field;
} REG_NWEDUVS1THS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 3
// Offset: 0x254C
typedef union _REG_NWEDUVS1THS3
{
	UINT32 value;
	struct
	{
		UINT32 uvts6                : 13; // [12:0] UV Threshold S6(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts7                : 13; // [28:16] UV Threshold S7(1.4.8)
	} field;
} REG_NWEDUVS1THS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 4
// Offset: 0x2550
typedef union _REG_NWEDUVS1THS4
{
	UINT32 value;
	struct
	{
		UINT32 uvts8                : 13; // [12:0] UV Threshold S8(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts9                : 13; // [28:16] UV Threshold S9(1.4.8)
	} field;
} REG_NWEDUVS1THS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 5
// Offset: 0x2554
typedef union _REG_NWEDUVS1THS5
{
	UINT32 value;
	struct
	{
		UINT32 uvts10               : 13; // [12:0] UV Threshold S10(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts11               : 13; // [28:16] UV Threshold S11(1.4.8)
	} field;
} REG_NWEDUVS1THS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 6
// Offset: 0x2558
typedef union _REG_NWEDUVS1THS6
{
	UINT32 value;
	struct
	{
		UINT32 uvts12               : 13; // [12:0] UV Threshold S12(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts13               : 13; // [28:16] UV Threshold S13(1.4.8)
	} field;
} REG_NWEDUVS1THS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S1 Threshold S Register 7
// Offset: 0x255C
typedef union _REG_NWEDUVS1THS7
{
	UINT32 value;
	struct
	{
		UINT32 uvts14               : 13; // [12:0] UV Threshold S14(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts15               : 13; // [28:16] UV Threshold S15(1.4.8)
	} field;
} REG_NWEDUVS1THS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 0
// Offset: 0x2560
typedef union _REG_NWEDUVS6THS0
{
	UINT32 value;
	struct
	{
		UINT32 uvts0                : 13; // [12:0] UV Threshold S0(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts1                : 13; // [28:16] UV Threshold S1(1.4.8)
	} field;
} REG_NWEDUVS6THS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 1
// Offset: 0x2564
typedef union _REG_NWEDUVS6THS1
{
	UINT32 value;
	struct
	{
		UINT32 uvts2                : 13; // [12:0] UV Threshold S2(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts3                : 13; // [28:16] UV Threshold S3(1.4.8)
	} field;
} REG_NWEDUVS6THS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 2
// Offset: 0x2568
typedef union _REG_NWEDUVS6THS2
{
	UINT32 value;
	struct
	{
		UINT32 uvts4                : 13; // [12:0] UV Threshold S4(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts5                : 13; // [28:16] UV Threshold S5(1.4.8)
	} field;
} REG_NWEDUVS6THS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 3
// Offset: 0x256C
typedef union _REG_NWEDUVS6THS3
{
	UINT32 value;
	struct
	{
		UINT32 uvts6                : 13; // [12:0] UV Threshold S6(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts7                : 13; // [28:16] UV Threshold S7(1.4.8)
	} field;
} REG_NWEDUVS6THS3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 4
// Offset: 0x2570
typedef union _REG_NWEDUVS6THS4
{
	UINT32 value;
	struct
	{
		UINT32 uvts8                : 13; // [12:0] UV Threshold S8(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts9                : 13; // [28:16] UV Threshold S9(1.4.8)
	} field;
} REG_NWEDUVS6THS4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 5
// Offset: 0x2574
typedef union _REG_NWEDUVS6THS5
{
	UINT32 value;
	struct
	{
		UINT32 uvts10               : 13; // [12:0] UV Threshold S10(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts11               : 13; // [28:16] UV Threshold S11(1.4.8)
	} field;
} REG_NWEDUVS6THS5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 6
// Offset: 0x2578
typedef union _REG_NWEDUVS6THS6
{
	UINT32 value;
	struct
	{
		UINT32 uvts12               : 13; // [12:0] UV Threshold S12(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts13               : 13; // [28:16] UV Threshold S13(1.4.8)
	} field;
} REG_NWEDUVS6THS6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED UV Channel S6 Threshold S Register 7
// Offset: 0x257C
typedef union _REG_NWEDUVS6THS7
{
	UINT32 value;
	struct
	{
		UINT32 uvts14               : 13; // [12:0] UV Threshold S14(1.4.8)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvts15               : 13; // [28:16] UV Threshold S15(1.4.8)
	} field;
} REG_NWEDUVS6THS7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED DS Register 0
// Offset: 0x2580
typedef union _REG_NWEDDS0
{
	UINT32 value;
	struct
	{
		UINT32 ds0                  : 8 ; // [7:0] Scalars DS0(0.4.4)
		UINT32 ds1                  : 8 ; // [15:8] Scalars DS1(0.4.4)
		UINT32 ds2                  : 8 ; // [23:16] Scalars DS2(0.4.4)
		UINT32 ds3                  : 8 ; // [31:24] Scalars DS3(0.4.4)
	} field;
} REG_NWEDDS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED DS Register 1
// Offset: 0x2584
typedef union _REG_NWEDDS1
{
	UINT32 value;
	struct
	{
		UINT32 ds4                  : 8 ; // [7:0] Scalars DS4(0.4.4)
		UINT32 ds5                  : 8 ; // [15:8] Scalars DS5(0.4.4)
		UINT32 ds6                  : 8 ; // [23:16] Scalars DS6(0.4.4)
		UINT32 ds7                  : 8 ; // [31:24] Scalars DS7(0.4.4)
	} field;
} REG_NWEDDS1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 6~10bit(PW-4) offset register
// Offset: 0x3030
typedef union _REG_OBCO_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 10; // [9:0] [0.6/8/10.0] Offset at point A for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 b_s0                 : 10; // [25:16] [0.6/8/10.0] Offset at point B for symbol 2
	} field;
} REG_OBCO_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 6~10bit(PW-4) offset register
// Offset: 0x3034
typedef union _REG_OBCO_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 c_s0                 : 10; // [9:0] [0.6/8/10.0] Offset at point C for symbol 2
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 d_s0                 : 10; // [25:16] [0.6/8/10.0] Offset at point D for symbol 2
	} field;
} REG_OBCO_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 6~10bit(PW-4) offset register
// Offset: 0x3038
typedef union _REG_OBCO_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 a_s0                 : 10; // [9:0] [0.6/8/10.0] Offset at point A for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 b_s0                 : 10; // [25:16] [0.6/8/10.0] Offset at point B for symbol 3
	} field;
} REG_OBCO_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// each symbol has four point, each point has one 6~10bit(PW-4) offset register
// Offset: 0x303C
typedef union _REG_OBCO_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 c_s0                 : 10; // [9:0] [0.6/8/10.0] Offset at point C for symbol 3
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 d_s0                 : 10; // [25:16] [0.6/8/10.0] Offset at point D for symbol 3
	} field;
} REG_OBCO_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x3200
typedef union _REG_OECFC_X0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s0                : 14; // [13:0] X0 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x1_s0                : 14; // [29:16] X1 for symbol 0
	} field;
} REG_OECFC_X0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x3204
typedef union _REG_OECFC_X0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s0                : 14; // [13:0] X2 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x3_s0                : 14; // [29:16] X3 for symbol 0
	} field;
} REG_OECFC_X0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x3208
typedef union _REG_OECFC_X0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s0                : 14; // [13:0] X4 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x5_s0                : 14; // [29:16] X5 for symbol 0
	} field;
} REG_OECFC_X0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x320C
typedef union _REG_OECFC_X0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s0                : 14; // [13:0] X6 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x7_s0                : 14; // [29:16] X7 for symbol 0
	} field;
} REG_OECFC_X0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x3210
typedef union _REG_OECFC_X0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s0                : 14; // [13:0] X8 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x9_s0                : 14; // [29:16] X9 for symbol 0
	} field;
} REG_OECFC_X0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x3214
typedef union _REG_OECFC_X0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s0               : 14; // [13:0] X10 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x11_s0               : 14; // [29:16] X11 for symbol 0
	} field;
} REG_OECFC_X0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x3218
typedef union _REG_OECFC_X0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s0               : 14; // [13:0] X12 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x13_s0               : 14; // [29:16] X13 for symbol 0
	} field;
} REG_OECFC_X0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
// Offset: 0x321C
typedef union _REG_OECFC_X0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s0               : 14; // [13:0] X14 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x15_s0               : 14; // [29:16] X15 for symbol 0
	} field;
} REG_OECFC_X0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x3220
typedef union _REG_OECFC_X1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s1                : 14; // [13:0] X0 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x1_s1                : 14; // [29:16] X1 for symbol 1
	} field;
} REG_OECFC_X1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x3224
typedef union _REG_OECFC_X1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s1                : 14; // [13:0] X2 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x3_s1                : 14; // [29:16] X3 for symbol 1
	} field;
} REG_OECFC_X1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x3228
typedef union _REG_OECFC_X1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s1                : 14; // [13:0] X4 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x5_s1                : 14; // [29:16] X5 for symbol 1
	} field;
} REG_OECFC_X1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x322C
typedef union _REG_OECFC_X1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s1                : 14; // [13:0] X6 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x7_s1                : 14; // [29:16] X7 for symbol 1
	} field;
} REG_OECFC_X1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x3230
typedef union _REG_OECFC_X1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s1                : 14; // [13:0] X8 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x9_s1                : 14; // [29:16] X9 for symbol 1
	} field;
} REG_OECFC_X1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x3234
typedef union _REG_OECFC_X1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s1               : 14; // [13:0] X10 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x11_s1               : 14; // [29:16] X11 for symbol 1
	} field;
} REG_OECFC_X1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x3238
typedef union _REG_OECFC_X1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s1               : 14; // [13:0] X12 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x13_s1               : 14; // [29:16] X13 for symbol 1
	} field;
} REG_OECFC_X1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
// Offset: 0x323C
typedef union _REG_OECFC_X1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s1               : 14; // [13:0] X14 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x15_s1               : 14; // [29:16] X15 for symbol 1
	} field;
} REG_OECFC_X1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x3240
typedef union _REG_OECFC_X2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s2                : 14; // [13:0] X0 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x1_s2                : 14; // [29:16] X1 for symbol 2
	} field;
} REG_OECFC_X2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x3244
typedef union _REG_OECFC_X2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s2                : 14; // [13:0] X2 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x3_s2                : 14; // [29:16] X3 for symbol 2
	} field;
} REG_OECFC_X2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x3248
typedef union _REG_OECFC_X2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s2                : 14; // [13:0] X4 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x5_s2                : 14; // [29:16] X5 for symbol 2
	} field;
} REG_OECFC_X2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x324C
typedef union _REG_OECFC_X2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s2                : 14; // [13:0] X6 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x7_s2                : 14; // [29:16] X7 for symbol 2
	} field;
} REG_OECFC_X2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x3250
typedef union _REG_OECFC_X2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s2                : 14; // [13:0] X8 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x9_s2                : 14; // [29:16] X9 for symbol 2
	} field;
} REG_OECFC_X2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x3254
typedef union _REG_OECFC_X2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s2               : 14; // [13:0] X10 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x11_s2               : 14; // [29:16] X11 for symbol 2
	} field;
} REG_OECFC_X2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x3258
typedef union _REG_OECFC_X2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s2               : 14; // [13:0] X12 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x13_s2               : 14; // [29:16] X13 for symbol 2
	} field;
} REG_OECFC_X2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
// Offset: 0x325C
typedef union _REG_OECFC_X2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s2               : 14; // [13:0] X14 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x15_s2               : 14; // [29:16] X15 for symbol 2
	} field;
} REG_OECFC_X2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x3260
typedef union _REG_OECFC_X3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 x0_s3                : 14; // [13:0] X0 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x1_s3                : 14; // [29:16] X1 for symbol 3
	} field;
} REG_OECFC_X3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x3264
typedef union _REG_OECFC_X3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 x2_s3                : 14; // [13:0] X2 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x3_s3                : 14; // [29:16] X3 for symbol 3
	} field;
} REG_OECFC_X3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x3268
typedef union _REG_OECFC_X3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 x4_s3                : 14; // [13:0] X4 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x5_s3                : 14; // [29:16] X5 for symbol 3
	} field;
} REG_OECFC_X3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x326C
typedef union _REG_OECFC_X3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 x6_s3                : 14; // [13:0] X6 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x7_s3                : 14; // [29:16] X7 for symbol 3
	} field;
} REG_OECFC_X3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x3270
typedef union _REG_OECFC_X3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 x8_s3                : 14; // [13:0] X8 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x9_s3                : 14; // [29:16] X9 for symbol 3
	} field;
} REG_OECFC_X3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x3274
typedef union _REG_OECFC_X3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 x10_s3               : 14; // [13:0] X10 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x11_s3               : 14; // [29:16] X11 for symbol 3
	} field;
} REG_OECFC_X3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x3278
typedef union _REG_OECFC_X3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 x12_s3               : 14; // [13:0] X12 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x13_s3               : 14; // [29:16] X13 for symbol 3
	} field;
} REG_OECFC_X3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
// Offset: 0x327C
typedef union _REG_OECFC_X3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 x14_s3               : 14; // [13:0] X14 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 x15_s3               : 14; // [29:16] X15 for symbol 3
	} field;
} REG_OECFC_X3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x3280
typedef union _REG_OECFC_Y0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s0                : 14; // [13:0] Y0 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y1_s0                : 14; // [29:16] Y1 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x3284
typedef union _REG_OECFC_Y0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s0                : 14; // [13:0] Y2 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y3_s0                : 14; // [29:16] Y3 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x3288
typedef union _REG_OECFC_Y0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s0                : 14; // [13:0] Y4 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y5_s0                : 14; // [29:16] Y5 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x328C
typedef union _REG_OECFC_Y0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s0                : 14; // [13:0] Y6 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y7_s0                : 14; // [29:16] Y7 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x3290
typedef union _REG_OECFC_Y0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s0                : 14; // [13:0] Y8 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y9_s0                : 14; // [29:16] Y9 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x3294
typedef union _REG_OECFC_Y0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s0               : 14; // [13:0] Y10 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y11_s0               : 14; // [29:16] Y11 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x3298
typedef union _REG_OECFC_Y0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s0               : 14; // [13:0] Y12 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y13_s0               : 14; // [29:16] Y13 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
// Offset: 0x329C
typedef union _REG_OECFC_Y0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s0               : 14; // [13:0] Y14 for symbol 0
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y15_s0               : 14; // [29:16] Y15 for symbol 0
	} field;
} REG_OECFC_Y0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32A0
typedef union _REG_OECFC_Y1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s1                : 14; // [13:0] Y0 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y1_s1                : 14; // [29:16] Y1 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32A4
typedef union _REG_OECFC_Y1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s1                : 14; // [13:0] Y2 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y3_s1                : 14; // [29:16] Y3 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32A8
typedef union _REG_OECFC_Y1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s1                : 14; // [13:0] Y4 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y5_s1                : 14; // [29:16] Y5 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32AC
typedef union _REG_OECFC_Y1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s1                : 14; // [13:0] Y6 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y7_s1                : 14; // [29:16] Y7 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32B0
typedef union _REG_OECFC_Y1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s1                : 14; // [13:0] Y8 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y9_s1                : 14; // [29:16] Y9 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32B4
typedef union _REG_OECFC_Y1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s1               : 14; // [13:0] Y10 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y11_s1               : 14; // [29:16] Y11 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32B8
typedef union _REG_OECFC_Y1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s1               : 14; // [13:0] Y12 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y13_s1               : 14; // [29:16] Y13 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
// Offset: 0x32BC
typedef union _REG_OECFC_Y1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s1               : 14; // [13:0] Y14 for symbol 1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y15_s1               : 14; // [29:16] Y15 for symbol 1
	} field;
} REG_OECFC_Y1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32C0
typedef union _REG_OECFC_Y2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s2                : 14; // [13:0] Y0 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y1_s2                : 14; // [29:16] Y1 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32C4
typedef union _REG_OECFC_Y2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s2                : 14; // [13:0] Y2 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y3_s2                : 14; // [29:16] Y3 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32C8
typedef union _REG_OECFC_Y2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s2                : 14; // [13:0] Y4 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y5_s2                : 14; // [29:16] Y5 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32CC
typedef union _REG_OECFC_Y2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s2                : 14; // [13:0] Y6 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y7_s2                : 14; // [29:16] Y7 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32D0
typedef union _REG_OECFC_Y2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s2                : 14; // [13:0] Y8 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y9_s2                : 14; // [29:16] Y9 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32D4
typedef union _REG_OECFC_Y2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s2               : 14; // [13:0] Y10 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y11_s2               : 14; // [29:16] Y11 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32D8
typedef union _REG_OECFC_Y2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s2               : 14; // [13:0] Y12 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y13_s2               : 14; // [29:16] Y13 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
// Offset: 0x32DC
typedef union _REG_OECFC_Y2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s2               : 14; // [13:0] Y14 for symbol 2
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y15_s2               : 14; // [29:16] Y15 for symbol 2
	} field;
} REG_OECFC_Y2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32E0
typedef union _REG_OECFC_Y3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 y0_s3                : 14; // [13:0] Y0 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y1_s3                : 14; // [29:16] Y1 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32E4
typedef union _REG_OECFC_Y3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 y2_s3                : 14; // [13:0] Y2 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y3_s3                : 14; // [29:16] Y3 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32E8
typedef union _REG_OECFC_Y3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 y4_s3                : 14; // [13:0] Y4 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y5_s3                : 14; // [29:16] Y5 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32EC
typedef union _REG_OECFC_Y3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 y6_s3                : 14; // [13:0] Y6 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y7_s3                : 14; // [29:16] Y7 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32F0
typedef union _REG_OECFC_Y3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 y8_s3                : 14; // [13:0] Y8 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y9_s3                : 14; // [29:16] Y9 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32F4
typedef union _REG_OECFC_Y3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 y10_s3               : 14; // [13:0] Y10 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y11_s3               : 14; // [29:16] Y11 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32F8
typedef union _REG_OECFC_Y3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 y12_s3               : 14; // [13:0] Y12 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y13_s3               : 14; // [29:16] Y13 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
// Offset: 0x32FC
typedef union _REG_OECFC_Y3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 y14_s3               : 14; // [13:0] Y14 for symbol 3
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 y15_s3               : 14; // [29:16] Y15 for symbol 3
	} field;
} REG_OECFC_Y3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x3300
typedef union _REG_OECFC_S0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s0                : 16; // [15:0] S0 for symbol 0
		UINT32 s1_s0                : 16; // [31:16] S1 for symbol 0
	} field;
} REG_OECFC_S0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x3304
typedef union _REG_OECFC_S0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s0                : 16; // [15:0] S2 for symbol 0
		UINT32 s3_s0                : 16; // [31:16] S3 for symbol 0
	} field;
} REG_OECFC_S0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x3308
typedef union _REG_OECFC_S0_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s0                : 16; // [15:0] S4 for symbol 0
		UINT32 s5_s0                : 16; // [31:16] S5 for symbol 0
	} field;
} REG_OECFC_S0_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x330C
typedef union _REG_OECFC_S0_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s0                : 16; // [15:0] S6 for symbol 0
		UINT32 s7_s0                : 16; // [31:16] S7 for symbol 0
	} field;
} REG_OECFC_S0_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x3310
typedef union _REG_OECFC_S0_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s0                : 16; // [15:0] S8 for symbol 0
		UINT32 s9_s0                : 16; // [31:16] S9 for symbol 0
	} field;
} REG_OECFC_S0_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x3314
typedef union _REG_OECFC_S0_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s0               : 16; // [15:0] S10 for symbol 0
		UINT32 s11_s0               : 16; // [31:16] S11 for symbol 0
	} field;
} REG_OECFC_S0_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x3318
typedef union _REG_OECFC_S0_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s0               : 16; // [15:0] S12 for symbol 0
		UINT32 s13_s0               : 16; // [31:16] S13 for symbol 0
	} field;
} REG_OECFC_S0_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
// Offset: 0x331C
typedef union _REG_OECFC_S0_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s0               : 16; // [15:0] S14 for symbol 0
		UINT32 s15_s0               : 16; // [31:16] S15 for symbol 0
	} field;
} REG_OECFC_S0_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x3320
typedef union _REG_OECFC_S1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s1                : 16; // [15:0] S0 for symbol 1
		UINT32 s1_s1                : 16; // [31:16] S1 for symbol 1
	} field;
} REG_OECFC_S1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x3324
typedef union _REG_OECFC_S1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s1                : 16; // [15:0] S2 for symbol 1
		UINT32 s3_s1                : 16; // [31:16] S3 for symbol 1
	} field;
} REG_OECFC_S1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x3328
typedef union _REG_OECFC_S1_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s1                : 16; // [15:0] S4 for symbol 1
		UINT32 s5_s1                : 16; // [31:16] S5 for symbol 1
	} field;
} REG_OECFC_S1_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x332C
typedef union _REG_OECFC_S1_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s1                : 16; // [15:0] S6 for symbol 1
		UINT32 s7_s1                : 16; // [31:16] S7 for symbol 1
	} field;
} REG_OECFC_S1_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x3330
typedef union _REG_OECFC_S1_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s1                : 16; // [15:0] S8 for symbol 1
		UINT32 s9_s1                : 16; // [31:16] S9 for symbol 1
	} field;
} REG_OECFC_S1_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x3334
typedef union _REG_OECFC_S1_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s1               : 16; // [15:0] S10 for symbol 1
		UINT32 s11_s1               : 16; // [31:16] S11 for symbol 1
	} field;
} REG_OECFC_S1_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x3338
typedef union _REG_OECFC_S1_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s1               : 16; // [15:0] S12 for symbol 1
		UINT32 s13_s1               : 16; // [31:16] S13 for symbol 1
	} field;
} REG_OECFC_S1_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
// Offset: 0x333C
typedef union _REG_OECFC_S1_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s1               : 16; // [15:0] S14 for symbol 1
		UINT32 s15_s1               : 16; // [31:16] S15 for symbol 1
	} field;
} REG_OECFC_S1_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x3340
typedef union _REG_OECFC_S2_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s2                : 16; // [15:0] S0 for symbol 2
		UINT32 s1_s2                : 16; // [31:16] S1 for symbol 2
	} field;
} REG_OECFC_S2_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x3344
typedef union _REG_OECFC_S2_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s2                : 16; // [15:0] S2 for symbol 2
		UINT32 s3_s2                : 16; // [31:16] S3 for symbol 2
	} field;
} REG_OECFC_S2_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x3348
typedef union _REG_OECFC_S2_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s2                : 16; // [15:0] S4 for symbol 2
		UINT32 s5_s2                : 16; // [31:16] S5 for symbol 2
	} field;
} REG_OECFC_S2_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x334C
typedef union _REG_OECFC_S2_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s2                : 16; // [15:0] S6 for symbol 2
		UINT32 s7_s2                : 16; // [31:16] S7 for symbol 2
	} field;
} REG_OECFC_S2_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x3350
typedef union _REG_OECFC_S2_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s2                : 16; // [15:0] S8 for symbol 2
		UINT32 s9_s2                : 16; // [31:16] S9 for symbol 2
	} field;
} REG_OECFC_S2_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x3354
typedef union _REG_OECFC_S2_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s2               : 16; // [15:0] S10 for symbol 2
		UINT32 s11_s2               : 16; // [31:16] S11 for symbol 2
	} field;
} REG_OECFC_S2_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x3358
typedef union _REG_OECFC_S2_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s2               : 16; // [15:0] S12 for symbol 2
		UINT32 s13_s2               : 16; // [31:16] S13 for symbol 2
	} field;
} REG_OECFC_S2_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
// Offset: 0x335C
typedef union _REG_OECFC_S2_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s2               : 16; // [15:0] S14 for symbol 2
		UINT32 s15_s2               : 16; // [31:16] S15 for symbol 2
	} field;
} REG_OECFC_S2_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x3360
typedef union _REG_OECFC_S3_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 s0_s3                : 16; // [15:0] S0 for symbol 3
		UINT32 s1_s3                : 16; // [31:16] S1 for symbol 3
	} field;
} REG_OECFC_S3_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x3364
typedef union _REG_OECFC_S3_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 s2_s3                : 16; // [15:0] S2 for symbol 3
		UINT32 s3_s3                : 16; // [31:16] S3 for symbol 3
	} field;
} REG_OECFC_S3_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x3368
typedef union _REG_OECFC_S3_CFG_2
{
	UINT32 value;
	struct
	{
		UINT32 s4_s3                : 16; // [15:0] S4 for symbol 3
		UINT32 s5_s3                : 16; // [31:16] S5 for symbol 3
	} field;
} REG_OECFC_S3_CFG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x336C
typedef union _REG_OECFC_S3_CFG_3
{
	UINT32 value;
	struct
	{
		UINT32 s6_s3                : 16; // [15:0] S6 for symbol 3
		UINT32 s7_s3                : 16; // [31:16] S7 for symbol 3
	} field;
} REG_OECFC_S3_CFG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x3370
typedef union _REG_OECFC_S3_CFG_4
{
	UINT32 value;
	struct
	{
		UINT32 s8_s3                : 16; // [15:0] S8 for symbol 3
		UINT32 s9_s3                : 16; // [31:16] S9 for symbol 3
	} field;
} REG_OECFC_S3_CFG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x3374
typedef union _REG_OECFC_S3_CFG_5
{
	UINT32 value;
	struct
	{
		UINT32 s10_s3               : 16; // [15:0] S10 for symbol 3
		UINT32 s11_s3               : 16; // [31:16] S11 for symbol 3
	} field;
} REG_OECFC_S3_CFG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x3378
typedef union _REG_OECFC_S3_CFG_6
{
	UINT32 value;
	struct
	{
		UINT32 s12_s3               : 16; // [15:0] S12 for symbol 3
		UINT32 s13_s3               : 16; // [31:16] S13 for symbol 3
	} field;
} REG_OECFC_S3_CFG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
// Offset: 0x337C
typedef union _REG_OECFC_S3_CFG_7
{
	UINT32 value;
	struct
	{
		UINT32 s14_s3               : 16; // [15:0] S14 for symbol 3
		UINT32 s15_s3               : 16; // [31:16] S15 for symbol 3
	} field;
} REG_OECFC_S3_CFG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// sc1 frame cropping for sc ae/af
// Offset: 0x3810
typedef union _REG_SC1_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 16; // [15:0] Horizontal starting point for frame cropping
		UINT32 vstart               : 16; // [31:16] Vertical starting point for frame cropping
	} field;
} REG_SC1_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC1 cfg1 register
// Offset: 0x3814
typedef union _REG_SC1_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 width                : 5 ; // [4:0] Width of SC sub-window(SC_WIDTH+1)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 height               : 5 ; // [12:8] Height of SC sub-window(SC_HEIGHT+1)
		UINT32 rsvd13               : 17; // [29:13] 
		UINT32 sc1_sel              : 2 ; // [31:30] sc1 input mux for sc ae/af
	} field;
} REG_SC1_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// sc1 dec cfg register for sc ae/af, Horizontal/Vertical period/keep
// Offset: 0x3818
typedef union _REG_SC1_DEC
{
	UINT32 value;
	struct
	{
		UINT32 hperiod              : 5 ; // [4:0] Horizontal period(zero base)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 hkeep                : 5 ; // [12:8] Horizontal keep(zero base)
		UINT32 rsvd7                : 3 ; // [15:13] 
		UINT32 vperiod              : 5 ; // [20:16] Vertical period(zero base)
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 vkeep                : 5 ; // [28:24] Vertical keep(zero base)
	} field;
} REG_SC1_DEC;

////////////////////////////////////////////////////////////////////////////////////////////////////
// sc0 frame cropping for sc awb
// Offset: 0x3820
typedef union _REG_SC0_CFG_0
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 16; // [15:0] Horizontal starting point for frame cropping
		UINT32 vstart               : 16; // [31:16] Vertical starting point for frame cropping
	} field;
} REG_SC0_CFG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC0 cfg1 register
// Offset: 0x3824
typedef union _REG_SC0_CFG_1
{
	UINT32 value;
	struct
	{
		UINT32 width                : 5 ; // [4:0] Width of SC sub-window(SC_WIDTH+1)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 height               : 5 ; // [12:8] Height of SC sub-window(SC_HEIGHT+1)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 awb_ps_grb_ba        : 8 ; // [23:16] [0.4.4] awb b/a value
		UINT32 rsvd24               : 6 ; // [29:24] 
		UINT32 sc0_sel              : 2 ; // [31:30] sc0 input mux for sc awb
	} field;
} REG_SC0_CFG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// sc0 dec cfg register for sc awb, Horizontal/Vertical period/keep
// Offset: 0x3828
typedef union _REG_SC0_DEC
{
	UINT32 value;
	struct
	{
		UINT32 hperiod              : 5 ; // [4:0] Horizontal period(zero base)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 hkeep                : 5 ; // [12:8] Horizontal keep(zero base)
		UINT32 rsvd7                : 3 ; // [15:13] 
		UINT32 vperiod              : 5 ; // [20:16] Vertical period(zero base)
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 vkeep                : 5 ; // [28:24] Vertical keep(zero base)
	} field;
} REG_SC0_DEC;

////////////////////////////////////////////////////////////////////////////////////////////////////
// module clock gate config register
// Offset: 0x400C
typedef union _REG_CLKGCFG
{
	UINT32 value;
	struct
	{
		UINT32 dc_clkg              : 1 ; // [0] active high
		UINT32 dec_clkg             : 1 ; // [1] active high
		UINT32 obc_clkg             : 1 ; // [2] active high
		UINT32 oecfc_clkg           : 1 ; // [3] active high
		UINT32 oecf_clkg            : 1 ; // [4] active high
		UINT32 lcbq_clkg            : 1 ; // [5] active high
		UINT32 lccf_clkg            : 1 ; // [6] active high
		UINT32 oba_clkg             : 1 ; // [7] active high
		UINT32 dbc_clkg             : 1 ; // [8] active high
		UINT32 nl3d_clkg            : 1 ; // [9] active high
		UINT32 ctc_clkg             : 1 ; // [10] active high
		UINT32 nl2d_clkg            : 1 ; // [11] active high
		UINT32 ls_clkg              : 1 ; // [12] active high
		UINT32 gamr_clkg            : 1 ; // [13] active high
		UINT32 pf_clkg              : 1 ; // [14] active high
		UINT32 ca_clkg              : 1 ; // [15] active high
		UINT32 wdr_clkg             : 1 ; // [16] active high
		UINT32 lut_clkg             : 1 ; // [17] active high
		UINT32 ctm_clkg             : 1 ; // [18] active high
		UINT32 ycurve_clkg          : 1 ; // [19] active high
		UINT32 shrp_clkg            : 1 ; // [20] active high
		UINT32 bil_clkg             : 1 ; // [21] active high
		UINT32 sat_clkg             : 1 ; // [22] active high
		UINT32 yhist_clkg           : 1 ; // [23] active high
		UINT32 iti0_rd_clkg         : 1 ; // [24] tiling 0 read module clk gate, active high
		UINT32 iti0_wr_clkg         : 1 ; // [25] tiling 0 write module clk gate, active high
		UINT32 iti1_wr_clkg         : 1 ; // [26] tiling 1 write module clk gate, active high
	} field;
} REG_CLKGCFG;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sensor X/Y size
// Offset: 0x4028
typedef union _REG_SENSORSZ
{
	UINT32 value;
	struct
	{
		UINT32 w                    : 16; // [15:0] Active capture area width (xsize)
		UINT32 h                    : 16; // [31:16] Active capture area height(ysize)
	} field;
} REG_SENSORSZ;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline module interrupt mux register
// Offset: 0x403C
typedef union _REG_PMIMR
{
	UINT32 value;
	struct
	{
		UINT32 intmux               : 4 ; // [3:0] pipeline module frame end interrupt mux, the same as tiling index define
	} field;
} REG_PMIMR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP Interrupt Enable Register 
// Offset: 0x404C
typedef union _REG_ISPINTEN
{
	UINT32 value;
	struct
	{
		UINT32 rsvd                 : 16; // [15:0] 
		UINT32 inte                 : 16; // [31:16] interrupt enable
	} field;
} REG_ISPINTEN;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Tiling FBC control0 regsiter
// Offset: 0x4060
typedef union _REG_ITIFBC0
{
	UINT32 value;
	struct
	{
		UINT32 t1                   : 14; // [13:0] Threshold value T1
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 t2                   : 14; // [29:16] Threshold value T2
	} field;
} REG_ITIFBC0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Tiling FBC control1 regsiter
// Offset: 0x4064
typedef union _REG_ITIFBC1
{
	UINT32 value;
	struct
	{
		UINT32 ifbce                : 1 ; // [0] Tiling frame buffer compressed moudle enable
		UINT32 rsvd1                : 3 ; // [3:1] 
		UINT32 ct                   : 2 ; // [5:4] Color transform
		UINT32 rsc                  : 2 ; // [7:6] RAW start color, read only
		UINT32 spm                  : 2 ; // [9:8] Sample mode register, 2'b00 for 8bit, 2'b01 for 10bit, 2'b10 for 12bit, 2'b11 for 14bit;
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 t3                   : 14; // [29:16] Threshold value T3
	} field;
} REG_ITIFBC1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// tiling write0 DEC register, Horizontal/Vertical period/keep
// Offset: 0x4068
typedef union _REG_ITIDEC0
{
	UINT32 value;
	struct
	{
		UINT32 hperiod              : 5 ; // [4:0] Horizontal period(zero base)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 hkeep                : 5 ; // [12:8] Horizontal keep(zero base)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 vperiod              : 5 ; // [20:16] Vertical period(zero base)
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 vkeep                : 5 ; // [28:24] Vertical keep(zero base)
		UINT32 rsvd29               : 2 ; // [30:29] 
		UINT32 dec_en               : 1 ; // [31] tiling write enable
	} field;
} REG_ITIDEC0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// tiling write1 DEC register, Horizontal/Vertical period/keep
// Offset: 0x406C
typedef union _REG_ITIDEC1
{
	UINT32 value;
	struct
	{
		UINT32 hperiod              : 5 ; // [4:0] Horizontal period(zero base)
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 hkeep                : 5 ; // [12:8] Horizontal keep(zero base)
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 vperiod              : 5 ; // [20:16] Vertical period(zero base)
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 vkeep                : 5 ; // [28:24] Vertical keep(zero base)
		UINT32 rsvd29               : 2 ; // [30:29] 
		UINT32 dec_en               : 1 ; // [31] tiling write enable
	} field;
} REG_ITIDEC1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// tiling write 0 cropping register (x/y start location)
// Offset: 0x4070
typedef union _REG_ITICROP0
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 16; // [15:0] Horizontal starting point of capture window
		UINT32 vstart               : 16; // [31:16] Vertical starting point of capture window
	} field;
} REG_ITICROP0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// tiling write 0 cropping register (x/y end location)
// Offset: 0x4074
typedef union _REG_ITICROP1
{
	UINT32 value;
	struct
	{
		UINT32 hend                 : 16; // [15:0] Horizontal ending point of capture window, when hend = 0 will disable cropping (default)
		UINT32 vend                 : 16; // [31:16] Vertical ending point of capture window
	} field;
} REG_ITICROP1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// tiling write 1 cropping register (x/y start location)
// Offset: 0x4078
typedef union _REG_ITICROP2
{
	UINT32 value;
	struct
	{
		UINT32 hstart               : 16; // [15:0] Horizontal starting point of capture window
		UINT32 vstart               : 16; // [31:16] Vertical starting point of capture window
	} field;
} REG_ITICROP2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// tiling write 1 cropping register (x/y end location)
// Offset: 0x407C
typedef union _REG_ITICROP3
{
	UINT32 value;
	struct
	{
		UINT32 hend                 : 16; // [15:0] Horizontal ending point of capture window, when hend = 0 will disable cropping (default)
		UINT32 vend                 : 16; // [31:16] Vertical ending point of capture window
	} field;
} REG_ITICROP3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI write 0 Image Window Size Register
// Offset: 0x4080
typedef union _REG_ITIIWSR__
{
	UINT32 value;
	struct
	{
		UINT32 wsize                : 16; // [15:0] xsize for normal tiling 0 write
		UINT32 hsize                : 16; // [31:16] ysize for normal tiling 0 write
	} field;
} REG_ITIIWSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI read Image Window Size Register
// Offset: 0x4084
typedef union _REG_ITIRWSR__
{
	UINT32 value;
	struct
	{
		UINT32 wsize                : 16; // [15:0] xsize for  tiling read
		UINT32 hsize                : 16; // [31:16] ysize for  tiling read
	} field;
} REG_ITIRWSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM WRITE Line Stride Register, 64bit align,
// Offset: 0x4088
typedef union _REG_ITIDWLSR__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wstride              : 13; // [15:3] The line stride of  the next  line address  in DRAM Y buffer (8-byte Alignment) for the write path. when set to 1, indicate frame mode(no line stride)
		UINT32 reserved16           : 3 ; // [18:16] 
		UINT32 uvwstride            : 13; // [31:19] The line stride of  the next  line address  in DRAM UV buffer (8-byte Alignment) for the write path. when set to 1, indicate frame mode(no line stride)
	} field;
} REG_ITIDWLSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM READ Line Stride Register, 64bit align, 
// Offset: 0x408C
typedef union _REG_ITIDRLSR__
{
	UINT32 value;
	struct
	{
		UINT32 reserved0            : 3 ; // [2:0] 
		UINT32 rstride              : 13; // [15:3] The line stride of  the next  line address  in DRAM Y buffer (8-byte Alignment) for the READ  path. when set to 1, indicate frame mode(no line stride)
		UINT32 reserved16           : 3 ; // [18:16] 
		UINT32 uvrstride            : 13; // [31:19] The line stride of  the next  line address  in DRAM UV buffer (8-byte Alignment) for the READ  path. when set to 1, indicate frame mode(no line stride)
	} field;
} REG_ITIDRLSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write Y Start Address 0 Register, 64bit align
// Offset: 0x4090
typedef union _REG_ITIDWYSAR0__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] Data buffer start address 0 for writing RAW/Y plane in DRAM buffer(8-byte Alignment)
	} field;
} REG_ITIDWYSAR0__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write UV Start Address 0 Register, 64bit align
// Offset: 0x4094
typedef union _REG_ITIDWUSAR0__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wuvaddr              : 29; // [31:3] UV start address 0 (8-byte Alignment)
	} field;
} REG_ITIDWUSAR0__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read Y Start Address 0  Register, 64bit align
// Offset: 0x4098
typedef union _REG_ITIDRYSAR0__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ryaddr               : 29; // [31:3] read RAW/Y plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRYSAR0__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read UV Start Address 0  Register, 64bit align
// Offset: 0x409C
typedef union _REG_ITIDRUSAR0__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ruvaddr              : 29; // [31:3] read UV plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRUSAR0__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP Tiling Interface BUSY Status Register
// Offset: 0x40A0
typedef union _REG_ITIBSR__
{
	UINT32 value;
	struct
	{
		UINT32 wbusy0               : 1 ; // [0] write0 busy, active high(read-only)
		UINT32 rbusy                : 1 ; // [1] read busy, active high(read-only)
		UINT32 wbusy1               : 1 ; // [2] write1 busy, active high(read-only)
	} field;
} REG_ITIBSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Write Data Format  Register
// Offset: 0x40A4
typedef union _REG_ITIWRDFR__
{
	UINT32 value;
	struct
	{
		UINT32 wrformat             : 4 ; // [3:0] Data Package Format type for the write path.
		UINT32 wrflexiblebit        : 5 ; // [8:4] RAW flexible bit number for write
		UINT32 frameswreset_dsb     : 1 ; // [9] 0 : frame soft-reset enable, 1 : disable
		UINT32 yuvbitmode           : 1 ; // [10] tiling write 0, 0:8bit, 1:10bit
		UINT32 yuvpaddingmode       : 1 ; // [11] tiling write 0, 1:msb padding, 0:lsb padding
		UINT32 yuvsubsamplemode     : 2 ; // [13:12] tiling write 0 YUV420/422 sub-sample mode,
		UINT32 uvoffset_dsb         : 1 ; // [14] UV offset disable, 1:  disable add 512 in write path , 0: add 512 in write path
		UINT32 rsvd15               : 1 ; // [15] 
		UINT32 writeframemode       : 2 ; // [17:16] frame image write mode
		UINT32 writedumpen          : 1 ; // [18] one valid when WriteFrameMode set to non zero
		UINT32 writedumpdone        : 1 ; // [19] frame write done flag(read-only)
		UINT32 frame_cnt            : 2 ; // [21:20] current write frame counter(read only)
		UINT32 rvi_frame_cnt        : 2 ; // [23:22] write rvi interface frame cnt(read only)
	} field;
} REG_ITIWRDFR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI  Read Data Format  Register
// Offset: 0x40A8
typedef union _REG_ITIRDDFR__
{
	UINT32 value;
	struct
	{
		UINT32 rdformat             : 4 ; // [3:0] Data Package Format type for the read path
		UINT32 rdflexiblebit        : 5 ; // [8:4] RAW flexible bit number for read
		UINT32 rsvd9                : 1 ; // [9] 
		UINT32 yuvbitmode           : 1 ; // [10] tiling write 0, 0:8bit, 1:10bit
		UINT32 yuvpaddingmode       : 1 ; // [11] tiling write 0, 1:msb padding, 0:lsb padding
		UINT32 yuvsubsamplemode     : 2 ; // [13:12] tiling write 0 YUV420/422 sub-sample mode,
		UINT32 uvoffset_dsb         : 1 ; // [14] UV offset disable, 1:  disable sub 512 in read path , 0: sub 512 in read path
		UINT32 rdlinebufoff         : 1 ; // [15] Disable  UV line buffer function for  YUV de-package flow
		UINT32 readframemode        : 2 ; // [17:16] read frame mode 0:continuous frame, 1 : only read one frame image , 2 : read two frame image, 3 : read four frame image
		UINT32 rsvd18               : 1 ; // [18] 
		UINT32 readframedone        : 1 ; // [19] frame read done flag(read-only)
		UINT32 frame_cnt            : 2 ; // [21:20] current read frame counter(read only)
		UINT32 rsvd22               : 1 ; // [22] 
		UINT32 blanken              : 1 ; // [23] frame blanking enable, when set to high will generate blanking by BlankSize
		UINT32 blanksize            : 8 ; // [31:24] frame blanking size, vsync generate in the center of blanking(minimum=2)
	} field;
} REG_ITIRDDFR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ISP Tiling Interface  Data Path Select Register
// Offset: 0x40AC
typedef union _REG_ITIDPSR__
{
	UINT32 value;
	struct
	{
		UINT32 readindex            : 4 ; // [3:0] The index of the selected module whose input will be selected from DRAM buffer.
		UINT32 writeindex           : 4 ; // [7:4] The index of the selected module whose output will be written into DRAM buffer.
		UINT32 rd_sym               : 2 ; // [9:8] (read only) tiling read raw data first pixel symbol, 0-> R 1-> Gr 2-> Gb 3-> B
		UINT32 rbstm                : 2 ; // [11:10] tiling read axi outstanding mode, 0 : 4*1*8*64, 1: 2*2*8*64, 2: 1*4*8*64
		UINT32 wbstm                : 2 ; // [13:12] tiling write axi burst length mode, 0: burst 16, 1: burst 8, 2: burst 4
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 readdram             : 1 ; // [16] Enable the read function of the ITI interface from DRAM buffer.
		UINT32 writedram            : 1 ; // [17] Enable the write function of the ITI interface into DRAM buffer.
		UINT32 loopback             : 1 ; // [18] test pipeline control, but data from read tiling to write tiling
		UINT32 movedramdata         : 1 ; // [19] from read tiling to capture tiling when INDEPENDENTRDRVI not valid
		UINT32 independentrdrvi     : 1 ; // [20] Enable the independent  READ RVI signal function under  the normal  DRAM read mode. when set, readindex can't set to 1
		UINT32 independentwr        : 1 ; // [21] Enable the independent  write to DRAM, ignore next pipeline RVI
		UINT32 reserved22           : 2 ; // [23:22] 
		UINT32 rdnv21format         : 1 ; // [24] read UV swap, 1 : NV21, 0 : NV12
		UINT32 wrnv21format         : 1 ; // [25] write UV swap, 1 : NV21, 0 : NV12
		UINT32 hblank               : 5 ; // [30:26] Horizontal blanking size
		UINT32 hblank_dsb           : 1 ; // [31] Horizontal blanking disable,  for dram read mode, must disable.
	} field;
} REG_ITIDPSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write Y Start Address 1 Register, 64bit align
// Offset: 0x40B0
typedef union _REG_ITIDWYSAR1__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] RAW/Y plane buffer address 1(8-byte Alignment)
	} field;
} REG_ITIDWYSAR1__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write UV Start Address 1 Register, 64bit align
// Offset: 0x40B4
typedef union _REG_ITIDWUSAR1__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wuvaddr              : 29; // [31:3] UV plane buffer address 1(8-byte Alignment)
	} field;
} REG_ITIDWUSAR1__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write Y Start Address 2 Register, 64bit align
// Offset: 0x40B8
typedef union _REG_ITIDWYSAR2__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] RAW/Y plane buffer address 2(8-byte Alignment)
	} field;
} REG_ITIDWYSAR2__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write UV Start Address 2 Register, 64bit align
// Offset: 0x40BC
typedef union _REG_ITIDWUSAR2__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wuvaddr              : 29; // [31:3] UV plane buffer address 2(8-byte Alignment)
	} field;
} REG_ITIDWUSAR2__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write Y Start Address 3 Register, 64bit align
// Offset: 0x40C0
typedef union _REG_ITIDWYSAR3__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] RAW/Y plane buffer address 3(8-byte Alignment)
	} field;
} REG_ITIDWYSAR3__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Write UV Start Address 3 Register, 64bit align
// Offset: 0x40C4
typedef union _REG_ITIDWUSAR3__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wuvaddr              : 29; // [31:3] UV plane buffer address 3(8-byte Alignment)
	} field;
} REG_ITIDWUSAR3__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read Y Start Address 1 Register, 64bit align
// Offset: 0x40C8
typedef union _REG_ITIDRYSAR1__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ryaddr               : 29; // [31:3] read RAW/Y plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRYSAR1__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read UV Start Address 1  Register, 64bit align
// Offset: 0x40CC
typedef union _REG_ITIDRUSAR1__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ruvaddr              : 29; // [31:3] read UV plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRUSAR1__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read Y Start Address 2 Register, 64bit align
// Offset: 0x40D0
typedef union _REG_ITIDRYSAR2__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ryaddr               : 29; // [31:3] read RAW/Y plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRYSAR2__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read UV Start Address 2  Register, 64bit align
// Offset: 0x40D4
typedef union _REG_ITIDRUSAR2__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ruvaddr              : 29; // [31:3] read UV plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRUSAR2__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read Y Start Address 3 Register, 64bit align
// Offset: 0x40D8
typedef union _REG_ITIDRYSAR3__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ryaddr               : 29; // [31:3] read RAW/Y plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRYSAR3__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI DRAM Read UV Start Address 3  Register, 64bit align
// Offset: 0x40DC
typedef union _REG_ITIDRUSAR3__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 ruvaddr              : 29; // [31:3] read UV plane start addres(8-byte Alignment)
	} field;
} REG_ITIDRUSAR3__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Capture Image Window Size Register
// Offset: 0x40E0
typedef union _REG_ITICIWSR__
{
	UINT32 value;
	struct
	{
		UINT32 wsize                : 16; // [15:0] xsize
		UINT32 hsize                : 16; // [31:16] ysize
	} field;
} REG_ITICIWSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Capture WRITE Line Stride Register, 64bit align, 
// Offset: 0x40E4
typedef union _REG_ITICWLSR__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wstride              : 13; // [15:3] line stride for capture tiling
	} field;
} REG_ITICWLSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Capture Write Start Address 0 Register, 64bit align
// Offset: 0x40E8
typedef union _REG_ITICWYSAR0__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] Tiling Capture buffer address (8-byte Alignment)
	} field;
} REG_ITICWYSAR0__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Capture Write Start Address 1  Register, 64bit align
// Offset: 0x40EC
typedef union _REG_ITICWYSAR1__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] Tiling Capture buffer address (8-byte Alignment)
	} field;
} REG_ITICWYSAR1__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Capture Write Start Address 2  Register, 64bit align
// Offset: 0x40F0
typedef union _REG_ITICWYSAR2__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] Tiling Capture buffer address (8-byte Alignment)
	} field;
} REG_ITICWYSAR2__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Capture Write Start Address 3  Register, 64bit align
// Offset: 0x40F4
typedef union _REG_ITICWYSAR3__
{
	UINT32 value;
	struct
	{
		UINT32 reserved             : 3 ; // [2:0] 
		UINT32 wyaddr               : 29; // [31:3] Tiling Capture buffer address (8-byte Alignment)
	} field;
} REG_ITICWYSAR3__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI  Capture Package Data Format  Register
// Offset: 0x40F8
typedef union _REG_ITICPDFR__
{
	UINT32 value;
	struct
	{
		UINT32 wrformat             : 4 ; // [3:0] Data Package Format type for the write path.
		UINT32 wrflexiblebit        : 5 ; // [8:4] RAW flexible bit number for write
		UINT32 frameswreset_dsb     : 1 ; // [9] 0 : frame soft-reset enable, 1 : disable
		UINT32 yuvbitmode           : 1 ; // [10] tiling write 1, 0:8bit, 1:10bit
		UINT32 rsvd11               : 3 ; // [13:11] 
		UINT32 uvoffset_dsb         : 1 ; // [14] UV offset disable, 1:  disable add 512 in write path , 0: add 512 in write path
		UINT32 wcrop_sel            : 1 ; // [15] write crop source, 0  : from pipeline, 1 : from tiling read(for copy)
		UINT32 writeframemode       : 2 ; // [17:16] frame image write mode
		UINT32 writedumpen          : 1 ; // [18] one valid when WriteFrameMode set to non zero
		UINT32 writedumpdone        : 1 ; // [19] frame write done flag(read-only)
		UINT32 frame_cnt            : 2 ; // [21:20] current write frame counter(read only)
		UINT32 rvi_frame_cnt        : 2 ; // [23:22] write rvi interface frame cnt(read only)
	} field;
} REG_ITICPDFR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// ITI Capture  Data Path Select Register
// Offset: 0x40FC
typedef union _REG_ITICDPSR__
{
	UINT32 value;
	struct
	{
		UINT32 writeindex           : 4 ; // [3:0] Capture write index
		UINT32 writedram            : 1 ; // [4] Enable the write function of the ITI capture write interface into DRAM buffer.
		UINT32 independentwr        : 1 ; // [5] Enable the independent  write to DRAM, ignore next pipeline RVI
		UINT32 rsvd6                : 6 ; // [11:6] rsvd
		UINT32 wbstm                : 2 ; // [13:12] tiling write axi burst length mode, 0: burst 16, 1: burst 8, 2: burst 4
	} field;
} REG_ITICDPSR__;

////////////////////////////////////////////////////////////////////////////////////////////////////
// DC Return Buffer Address register
// Offset: 0x4104
typedef union _REG_DC_RBADR
{
	UINT32 value;
	struct
	{
		UINT32 rbadr                : 32; // [31:0] DC return current buffer address
	} field;
} REG_DC_RBADR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// GrGb Filter Mode Register
// Offset: 0x4120
typedef union _REG_IGRGB0
{
	UINT32 value;
	struct
	{
		UINT32 gf_mode              : 2 ; // [1:0] GrGb filter mode
	} field;
} REG_IGRGB0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// GrGb Filter threshold 1 Register
// Offset: 0x4124
typedef union _REG_IGRGB1
{
	UINT32 value;
	struct
	{
		UINT32 mingt                : 12; // [11:0] (0.PW.0 format)
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 maxgt                : 12; // [27:16] (0.PW.0 format)
	} field;
} REG_IGRGB1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// GrGb filter threshold 2 Register
// Offset: 0x4128
typedef union _REG_IGRGB2
{
	UINT32 value;
	struct
	{
		UINT32 badxt                : 12; // [11:0] (0.PW.0 format)
		UINT32 rsvd12               : 4 ; // [15:12] 
		UINT32 badgt                : 12; // [27:16] (0.PW.0 format)
	} field;
} REG_IGRGB2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens shading Control 0 register
// Offset: 0x4150
typedef union _REG_ISLS0
{
	UINT32 value;
	struct
	{
		UINT32 size                 : 2 ; // [1:0] LS grid size
		UINT32 mode                 : 2 ; // [3:2] LS grid mode
		UINT32 ege                  : 1 ; // [4] Elliptic Gating enable
	} field;
} REG_ISLS0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens Shading Grid Buffer Start Address Register, 64bit align
// Offset: 0x4154
typedef union _REG_ISLSGBA
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] 
		UINT32 sad                  : 29; // [31:3] Base address in QWORD (64bit) boundary, mv/mh [1.4.11]; p[0.13.4]
	} field;
} REG_ISLSGBA;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens Shading Grid Buffer Stride Register
// Offset: 0x4158
typedef union _REG_ISLSGBS
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 3 ; // [2:0] 
		UINT32 sd                   : 10; // [12:3] Image stride (QWORD granularity)
	} field;
} REG_ISLSGBS;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens Shading Eliptic Gating Center Register,CX/CY,each 13bits
// Offset: 0x415C
typedef union _REG_ISLSEGC
{
	UINT32 value;
	struct
	{
		UINT32 cy                   : 13; // [12:0] Center Y cooridnate
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 cx                   : 13; // [28:16] Center X cooridnate
	} field;
} REG_ISLSEGC;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens Shading Eliptic Gating Semi Axis X Register
// Offset: 0x4160
typedef union _REG_ISLSEGSX
{
	UINT32 value;
	struct
	{
		UINT32 sxf                  : 20; // [19:0] Semi Axis Factor X [0.-8.28]
	} field;
} REG_ISLSEGSX;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens Shading Eliptic Gating Semi Axis Y Register
// Offset: 0x4164
typedef union _REG_ISLSEGSY
{
	UINT32 value;
	struct
	{
		UINT32 sxy                  : 20; // [19:0] Semi Axis Factor Y [0.-8.28]
	} field;
} REG_ISLSEGSY;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens Shading Eliptic Gating Center Width Register
// Offset: 0x4168
typedef union _REG_ISLSEGW
{
	UINT32 value;
	struct
	{
		UINT32 tw                   : 13; // [12:0] Transition width (normalized) Format 0.1.12
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 twf                  : 13; // [28:16] Transition width factor (normalized) TWF = 1/(2*TW)  Format 0.11.2,
	} field;
} REG_ISLSEGW;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Lens Shading Memory Read Register, axi burst len , fifo threshold (remove id)
// Offset: 0x416C
typedef union _REG_ISLSMRD
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 8 ; // [7:0] 
		UINT32 thr                  : 6 ; // [13:8] AXI Read Request Threshold
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 len                  : 4 ; // [19:16] AXI Maximum length(zero based)
	} field;
} REG_ISLSMRD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR HO register, the offsets of the 1st local window from image top-left corner
// Offset: 0x4280
typedef union _REG_WDR_HOR
{
	UINT32 value;
	struct
	{
		UINT32 hox                  : 13; // [12:0] Horizontal offset, [0.13.0], must be set to even number
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 hoy                  : 13; // [28:16] Vertical offset, [0.13.0], must be set to even number
	} field;
} REG_WDR_HOR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR local window  register
// Offset: 0x4284
typedef union _REG_WDR_LWR
{
	UINT32 value;
	struct
	{
		UINT32 bwx                  : 4 ; // [3:0] local window width(2^BWx), range from 6 to 10
		UINT32 bwy                  : 4 ; // [7:4] local window height(2^BWy), range from 6 to 10
		UINT32 bux                  : 4 ; // [11:8] the distance between adjacent local windows in horizontal direction(2^BUx), range from 6 to 10
		UINT32 buy                  : 4 ; // [15:12] the distance between adjacent local windows in vertical direction(2^BUy), range from 6 to 10
		UINT32 n                    : 5 ; // [20:16] max window number in x direction
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 m                    : 5 ; // [28:24] max window number in y direction
	} field;
} REG_WDR_LWR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR level0 window threshold regiser
// Offset: 0x4288
typedef union _REG_WDR_THR0
{
	UINT32 value;
	struct
	{
		UINT32 tmin                 : 10; // [9:0] Flood threshold [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 tmax                 : 10; // [25:16] Trim threshold [0.10.0]
	} field;
} REG_WDR_THR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR scale regiser
// Offset: 0x428C
typedef union _REG_WDR_SCR
{
	UINT32 value;
	struct
	{
		UINT32 bsx                  : 3 ; // [2:0] window bin count scale down factor [0.3.0]
		UINT32 rsvd3                : 1 ; // [3] 
		UINT32 bsy                  : 3 ; // [6:4] window bin count scale down factor [0.3.0]
		UINT32 rsvd7                : 1 ; // [7] 
		UINT32 datfmt               : 1 ; // [8] local window data format in dram, 0 : compress mode, 6 bin count each 2W; 1: normal mode, one bin count two byte
		UINT32 l0sw_force           : 1 ; // [9] force use level 0 spatial weight only(debug only)
	} field;
} REG_WDR_SCR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR internal buffer0 address register
// Offset: 0x4290
typedef union _REG_WDR_IBADDR0
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 7 ; // [6:0] 
		UINT32 addr                 : 25; // [31:7] wdr internal buffer0 address(8x16byte align)
	} field;
} REG_WDR_IBADDR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR internal buffer1 address register
// Offset: 0x4294
typedef union _REG_WDR_IBADDR1
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 7 ; // [6:0] 
		UINT32 addr                 : 25; // [31:7] wdr internal buffer1 address(8x16byte align)
	} field;
} REG_WDR_IBADDR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR level1 window threshold regiser
// Offset: 0x4298
typedef union _REG_WDR_THR1
{
	UINT32 value;
	struct
	{
		UINT32 tmin                 : 10; // [9:0] Flood threshold [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 tmax                 : 10; // [25:16] Trim threshold [0.10.0]
	} field;
} REG_WDR_THR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR level2 window threshold regiser
// Offset: 0x429C
typedef union _REG_WDR_THR2
{
	UINT32 value;
	struct
	{
		UINT32 tmin                 : 10; // [9:0] Flood threshold [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 tmax                 : 10; // [25:16] Trim threshold [0.10.0]
	} field;
} REG_WDR_THR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR level3 window threshold regiser
// Offset: 0x42A0
typedef union _REG_WDR_THR3
{
	UINT32 value;
	struct
	{
		UINT32 tmin                 : 10; // [9:0] Flood threshold [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 tmax                 : 10; // [25:16] Trim threshold [0.10.0]
	} field;
} REG_WDR_THR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR spatial weight regiser
// Offset: 0x42A4
typedef union _REG_WDR_WSR
{
	UINT32 value;
	struct
	{
		UINT32 ws0                  : 5 ; // [4:0] level 0 window spatial weight [0.5.0]
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 ws1                  : 5 ; // [12:8] level 1 window spatial weight [0.5.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 ws2                  : 5 ; // [20:16] level 2 window spatial weight [0.5.0]
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 ws3                  : 5 ; // [28:24] level 3 window spatial weight [0.5.0]
	} field;
} REG_WDR_WSR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR variance table regiser
// Offset: 0x42A8
typedef union _REG_WDR_VR0
{
	UINT32 value;
	struct
	{
		UINT32 v0                   : 10; // [9:0] variance value [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 v1                   : 10; // [25:16] variance value [0.10.0]
	} field;
} REG_WDR_VR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR variance table regiser
// Offset: 0x42AC
typedef union _REG_WDR_VR1
{
	UINT32 value;
	struct
	{
		UINT32 v2                   : 10; // [9:0] variance value [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 v3                   : 10; // [25:16] variance value  [0.10.0]
	} field;
} REG_WDR_VR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR variance table regiser
// Offset: 0x42B0
typedef union _REG_WDR_VR2
{
	UINT32 value;
	struct
	{
		UINT32 v4                   : 10; // [9:0] variance value  [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 v5                   : 10; // [25:16] variance value  [0.10.0]
	} field;
} REG_WDR_VR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR variance table regiser
// Offset: 0x42B4
typedef union _REG_WDR_VR3
{
	UINT32 value;
	struct
	{
		UINT32 v6                   : 10; // [9:0] variance value  [0.10.0]
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 v7                   : 10; // [25:16] variance value  [0.10.0]
	} field;
} REG_WDR_VR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR intensity weight table regiser
// Offset: 0x42B8
typedef union _REG_WDR_WR0
{
	UINT32 value;
	struct
	{
		UINT32 w0                   : 5 ; // [4:0] intensity weight [0.5.0]
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 w1                   : 5 ; // [12:8] intensity weight [0.5.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 w2                   : 5 ; // [20:16] intensity weight [0.5.0]
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 w3                   : 5 ; // [28:24] intensity weight [0.5.0]
	} field;
} REG_WDR_WR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR intensity weight table regiser
// Offset: 0x42BC
typedef union _REG_WDR_WR1
{
	UINT32 value;
	struct
	{
		UINT32 w4                   : 5 ; // [4:0] intensity weight [0.5.0]
		UINT32 rsvd5                : 3 ; // [7:5] 
		UINT32 w5                   : 5 ; // [12:8] intensity weight [0.5.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 w6                   : 5 ; // [20:16] intensity weight [0.5.0]
		UINT32 rsvd21               : 3 ; // [23:21] 
		UINT32 w7                   : 5 ; // [28:24] intensity weight [0.5.0]
	} field;
} REG_WDR_WR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR intensity weigth slope regiser
// Offset: 0x42C0
typedef union _REG_WDR_SR0
{
	UINT32 value;
	struct
	{
		UINT32 s0                   : 11; // [10:0] intensity weigth slope  [1.0.10]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 s1                   : 11; // [26:16] intensity weigth slope  [1.0.10]
	} field;
} REG_WDR_SR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR intensity weigth slope regiser
// Offset: 0x42C4
typedef union _REG_WDR_SR1
{
	UINT32 value;
	struct
	{
		UINT32 s2                   : 11; // [10:0] intensity weigth slope  [1.0.10]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 s3                   : 11; // [26:16] intensity weigth slope  [1.0.10]
	} field;
} REG_WDR_SR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR intensity weigth slope regiser
// Offset: 0x42C8
typedef union _REG_WDR_SR2
{
	UINT32 value;
	struct
	{
		UINT32 s4                   : 11; // [10:0] intensity weigth slope  [1.0.10]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 s5                   : 11; // [26:16] intensity weigth slope  [1.0.10]
	} field;
} REG_WDR_SR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR intensity weigth slope regiser
// Offset: 0x42CC
typedef union _REG_WDR_SR3
{
	UINT32 value;
	struct
	{
		UINT32 s6                   : 11; // [10:0] intensity weigth slope  [1.0.10]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 s7                   : 11; // [26:16] intensity weigth slope  [1.0.10]
	} field;
} REG_WDR_SR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR L3 histogram sum factor register
// Offset: 0x42D0
typedef union _REG_WDR_L3HSR
{
	UINT32 value;
	struct
	{
		UINT32 factor               : 10; // [9:0] level 3 histogram sum factor [0.0.10]
	} field;
} REG_WDR_L3HSR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 0
// Offset: 0x433C
typedef union _REG_IGRVAL_15
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.[1.4.11]
	} field;
} REG_IGRVAL_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 1
// Offset: 0x4340
typedef union _REG_IGRVAL_16
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 2
// Offset: 0x4344
typedef union _REG_IGRVAL_17
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 3
// Offset: 0x4348
typedef union _REG_IGRVAL_18
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 4
// Offset: 0x434C
typedef union _REG_IGRVAL_19
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 5
// Offset: 0x4350
typedef union _REG_IGRVAL_20
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 6
// Offset: 0x4354
typedef union _REG_IGRVAL_21
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 7
// Offset: 0x4358
typedef union _REG_IGRVAL_22
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 8
// Offset: 0x435C
typedef union _REG_IGRVAL_23
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 9
// Offset: 0x4360
typedef union _REG_IGRVAL_24
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 10
// Offset: 0x4364
typedef union _REG_IGRVAL_25
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 11
// Offset: 0x4368
typedef union _REG_IGRVAL_26
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_26;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 12
// Offset: 0x436C
typedef union _REG_IGRVAL_27
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_27;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 13
// Offset: 0x4370
typedef union _REG_IGRVAL_28
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_28;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Forward Gamma table Register 14
// Offset: 0x4374
typedef union _REG_IGRVAL_29
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Forward gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Forward gamma slope value.
	} field;
} REG_IGRVAL_29;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 0
// Offset: 0x4378
typedef union _REG_IGRVAL_30
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.[1.4.11]
	} field;
} REG_IGRVAL_30;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 1
// Offset: 0x437C
typedef union _REG_IGRVAL_31
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_31;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 2
// Offset: 0x4380
typedef union _REG_IGRVAL_32
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_32;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 3
// Offset: 0x4384
typedef union _REG_IGRVAL_33
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_33;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 4
// Offset: 0x4388
typedef union _REG_IGRVAL_34
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_34;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 5
// Offset: 0x438C
typedef union _REG_IGRVAL_35
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_35;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 6
// Offset: 0x4390
typedef union _REG_IGRVAL_36
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_36;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 7
// Offset: 0x4394
typedef union _REG_IGRVAL_37
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_37;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 8
// Offset: 0x4398
typedef union _REG_IGRVAL_38
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_38;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 9
// Offset: 0x439C
typedef union _REG_IGRVAL_39
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_39;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 10
// Offset: 0x43A0
typedef union _REG_IGRVAL_40
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_40;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 11
// Offset: 0x43A4
typedef union _REG_IGRVAL_41
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_41;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 12
// Offset: 0x43A8
typedef union _REG_IGRVAL_42
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_42;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 13
// Offset: 0x43AC
typedef union _REG_IGRVAL_43
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_43;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Reserve Gamma table Register 14
// Offset: 0x43B0
typedef union _REG_IGRVAL_44
{
	UINT32 value;
	struct
	{
		UINT32 gval                 : 14; // [13:0] Reserve gamma value. [0.14/PW.0]
		UINT32 rsvd14               : 2 ; // [15:14] 
		UINT32 sgval                : 16; // [31:16] Reserve gamma slope value.
	} field;
} REG_IGRVAL_44;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 0
// Offset: 0x4400
typedef union _REG_IPF0_CB_0
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 0
// Offset: 0x4404
typedef union _REG_IPF0_CB_1
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 1
// Offset: 0x4408
typedef union _REG_IPF0_CB_2
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 1
// Offset: 0x440C
typedef union _REG_IPF0_CB_3
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 2
// Offset: 0x4410
typedef union _REG_IPF0_CB_4
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 2
// Offset: 0x4414
typedef union _REG_IPF0_CB_5
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 3
// Offset: 0x4418
typedef union _REG_IPF0_CB_6
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 3
// Offset: 0x441C
typedef union _REG_IPF0_CB_7
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 4
// Offset: 0x4420
typedef union _REG_IPF0_CB_8
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 4
// Offset: 0x4424
typedef union _REG_IPF0_CB_9
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 5
// Offset: 0x4428
typedef union _REG_IPF0_CB_10
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 5
// Offset: 0x442C
typedef union _REG_IPF0_CB_11
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 6
// Offset: 0x4430
typedef union _REG_IPF0_CB_12
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 6
// Offset: 0x4434
typedef union _REG_IPF0_CB_13
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 7
// Offset: 0x4438
typedef union _REG_IPF0_CB_14
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 7
// Offset: 0x443C
typedef union _REG_IPF0_CB_15
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 8
// Offset: 0x4440
typedef union _REG_IPF0_CB_16
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 8
// Offset: 0x4444
typedef union _REG_IPF0_CB_17
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 9
// Offset: 0x4448
typedef union _REG_IPF0_CB_18
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 9
// Offset: 0x444C
typedef union _REG_IPF0_CB_19
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 10
// Offset: 0x4450
typedef union _REG_IPF0_CB_20
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 10
// Offset: 0x4454
typedef union _REG_IPF0_CB_21
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 11
// Offset: 0x4458
typedef union _REG_IPF0_CB_22
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 11
// Offset: 0x445C
typedef union _REG_IPF0_CB_23
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 12
// Offset: 0x4460
typedef union _REG_IPF0_CB_24
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 32; // [31:0] COEFF_B[31:0]
	} field;
} REG_IPF0_CB_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 12
// Offset: 0x4464
typedef union _REG_IPF0_CB_25
{
	UINT32 value;
	struct
	{
		UINT32 coeff_b              : 10; // [9:0] COEFF_B[41:32]
	} field;
} REG_IPF0_CB_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 0
// Offset: 0x4468
typedef union _REG_IPF1_CRG_0
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG[31:0]
	} field;
} REG_IPF1_CRG_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 0
// Offset: 0x446C
typedef union _REG_IPF1_CRG_1
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG[41:32]
	} field;
} REG_IPF1_CRG_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 1
// Offset: 0x4470
typedef union _REG_IPF1_CRG_2
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG[31:0]
	} field;
} REG_IPF1_CRG_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 1
// Offset: 0x4474
typedef union _REG_IPF1_CRG_3
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG[41:32]
	} field;
} REG_IPF1_CRG_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 2
// Offset: 0x4478
typedef union _REG_IPF1_CRG_4
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG[31:0]
	} field;
} REG_IPF1_CRG_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 2
// Offset: 0x447C
typedef union _REG_IPF1_CRG_5
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 3
// Offset: 0x4480
typedef union _REG_IPF1_CRG_6
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 3
// Offset: 0x4484
typedef union _REG_IPF1_CRG_7
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 4
// Offset: 0x4488
typedef union _REG_IPF1_CRG_8
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 4
// Offset: 0x448C
typedef union _REG_IPF1_CRG_9
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 5
// Offset: 0x4490
typedef union _REG_IPF1_CRG_10
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 5
// Offset: 0x4494
typedef union _REG_IPF1_CRG_11
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 6
// Offset: 0x4498
typedef union _REG_IPF1_CRG_12
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 6
// Offset: 0x449C
typedef union _REG_IPF1_CRG_13
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 7
// Offset: 0x44A0
typedef union _REG_IPF1_CRG_14
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 7
// Offset: 0x44A4
typedef union _REG_IPF1_CRG_15
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 8
// Offset: 0x44A8
typedef union _REG_IPF1_CRG_16
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 8
// Offset: 0x44AC
typedef union _REG_IPF1_CRG_17
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 9
// Offset: 0x44B0
typedef union _REG_IPF1_CRG_18
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 9
// Offset: 0x44B4
typedef union _REG_IPF1_CRG_19
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 10
// Offset: 0x44B8
typedef union _REG_IPF1_CRG_20
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 10
// Offset: 0x44BC
typedef union _REG_IPF1_CRG_21
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 11
// Offset: 0x44C0
typedef union _REG_IPF1_CRG_22
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 11
// Offset: 0x44C4
typedef union _REG_IPF1_CRG_23
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 12
// Offset: 0x44C8
typedef union _REG_IPF1_CRG_24
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 32; // [31:0] COEFF_RG [31:0]
	} field;
} REG_IPF1_CRG_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 12
// Offset: 0x44CC
typedef union _REG_IPF1_CRG_25
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rg             : 10; // [9:0] COEFF_RG [41:32]
	} field;
} REG_IPF1_CRG_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4500
typedef union _REG_IPF2_F_0
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_0               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_0               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4504
typedef union _REG_IPF2_F_1
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_1               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_1               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4508
typedef union _REG_IPF2_F_2
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_2               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_2               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x450C
typedef union _REG_IPF2_F_3
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_3               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_3               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4510
typedef union _REG_IPF2_F_4
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_4               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_4               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4514
typedef union _REG_IPF2_F_5
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_5               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_5               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4518
typedef union _REG_IPF2_F_6
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_6               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_6               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x451C
typedef union _REG_IPF2_F_7
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_7               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_7               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4520
typedef union _REG_IPF2_F_8
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_8               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_8               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4524
typedef union _REG_IPF2_F_9
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_9               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_9               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4528
typedef union _REG_IPF2_F_10
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_10              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_10              : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x452C
typedef union _REG_IPF2_F_11
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_11              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_11              : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4530
typedef union _REG_IPF2_F_12
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_12              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f0_12              : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4534
typedef union _REG_IPF2_F_13
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_13              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_0               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4538
typedef union _REG_IPF2_F_14
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_14              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_1               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x453C
typedef union _REG_IPF2_F_15
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_15              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_2               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4540
typedef union _REG_IPF2_F_16
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_16              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_3               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4544
typedef union _REG_IPF2_F_17
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_17              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_4               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4548
typedef union _REG_IPF2_F_18
{
	UINT32 value;
	struct
	{
		UINT32 g_f0_18              : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_5               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x454C
typedef union _REG_IPF2_F_19
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_0               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_6               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4550
typedef union _REG_IPF2_F_20
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_1               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_7               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4554
typedef union _REG_IPF2_F_21
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_2               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_8               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4558
typedef union _REG_IPF2_F_22
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_3               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_9               : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x455C
typedef union _REG_IPF2_F_23
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_4               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_10              : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4560
typedef union _REG_IPF2_F_24
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_5               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_11              : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4564
typedef union _REG_IPF2_F_25
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_6               : 16; // [15:0] PF correction Green filter value.
		UINT32 r_f1_12              : 16; // [31:16] PF correction Red filter value.
	} field;
} REG_IPF2_F_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4568
typedef union _REG_IPF2_F_26
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_7               : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_0               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_26;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x456C
typedef union _REG_IPF2_F_27
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_8               : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_1               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_27;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4570
typedef union _REG_IPF2_F_28
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_9               : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_2               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_28;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4574
typedef union _REG_IPF2_F_29
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_10              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_3               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_29;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4578
typedef union _REG_IPF2_F_30
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_11              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_4               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_30;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x457C
typedef union _REG_IPF2_F_31
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_12              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_5               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_31;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4580
typedef union _REG_IPF2_F_32
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_13              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_6               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_32;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4584
typedef union _REG_IPF2_F_33
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_14              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_7               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_33;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4588
typedef union _REG_IPF2_F_34
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_15              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_8               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_34;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x458C
typedef union _REG_IPF2_F_35
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_16              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_9               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_35;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4590
typedef union _REG_IPF2_F_36
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_17              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_10              : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_36;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4594
typedef union _REG_IPF2_F_37
{
	UINT32 value;
	struct
	{
		UINT32 g_f1_18              : 16; // [15:0] PF correction Green filter value.
		UINT32 b_f0_11              : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_37;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x4598
typedef union _REG_IPF2_F_38
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f0_12              : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_38;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x459C
typedef union _REG_IPF2_F_39
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_0               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_39;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45A0
typedef union _REG_IPF2_F_40
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_1               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_40;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45A4
typedef union _REG_IPF2_F_41
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_2               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_41;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45A8
typedef union _REG_IPF2_F_42
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_3               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_42;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45AC
typedef union _REG_IPF2_F_43
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_4               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_43;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45B0
typedef union _REG_IPF2_F_44
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_5               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_44;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45B4
typedef union _REG_IPF2_F_45
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_6               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_45;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45B8
typedef union _REG_IPF2_F_46
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_7               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_46;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45BC
typedef union _REG_IPF2_F_47
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_8               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_47;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45C0
typedef union _REG_IPF2_F_48
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_9               : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_48;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45C4
typedef union _REG_IPF2_F_49
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_10              : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_49;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45C8
typedef union _REG_IPF2_F_50
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_11              : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_50;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 
// Offset: 0x45CC
typedef union _REG_IPF2_F_51
{
	UINT32 value;
	struct
	{
		UINT32 rsvd0                : 16; // [15:0] 
		UINT32 b_f1_12              : 16; // [31:16] PF correction Blue filter value.
	} field;
} REG_IPF2_F_51;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Purple Fringing Correction Register 3
// Offset: 0x45D0
typedef union _REG_IPF3_RG_MD
{
	UINT32 value;
	struct
	{
		UINT32 rg_md                : 2 ; // [1:0] PF correction Red Green mode
		UINT32 rsvd2                : 30; // [31:2] 
	} field;
} REG_IPF3_RG_MD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x4600
typedef union _REG_ICA0_CRGX_0
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x4604
typedef union _REG_ICA0_CRGX_1
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x4608
typedef union _REG_ICA0_CRGX_2
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x460C
typedef union _REG_ICA0_CRGX_3
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x4610
typedef union _REG_ICA0_CRGX_4
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x4614
typedef union _REG_ICA0_CRGX_5
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x4618
typedef union _REG_ICA0_CRGX_6
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x461C
typedef union _REG_ICA0_CRGX_7
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x4620
typedef union _REG_ICA0_CRGX_8
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x4624
typedef union _REG_ICA0_CRGX_9
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x4628
typedef union _REG_ICA0_CRGX_10
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x462C
typedef union _REG_ICA0_CRGX_11
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x4630
typedef union _REG_ICA0_CRGX_12
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x4634
typedef union _REG_ICA0_CRGX_13
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x4638
typedef union _REG_ICA0_CRGX_14
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x463C
typedef union _REG_ICA0_CRGX_15
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x4640
typedef union _REG_ICA0_CRGX_16
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x4644
typedef union _REG_ICA0_CRGX_17
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x4648
typedef union _REG_ICA0_CRGX_18
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x464C
typedef union _REG_ICA0_CRGX_19
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x4650
typedef union _REG_ICA0_CRGX_20
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x4654
typedef union _REG_ICA0_CRGX_21
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x4658
typedef union _REG_ICA0_CRGX_22
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x465C
typedef union _REG_ICA0_CRGX_23
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x4660
typedef union _REG_ICA0_CRGX_24
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[31:0]
	} field;
} REG_ICA0_CRGX_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x4664
typedef union _REG_ICA0_CRGX_25
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgx            : 32; // [31:0] COEFF_RGX[63:32]
	} field;
} REG_ICA0_CRGX_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x4668
typedef union _REG_ICA1_CRGY_0
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x466C
typedef union _REG_ICA1_CRGY_1
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x4670
typedef union _REG_ICA1_CRGY_2
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x4674
typedef union _REG_ICA1_CRGY_3
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x4678
typedef union _REG_ICA1_CRGY_4
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x467C
typedef union _REG_ICA1_CRGY_5
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x4680
typedef union _REG_ICA1_CRGY_6
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x4684
typedef union _REG_ICA1_CRGY_7
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x4688
typedef union _REG_ICA1_CRGY_8
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x468C
typedef union _REG_ICA1_CRGY_9
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x4690
typedef union _REG_ICA1_CRGY_10
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x4694
typedef union _REG_ICA1_CRGY_11
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x4698
typedef union _REG_ICA1_CRGY_12
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x469C
typedef union _REG_ICA1_CRGY_13
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x46A0
typedef union _REG_ICA1_CRGY_14
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x46A4
typedef union _REG_ICA1_CRGY_15
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x46A8
typedef union _REG_ICA1_CRGY_16
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x46AC
typedef union _REG_ICA1_CRGY_17
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x46B0
typedef union _REG_ICA1_CRGY_18
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x46B4
typedef union _REG_ICA1_CRGY_19
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x46B8
typedef union _REG_ICA1_CRGY_20
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x46BC
typedef union _REG_ICA1_CRGY_21
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x46C0
typedef union _REG_ICA1_CRGY_22
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x46C4
typedef union _REG_ICA1_CRGY_23
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x46C8
typedef union _REG_ICA1_CRGY_24
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[31:0]
	} field;
} REG_ICA1_CRGY_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x46CC
typedef union _REG_ICA1_CRGY_25
{
	UINT32 value;
	struct
	{
		UINT32 coeff_rgy            : 32; // [31:0] COEFF_RGY[63:32]
	} field;
} REG_ICA1_CRGY_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x4700
typedef union _REG_ICA2_CBGX_0
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x4704
typedef union _REG_ICA2_CBGX_1
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x4708
typedef union _REG_ICA2_CBGX_2
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x470C
typedef union _REG_ICA2_CBGX_3
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x4710
typedef union _REG_ICA2_CBGX_4
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x4714
typedef union _REG_ICA2_CBGX_5
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x4718
typedef union _REG_ICA2_CBGX_6
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x471C
typedef union _REG_ICA2_CBGX_7
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x4720
typedef union _REG_ICA2_CBGX_8
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x4724
typedef union _REG_ICA2_CBGX_9
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x4728
typedef union _REG_ICA2_CBGX_10
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x472C
typedef union _REG_ICA2_CBGX_11
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x4730
typedef union _REG_ICA2_CBGX_12
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x4734
typedef union _REG_ICA2_CBGX_13
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x4738
typedef union _REG_ICA2_CBGX_14
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x473C
typedef union _REG_ICA2_CBGX_15
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x4740
typedef union _REG_ICA2_CBGX_16
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x4744
typedef union _REG_ICA2_CBGX_17
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x4748
typedef union _REG_ICA2_CBGX_18
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x474C
typedef union _REG_ICA2_CBGX_19
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x4750
typedef union _REG_ICA2_CBGX_20
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x4754
typedef union _REG_ICA2_CBGX_21
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x4758
typedef union _REG_ICA2_CBGX_22
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x475C
typedef union _REG_ICA2_CBGX_23
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x4760
typedef union _REG_ICA2_CBGX_24
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[31:0]
	} field;
} REG_ICA2_CBGX_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x4764
typedef union _REG_ICA2_CBGX_25
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgx            : 32; // [31:0] COEFF_BGX[63:32]
	} field;
} REG_ICA2_CBGX_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x4768
typedef union _REG_ICA3_CBGY_0
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 0
// Offset: 0x476C
typedef union _REG_ICA3_CBGY_1
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x4770
typedef union _REG_ICA3_CBGY_2
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 1
// Offset: 0x4774
typedef union _REG_ICA3_CBGY_3
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x4778
typedef union _REG_ICA3_CBGY_4
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 2
// Offset: 0x477C
typedef union _REG_ICA3_CBGY_5
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x4780
typedef union _REG_ICA3_CBGY_6
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 3
// Offset: 0x4784
typedef union _REG_ICA3_CBGY_7
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x4788
typedef union _REG_ICA3_CBGY_8
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 4
// Offset: 0x478C
typedef union _REG_ICA3_CBGY_9
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x4790
typedef union _REG_ICA3_CBGY_10
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 5
// Offset: 0x4794
typedef union _REG_ICA3_CBGY_11
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x4798
typedef union _REG_ICA3_CBGY_12
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 6
// Offset: 0x479C
typedef union _REG_ICA3_CBGY_13
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x47A0
typedef union _REG_ICA3_CBGY_14
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 7
// Offset: 0x47A4
typedef union _REG_ICA3_CBGY_15
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x47A8
typedef union _REG_ICA3_CBGY_16
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 8
// Offset: 0x47AC
typedef union _REG_ICA3_CBGY_17
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x47B0
typedef union _REG_ICA3_CBGY_18
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 9
// Offset: 0x47B4
typedef union _REG_ICA3_CBGY_19
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x47B8
typedef union _REG_ICA3_CBGY_20
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 10
// Offset: 0x47BC
typedef union _REG_ICA3_CBGY_21
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x47C0
typedef union _REG_ICA3_CBGY_22
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 11
// Offset: 0x47C4
typedef union _REG_ICA3_CBGY_23
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x47C8
typedef union _REG_ICA3_CBGY_24
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[31:0]
	} field;
} REG_ICA3_CBGY_24;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Chromatic Aberration Correction Register 12
// Offset: 0x47CC
typedef union _REG_ICA3_CBGY_25
{
	UINT32 value;
	struct
	{
		UINT32 coeff_bgy            : 32; // [31:0] COEFF_BGY[63:32]
	} field;
} REG_ICA3_CBGY_25;

////////////////////////////////////////////////////////////////////////////////////////////////////
// x coordinates for luminance regiser 0
// Offset: 0x4868
typedef union _REG_ICAMD_XL_CFG0
{
	UINT32 value;
	struct
	{
		UINT32 xl0                  : 10; // [9:0] x coordinates for luminance [0.10.0]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 xl1                  : 10; // [25:16] x coordinates for luminance [0.10.0]
	} field;
} REG_ICAMD_XL_CFG0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// x coordinates for luminance regiser 1
// Offset: 0x486C
typedef union _REG_ICAMD_XL_CFG1
{
	UINT32 value;
	struct
	{
		UINT32 xl2                  : 10; // [9:0] x coordinates for luminance [0.10.0]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 xl3                  : 10; // [25:16] x coordinates for luminance [0.10.0]
	} field;
} REG_ICAMD_XL_CFG1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// f coordinates for luminance regiser 0
// Offset: 0x4870
typedef union _REG_ICAMD_FL_CFG0
{
	UINT32 value;
	struct
	{
		UINT32 fl0                  : 10; // [9:0] x coordinates for luminance [0.3.7]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 fl1                  : 10; // [25:16] x coordinates for luminance [0.3.7]
	} field;
} REG_ICAMD_FL_CFG0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// f coordinates for luminance regiser 1
// Offset: 0x4874
typedef union _REG_ICAMD_FL_CFG1
{
	UINT32 value;
	struct
	{
		UINT32 fl2                  : 10; // [9:0] x coordinates for luminance [0.3.7]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 fl3                  : 10; // [25:16] x coordinates for luminance [0.3.7]
	} field;
} REG_ICAMD_FL_CFG1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// s (slope) for luminance regiser 0
// Offset: 0x4878
typedef union _REG_ICAMD_SL_CFG0
{
	UINT32 value;
	struct
	{
		UINT32 sl0                  : 16; // [15:0] x coordinates for luminance [1.3.12]
		UINT32 sl1                  : 16; // [31:16] x coordinates for luminance [1.3.12]
	} field;
} REG_ICAMD_SL_CFG0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// s (slope) for luminance regiser 1
// Offset: 0x487C
typedef union _REG_ICAMD_SL_CFG1
{
	UINT32 value;
	struct
	{
		UINT32 sl2                  : 16; // [15:0] x coordinates for luminance [1.3.12]
		UINT32 sl3                  : 16; // [31:16] x coordinates for luminance [1.3.12]
	} field;
} REG_ICAMD_SL_CFG1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// x coordinates for color saturation regiser 0
// Offset: 0x4880
typedef union _REG_ICAMD_XS_CFG0
{
	UINT32 value;
	struct
	{
		UINT32 xl0                  : 10; // [9:0] x coordinates for color saturation [0.10.0]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 xl1                  : 10; // [25:16] x coordinates for color saturation [0.10.0]
	} field;
} REG_ICAMD_XS_CFG0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// x coordinates for color saturation regiser 1
// Offset: 0x4884
typedef union _REG_ICAMD_XS_CFG1
{
	UINT32 value;
	struct
	{
		UINT32 xl2                  : 10; // [9:0] x coordinates for color saturation [0.10.0]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 xl3                  : 10; // [25:16] x coordinates for color saturation [0.10.0]
	} field;
} REG_ICAMD_XS_CFG1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// f coordinates for color saturation regiser 0
// Offset: 0x4888
typedef union _REG_ICAMD_FS_CFG0
{
	UINT32 value;
	struct
	{
		UINT32 fl0                  : 10; // [9:0] x coordinates for color saturation [0.3.7]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 fl1                  : 10; // [25:16] x coordinates for color saturation [0.3.7]
	} field;
} REG_ICAMD_FS_CFG0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// f coordinates for color saturation regiser 1
// Offset: 0x488C
typedef union _REG_ICAMD_FS_CFG1
{
	UINT32 value;
	struct
	{
		UINT32 fl2                  : 10; // [9:0] x coordinates for color saturation [0.3.7]
		UINT32 rsvd                 : 6 ; // [15:10] 
		UINT32 fl3                  : 10; // [25:16] x coordinates for color saturation [0.3.7]
	} field;
} REG_ICAMD_FS_CFG1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// s (slope) for color saturation regiser 0
// Offset: 0x4890
typedef union _REG_ICAMD_SS_CFG0
{
	UINT32 value;
	struct
	{
		UINT32 sl0                  : 16; // [15:0] x coordinates for color saturation [1.3.12]
		UINT32 sl1                  : 16; // [31:16] x coordinates for color saturation [1.3.12]
	} field;
} REG_ICAMD_SS_CFG0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// s (slope) for color saturation regiser 1
// Offset: 0x4894
typedef union _REG_ICAMD_SS_CFG1
{
	UINT32 value;
	struct
	{
		UINT32 sl2                  : 16; // [15:0] x coordinates for color saturation [1.3.12]
		UINT32 sl3                  : 16; // [31:16] x coordinates for color saturation [1.3.12]
	} field;
} REG_ICAMD_SS_CFG1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen Wsum 2nd set register
// Offset: 0x4A6C
typedef union _REG_ISHRPWS2
{
	UINT32 value;
	struct
	{
		UINT32 wsum2                : 22; // [21:0] Amplification filter weight normalization factor 2nd set
	} field;
} REG_ISHRPWS2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen UV Threshold
// Offset: 0x4A70
typedef union _REG_ISHRPUVSMT
{
	UINT32 value;
	struct
	{
		UINT32 uv_sm_t              : 10; // [9:0] uv threshold [0.10.0]
	} field;
} REG_ISHRPUVSMT;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen LPF Buffer 0 Register, 64bit align
// Offset: 0x4A74
typedef union _REG_ISFRPBUF0
{
	UINT32 value;
	struct
	{
		UINT32 wbstm                : 2 ; // [1:0] shrp axi write burst length mode, 0: burst 16, 1: burst 8, 2: burst 4
		UINT32 reserved             : 1 ; // [2] 
		UINT32 bufaddr              : 29; // [31:3] LPF buffer address (8-byte Alignment)
	} field;
} REG_ISFRPBUF0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen LPF Buffer 1 Register, 64bit align
// Offset: 0x4A78
typedef union _REG_ISFRPBUF1
{
	UINT32 value;
	struct
	{
		UINT32 rbstm                : 2 ; // [1:0] shrp read axi outstanding mode, 0 : 4*1*8*64, 1: 2*2*8*64, 2: 1*4*8*64
		UINT32 reserved             : 1 ; // [2] 
		UINT32 bufaddr              : 29; // [31:3] LPF buffer address (8-byte Alignment)
	} field;
} REG_ISFRPBUF1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Sharpen LPF Buffer Status Register
// Offset: 0x4A7C
typedef union _REG_ISFRPBUFST
{
	UINT32 value;
	struct
	{
		UINT32 bufst                : 1 ; // [0] LPF write buffer status
	} field;
} REG_ISFRPBUFST;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OBC shadow register update enable register
// Offset: 0x4B00
typedef union _REG_OBC_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_OBC_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL3D shadow register update enable register
// Offset: 0x4B04
typedef union _REG_NL3D_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_NL3D_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NL2D shadow register update enable register
// Offset: 0x4B08
typedef union _REG_NL2D_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_NL2D_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// GRGB shadow register update enable register
// Offset: 0x4B0C
typedef union _REG_GRGB_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_GRGB_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// AWB shadow register update enable register
// Offset: 0x4B10
typedef union _REG_AWB_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_AWB_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// CCM shadow register update enable register
// Offset: 0x4B14
typedef union _REG_CCM_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_CCM_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// LUT shadow register update enable register
// Offset: 0x4B18
typedef union _REG_LUT_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_LUT_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// GAMRGB shadow register update enable register
// Offset: 0x4B1C
typedef union _REG_GAMRGB_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_GAMRGB_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// R2Y shadow register update enable register
// Offset: 0x4B20
typedef union _REG_R2Y_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_R2Y_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// YCUR shadow register update enable register
// Offset: 0x4B24
typedef union _REG_YCUR_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_YCUR_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// NWED shadow register update enable register
// Offset: 0x4B28
typedef union _REG_NWED_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_NWED_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SHRP shadow register update enable register
// Offset: 0x4B2C
typedef union _REG_SHRP_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_SHRP_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SAT shadow register update enable register
// Offset: 0x4B30
typedef union _REG_SAT_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_SAT_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC0 shadow register update enable register
// Offset: 0x4B34
typedef union _REG_SC0_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_SC0_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// SC1 shadow register update enable register
// Offset: 0x4B38
typedef union _REG_SC1_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_SC1_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// YHIST shadow register update enable register
// Offset: 0x4B3C
typedef union _REG_YHIST_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_YHIST_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Tiling shadow register update enable register
// Offset: 0x4B40
typedef union _REG_ITI_SUD
{
	UINT32 value;
	struct
	{
		UINT32 iti_read_shadow_md   : 1 ; // [0] tiling read  enable  shadow, active high.
		UINT32 iti_write0_shadow_md : 1 ; // [1] tiling write0  enable  shadow, active high.
		UINT32 iti_write1_shadow_md : 1 ; // [2] tiling write1  enable shadow, active high.
		UINT32 iti_write0_crop_ud   : 1 ; // [3] tiling write0 crop register update enable, active high.
		UINT32 iti_write1_crop_ud   : 1 ; // [4] tiling write1 crop register update enable, active high.
	} field;
} REG_ITI_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// WDR shadow register update enable register
// Offset: 0x4B44
typedef union _REG_WDR_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_WDR_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BIYUV shadow register update enable register
// Offset: 0x4B48
typedef union _REG_BIYUV_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_BIYUV_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// CTM shadow register update enable register
// Offset: 0x4B4C
typedef union _REG_CTM_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_CTM_SUD;

////////////////////////////////////////////////////////////////////////////////////////////////////
// OECF shadow register update enable register
// Offset: 0x4B50
typedef union _REG_OECF_SUD
{
	UINT32 value;
	struct
	{
		UINT32 shadow_ud            : 1 ; // [0] shadow register update enable, active high.
	} field;
} REG_OECF_SUD;

#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
// RDMA enable register
// Offset: 0x4C00
typedef union _REG_RDMA_ENR
{
	UINT32 value;
	struct
	{
		UINT32 rdma_en              : 1 ; // [0] rdma enable, active high, internal check rise edge for rdma_en for rdma start
	} field;
} REG_RDMA_ENR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RDMA Software sint ack register
// Offset: 0x4C04
typedef union _REG_RDMA_SACKR
{
	UINT32 value;
	struct
	{
		UINT32 sack                 : 1 ; // [0] when RDMA descriptor include DESP_SINT with flag[1] set to high, need write this register, then rdma will execute next line descriptor.
	} field;
} REG_RDMA_SACKR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RDMA Descriptor Start Addresse register
// Offset: 0x4C08
typedef union _REG_RDMA_DADDR
{
	UINT32 value;
	struct
	{
		UINT32 desp_baddr           : 32; // [31:0] RDMA Descriptor Start Addresse register(8 byte align, low 3bit always set to 0)
	} field;
} REG_RDMA_DADDR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RDMA Descriptor Current Addresse register
// Offset: 0x4C0C
typedef union _REG_RDMA_CADDR
{
	UINT32 value;
	struct
	{
		UINT32 desp_caddr           : 32; // [31:0] RDMA Descriptor current address
	} field;
} REG_RDMA_CADDR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// RDMA Status Register
// Offset: 0x4C10
typedef union _REG_RDMA_STSR
{
	UINT32 value;
	struct
	{
		UINT32 desp_fsm             : 4 ; // [3:0] internal fsm state
		UINT32 desp_eint            : 1 ; // [4] rdma finish flag(read only)
		UINT32 desp_sint            : 1 ; // [5] rdma software interrupt flag(read only)
	} field;
} REG_RDMA_STSR;

#if 0
////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y channel S weight table register 0
// Offset: 0x4D00
typedef union _REG_BIYUV_YSWR0
{
	UINT32 value;
	struct
	{
		UINT32 yswa                 : 4 ; // [3:0] [0.4.0], y channel Sa
		UINT32 yswb                 : 4 ; // [7:4] [0.4.0], y channel Sb
		UINT32 yswc                 : 4 ; // [11:8] [0.4.0], y channel Sc
		UINT32 yswd                 : 4 ; // [15:12] [0.4.0], y channel Sd
		UINT32 yswe                 : 4 ; // [19:16] [0.4.0], y channel Se
		UINT32 yswf                 : 4 ; // [23:20] [0.4.0], y channel Sf
		UINT32 rsvd24               : 8 ; // [31:24] 
	} field;
} REG_BIYUV_YSWR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y channel S weight table register 1
// Offset: 0x4D04
typedef union _REG_BIYUV_YSWR1
{
	UINT32 value;
	struct
	{
		UINT32 yswg                 : 4 ; // [3:0] [0.4.0], y channel Sg
		UINT32 yswh                 : 4 ; // [7:4] [0.4.0], y channel Sh
		UINT32 yswi                 : 4 ; // [11:8] [0.4.0], y channel Si
		UINT32 yswj                 : 4 ; // [15:12] [0.4.0], y channel Sj
	} field;
} REG_BIYUV_YSWR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV channel S weight table register 0
// Offset: 0x4D08
typedef union _REG_BIYUV_UVSWR0
{
	UINT32 value;
	struct
	{
		UINT32 uvswa                : 4 ; // [3:0] [0.4.0], uv channel Sa
		UINT32 uvswb                : 4 ; // [7:4] [0.4.0], uv channel Sb
		UINT32 uvswc                : 4 ; // [11:8] [0.4.0], uv channel Sc
		UINT32 uvswd                : 4 ; // [15:12] [0.4.0], uv channel Sd
		UINT32 uvswe                : 4 ; // [19:16] [0.4.0], uv channel Se
		UINT32 uvswf                : 4 ; // [23:20] [0.4.0], uv channel Sf
		UINT32 rsvd24               : 8 ; // [31:24] 
	} field;
} REG_BIYUV_UVSWR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV channel S weight table register  1
// Offset: 0x4D0C
typedef union _REG_BIYUV_UVSWR1
{
	UINT32 value;
	struct
	{
		UINT32 uvswg                : 4 ; // [3:0] [0.4.0], uv channel Sg
		UINT32 uvswh                : 4 ; // [7:4] [0.4.0], uv channel Sh
		UINT32 uvswi                : 4 ; // [11:8] [0.4.0], uv channel Si
		UINT32 uvswj                : 4 ; // [15:12] [0.4.0], uv channel Sj
	} field;
} REG_BIYUV_UVSWR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve I component register
// Offset: 0x4D10
typedef union _REG_BIYUV_YCIR
{
	UINT32 value;
	struct
	{
		UINT32 yci0                 : 4 ; // [3:0] [0.4.0], Curve I components for Y
		UINT32 yci1                 : 4 ; // [7:4] [0.4.0], Curve I components for Y
		UINT32 yci2                 : 4 ; // [11:8] [0.4.0], Curve I components for Y
		UINT32 yci3                 : 4 ; // [15:12] [0.4.0], Curve I components for Y
		UINT32 yci4                 : 4 ; // [19:16] [0.4.0], Curve I components for Y
		UINT32 yci5                 : 4 ; // [23:20] [0.4.0], Curve I components for Y
		UINT32 yci6                 : 4 ; // [27:24] [0.4.0], Curve I components forY
		UINT32 yci7                 : 4 ; // [31:28] [0.4.0], Curve I components for Y
	} field;
} REG_BIYUV_YCIR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve I component register
// Offset: 0x4D14
typedef union _REG_BIYUV_UVCIR
{
	UINT32 value;
	struct
	{
		UINT32 uvci0                : 4 ; // [3:0] [0.4.0], Curve I components for UV
		UINT32 uvci1                : 4 ; // [7:4] [0.4.0], Curve I components for UV
		UINT32 uvci2                : 4 ; // [11:8] [0.4.0], Curve I components for UV
		UINT32 uvci3                : 4 ; // [15:12] [0.4.0], Curve I components for UV
		UINT32 uvci4                : 4 ; // [19:16] [0.4.0], Curve I components for UV
		UINT32 uvci5                : 4 ; // [23:20] [0.4.0], Curve I components for UV
		UINT32 uvci6                : 4 ; // [27:24] [0.4.0], Curve I components for UV
		UINT32 uvci7                : 4 ; // [31:28] [0.4.0], Curve I components for UV
	} field;
} REG_BIYUV_UVCIR;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve D component register 0
// Offset: 0x4D18
typedef union _REG_BIYUV_YCDR0
{
	UINT32 value;
	struct
	{
		UINT32 ycd0                 : 10; // [9:0] [0.10.0], Curve D components for Y
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ycd1                 : 10; // [25:16] [0.10.0], Curve D components for Y
	} field;
} REG_BIYUV_YCDR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve D component register 1
// Offset: 0x4D1C
typedef union _REG_BIYUV_YCDR1
{
	UINT32 value;
	struct
	{
		UINT32 ycd2                 : 10; // [9:0] [0.10.0], Curve D components for Y
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ycd3                 : 10; // [25:16] [0.10.0], Curve D components for Y
	} field;
} REG_BIYUV_YCDR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve D component register 2
// Offset: 0x4D20
typedef union _REG_BIYUV_YCDR2
{
	UINT32 value;
	struct
	{
		UINT32 ycd4                 : 10; // [9:0] [0.10.0], Curve D components for Y
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ycd5                 : 10; // [25:16] [0.10.0], Curve D components for Y
	} field;
} REG_BIYUV_YCDR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve D component register 3
// Offset: 0x4D24
typedef union _REG_BIYUV_YCDR3
{
	UINT32 value;
	struct
	{
		UINT32 ycd6                 : 10; // [9:0] [0.10.0], Curve D components for Y
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 ycd7                 : 10; // [25:16] [0.10.0], Curve D components for Y
	} field;
} REG_BIYUV_YCDR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve D component register 0
// Offset: 0x4D28
typedef union _REG_BIYUV_UVCDR0
{
	UINT32 value;
	struct
	{
		UINT32 uvcd0                : 10; // [9:0] [0.10.0], Curve D components for UV
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvcd1                : 10; // [25:16] [0.10.0], Curve D components for UV
	} field;
} REG_BIYUV_UVCDR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve D component register 1
// Offset: 0x4D2C
typedef union _REG_BIYUV_UVCDR1
{
	UINT32 value;
	struct
	{
		UINT32 uvcd2                : 10; // [9:0] [0.10.0], Curve D components for UV
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvcd3                : 10; // [25:16] [0.10.0], Curve D components for UV
	} field;
} REG_BIYUV_UVCDR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve D component register 2
// Offset: 0x4D30
typedef union _REG_BIYUV_UVCDR2
{
	UINT32 value;
	struct
	{
		UINT32 uvcd4                : 10; // [9:0] [0.10.0], Curve D components for UV
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvcd5                : 10; // [25:16] [0.10.0], Curve D components for UV
	} field;
} REG_BIYUV_UVCDR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve D component register 3
// Offset: 0x4D34
typedef union _REG_BIYUV_UVCDR3
{
	UINT32 value;
	struct
	{
		UINT32 uvcd6                : 10; // [9:0] [0.10.0], Curve D components for UV
		UINT32 rsvd10               : 6 ; // [15:10] 
		UINT32 uvcd7                : 10; // [25:16] [0.10.0], Curve D components for UV
	} field;
} REG_BIYUV_UVCDR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve S component register 0
// Offset: 0x4D38
typedef union _REG_BIYUV_YCSR0
{
	UINT32 value;
	struct
	{
		UINT32 ycs0                 : 13; // [12:0] [1.4.8], Curve S components for Y
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 ycs1                 : 13; // [28:16] [1.4.8], Curve S components for Y
	} field;
} REG_BIYUV_YCSR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve S component register 1
// Offset: 0x4D3C
typedef union _REG_BIYUV_YCSR1
{
	UINT32 value;
	struct
	{
		UINT32 ycs2                 : 13; // [12:0] [1.4.8], Curve S components for Y
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 ycs3                 : 13; // [28:16] [1.4.8], Curve S components for Y
	} field;
} REG_BIYUV_YCSR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve S component register 2
// Offset: 0x4D40
typedef union _REG_BIYUV_YCSR2
{
	UINT32 value;
	struct
	{
		UINT32 ycs4                 : 13; // [12:0] [1.4.8], Curve S components for Y
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 ycs5                 : 13; // [28:16] [1.4.8], Curve S components for Y
	} field;
} REG_BIYUV_YCSR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV Y Curve S component register 3
// Offset: 0x4D44
typedef union _REG_BIYUV_YCSR3
{
	UINT32 value;
	struct
	{
		UINT32 ycs6                 : 13; // [12:0] [1.4.8], Curve S components for Y
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 ycs7                 : 13; // [28:16] [1.4.8], Curve S components for Y
	} field;
} REG_BIYUV_YCSR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve S component register 0
// Offset: 0x4D48
typedef union _REG_BIYUV_UVCSR0
{
	UINT32 value;
	struct
	{
		UINT32 uvcs0                : 13; // [12:0] [1.4.8], Curve S components for UV
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvcs1                : 13; // [28:16] [1.4.8], Curve S components for UV
	} field;
} REG_BIYUV_UVCSR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve S component register 1
// Offset: 0x4D4C
typedef union _REG_BIYUV_UVCSR1
{
	UINT32 value;
	struct
	{
		UINT32 uvcs2                : 13; // [12:0] [1.4.8], Curve S components for UV
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvcs3                : 13; // [28:16] [1.4.8], Curve S components for UV
	} field;
} REG_BIYUV_UVCSR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve S component register 2
// Offset: 0x4D50
typedef union _REG_BIYUV_UVCSR2
{
	UINT32 value;
	struct
	{
		UINT32 uvcs4                : 13; // [12:0] [1.4.8], Curve S components for UV
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvcs5                : 13; // [28:16] [1.4.8], Curve S components for UV
	} field;
} REG_BIYUV_UVCSR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// BiYUV UV Curve S component register 3
// Offset: 0x4D54
typedef union _REG_BIYUV_UVCSR3
{
	UINT32 value;
	struct
	{
		UINT32 uvcs6                : 13; // [12:0] [1.4.8], Curve S components for UV
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 uvcs7                : 13; // [28:16] [1.4.8], Curve S components for UV
	} field;
} REG_BIYUV_UVCSR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E00
typedef union _REG_CTM_HR0
{
	UINT32 value;
	struct
	{
		UINT32 h0                   : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h1                   : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E04
typedef union _REG_CTM_HR1
{
	UINT32 value;
	struct
	{
		UINT32 h2                   : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h3                   : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E08
typedef union _REG_CTM_HR2
{
	UINT32 value;
	struct
	{
		UINT32 h4                   : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h5                   : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E0C
typedef union _REG_CTM_HR3
{
	UINT32 value;
	struct
	{
		UINT32 h6                   : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h7                   : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E10
typedef union _REG_CTM_HR4
{
	UINT32 value;
	struct
	{
		UINT32 h8                   : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h9                   : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E14
typedef union _REG_CTM_HR5
{
	UINT32 value;
	struct
	{
		UINT32 h10                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h11                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E18
typedef union _REG_CTM_HR6
{
	UINT32 value;
	struct
	{
		UINT32 h12                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h13                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E1C
typedef union _REG_CTM_HR7
{
	UINT32 value;
	struct
	{
		UINT32 h14                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h15                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E20
typedef union _REG_CTM_HR8
{
	UINT32 value;
	struct
	{
		UINT32 h16                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h17                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E24
typedef union _REG_CTM_HR9
{
	UINT32 value;
	struct
	{
		UINT32 h18                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h19                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E28
typedef union _REG_CTM_HR10
{
	UINT32 value;
	struct
	{
		UINT32 h20                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h21                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E2C
typedef union _REG_CTM_HR11
{
	UINT32 value;
	struct
	{
		UINT32 h22                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h23                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E30
typedef union _REG_CTM_HR12
{
	UINT32 value;
	struct
	{
		UINT32 h24                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h25                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E34
typedef union _REG_CTM_HR13
{
	UINT32 value;
	struct
	{
		UINT32 h26                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h27                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E38
typedef union _REG_CTM_HR14
{
	UINT32 value;
	struct
	{
		UINT32 h28                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h29                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E3C
typedef union _REG_CTM_HR15
{
	UINT32 value;
	struct
	{
		UINT32 h30                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h31                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E40
typedef union _REG_CTM_HR16
{
	UINT32 value;
	struct
	{
		UINT32 h32                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h33                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E44
typedef union _REG_CTM_HR17
{
	UINT32 value;
	struct
	{
		UINT32 h34                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h35                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E48
typedef union _REG_CTM_HR18
{
	UINT32 value;
	struct
	{
		UINT32 h36                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h37                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E4C
typedef union _REG_CTM_HR19
{
	UINT32 value;
	struct
	{
		UINT32 h38                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h39                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E50
typedef union _REG_CTM_HR20
{
	UINT32 value;
	struct
	{
		UINT32 h40                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h41                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E54
typedef union _REG_CTM_HR21
{
	UINT32 value;
	struct
	{
		UINT32 h42                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h43                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E58
typedef union _REG_CTM_HR22
{
	UINT32 value;
	struct
	{
		UINT32 h44                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h45                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping H register
// Offset: 0x4E5C
typedef union _REG_CTM_HR23
{
	UINT32 value;
	struct
	{
		UINT32 h46                  : 13; // [12:0] CTM H register [0.13.0]
		UINT32 rsvd13               : 3 ; // [15:13] 
		UINT32 h47                  : 13; // [28:16] CTM H register [0.13.0]
	} field;
} REG_CTM_HR23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E60
typedef union _REG_CTM_GSR0
{
	UINT32 value;
	struct
	{
		UINT32 gs0                  : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs1                  : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E64
typedef union _REG_CTM_GSR1
{
	UINT32 value;
	struct
	{
		UINT32 gs2                  : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs3                  : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E68
typedef union _REG_CTM_GSR2
{
	UINT32 value;
	struct
	{
		UINT32 gs4                  : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs5                  : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E6C
typedef union _REG_CTM_GSR3
{
	UINT32 value;
	struct
	{
		UINT32 gs6                  : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs7                  : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E70
typedef union _REG_CTM_GSR4
{
	UINT32 value;
	struct
	{
		UINT32 gs8                  : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs9                  : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E74
typedef union _REG_CTM_GSR5
{
	UINT32 value;
	struct
	{
		UINT32 gs10                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs11                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E78
typedef union _REG_CTM_GSR6
{
	UINT32 value;
	struct
	{
		UINT32 gs12                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs13                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E7C
typedef union _REG_CTM_GSR7
{
	UINT32 value;
	struct
	{
		UINT32 gs14                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs15                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E80
typedef union _REG_CTM_GSR8
{
	UINT32 value;
	struct
	{
		UINT32 gs16                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs17                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E84
typedef union _REG_CTM_GSR9
{
	UINT32 value;
	struct
	{
		UINT32 gs18                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs19                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E88
typedef union _REG_CTM_GSR10
{
	UINT32 value;
	struct
	{
		UINT32 gs20                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs21                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E8C
typedef union _REG_CTM_GSR11
{
	UINT32 value;
	struct
	{
		UINT32 gs22                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs23                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E90
typedef union _REG_CTM_GSR12
{
	UINT32 value;
	struct
	{
		UINT32 gs24                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs25                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E94
typedef union _REG_CTM_GSR13
{
	UINT32 value;
	struct
	{
		UINT32 gs26                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs27                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E98
typedef union _REG_CTM_GSR14
{
	UINT32 value;
	struct
	{
		UINT32 gs28                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs29                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4E9C
typedef union _REG_CTM_GSR15
{
	UINT32 value;
	struct
	{
		UINT32 gs30                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs31                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EA0
typedef union _REG_CTM_GSR16
{
	UINT32 value;
	struct
	{
		UINT32 gs32                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs33                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EA4
typedef union _REG_CTM_GSR17
{
	UINT32 value;
	struct
	{
		UINT32 gs34                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs35                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EA8
typedef union _REG_CTM_GSR18
{
	UINT32 value;
	struct
	{
		UINT32 gs36                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs37                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EAC
typedef union _REG_CTM_GSR19
{
	UINT32 value;
	struct
	{
		UINT32 gs38                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs39                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EB0
typedef union _REG_CTM_GSR20
{
	UINT32 value;
	struct
	{
		UINT32 gs40                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs41                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EB4
typedef union _REG_CTM_GSR21
{
	UINT32 value;
	struct
	{
		UINT32 gs42                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs43                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EB8
typedef union _REG_CTM_GSR22
{
	UINT32 value;
	struct
	{
		UINT32 gs44                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs45                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GS register
// Offset: 0x4EBC
typedef union _REG_CTM_GSR23
{
	UINT32 value;
	struct
	{
		UINT32 gs46                 : 11; // [10:0] CTM GS register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gs47                 : 11; // [26:16] CTM GS register [0.3.8]
	} field;
} REG_CTM_GSR23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EC0
typedef union _REG_CTM_GVR0
{
	UINT32 value;
	struct
	{
		UINT32 gv0                  : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv1                  : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR0;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EC4
typedef union _REG_CTM_GVR1
{
	UINT32 value;
	struct
	{
		UINT32 gv2                  : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv3                  : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR1;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EC8
typedef union _REG_CTM_GVR2
{
	UINT32 value;
	struct
	{
		UINT32 gv4                  : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv5                  : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR2;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4ECC
typedef union _REG_CTM_GVR3
{
	UINT32 value;
	struct
	{
		UINT32 gv6                  : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv7                  : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR3;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4ED0
typedef union _REG_CTM_GVR4
{
	UINT32 value;
	struct
	{
		UINT32 gv8                  : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv9                  : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR4;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4ED4
typedef union _REG_CTM_GVR5
{
	UINT32 value;
	struct
	{
		UINT32 gv10                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv11                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR5;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4ED8
typedef union _REG_CTM_GVR6
{
	UINT32 value;
	struct
	{
		UINT32 gv12                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv13                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR6;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EDC
typedef union _REG_CTM_GVR7
{
	UINT32 value;
	struct
	{
		UINT32 gv14                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv15                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR7;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EE0
typedef union _REG_CTM_GVR8
{
	UINT32 value;
	struct
	{
		UINT32 gv16                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv17                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR8;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EE4
typedef union _REG_CTM_GVR9
{
	UINT32 value;
	struct
	{
		UINT32 gv18                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv19                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR9;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EE8
typedef union _REG_CTM_GVR10
{
	UINT32 value;
	struct
	{
		UINT32 gv20                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv21                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR10;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EEC
typedef union _REG_CTM_GVR11
{
	UINT32 value;
	struct
	{
		UINT32 gv22                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv23                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR11;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EF0
typedef union _REG_CTM_GVR12
{
	UINT32 value;
	struct
	{
		UINT32 gv24                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv25                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR12;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EF4
typedef union _REG_CTM_GVR13
{
	UINT32 value;
	struct
	{
		UINT32 gv26                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv27                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR13;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EF8
typedef union _REG_CTM_GVR14
{
	UINT32 value;
	struct
	{
		UINT32 gv28                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv29                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR14;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4EFC
typedef union _REG_CTM_GVR15
{
	UINT32 value;
	struct
	{
		UINT32 gv30                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv31                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR15;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F00
typedef union _REG_CTM_GVR16
{
	UINT32 value;
	struct
	{
		UINT32 gv32                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv33                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR16;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F04
typedef union _REG_CTM_GVR17
{
	UINT32 value;
	struct
	{
		UINT32 gv34                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv35                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR17;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F08
typedef union _REG_CTM_GVR18
{
	UINT32 value;
	struct
	{
		UINT32 gv36                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv37                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR18;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F0C
typedef union _REG_CTM_GVR19
{
	UINT32 value;
	struct
	{
		UINT32 gv38                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv39                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR19;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F10
typedef union _REG_CTM_GVR20
{
	UINT32 value;
	struct
	{
		UINT32 gv40                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv41                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR20;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F14
typedef union _REG_CTM_GVR21
{
	UINT32 value;
	struct
	{
		UINT32 gv42                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv43                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR21;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F18
typedef union _REG_CTM_GVR22
{
	UINT32 value;
	struct
	{
		UINT32 gv44                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv45                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR22;

////////////////////////////////////////////////////////////////////////////////////////////////////
// Color Tone Mapping GV register
// Offset: 0x4F1C
typedef union _REG_CTM_GVR23
{
	UINT32 value;
	struct
	{
		UINT32 gv46                 : 11; // [10:0] CTM GV register [0.3.8]
		UINT32 rsvd11               : 5 ; // [15:11] 
		UINT32 gv47                 : 11; // [26:16] CTM GV register [0.3.8]
	} field;
} REG_CTM_GVR23;

////////////////////////////////////////////////////////////////////////////////////////////////////
// 3D LUT Color Correction Register, 0x8000~0xFFFF(0~8191)
// Offset: 0x8000 ~ 0xFFFF
typedef union _REG_I3DLUT
{
	UINT32 value;
	struct
	{
		UINT32 lut_val              : 30; // [29:0] LUT value
	} field;
} REG_I3DLUT;
#endif




#ifdef REG_VARIABLE_ENABLE
////////////////////////////////////////////////////////////////////////////////////////////////////
// Register variable list.
////////////////////////////////////////////////////////////////////////////////////////////////////
REG_ENABLE_STATUS             reg_enable_status             ; // 0x0000, csi input enable & status register.
REG_VCNT                      reg_vcnt                      ; // 0x0004, input pixel counter register.
REG_CSIINTS                   reg_csiints                   ; // 0x0008, Interrupt and Shadow 
REG_FUNCTION_MODE             reg_function_mode             ; // 0x0010, csi module enable register.
REG_SENSOR                    reg_sensor                    ; // 0x0014, input dvp format & signal polarity cfg.
REG_CFA                       reg_cfa                       ; // 0x0018, input RAW format cfg.
REG_CAPTURE_WINDOW_START      reg_capture_window_start      ; // 0x001C, input picture capture start cfg(x/y start location), each 16bit (cropping)
REG_CAPTURE_WINDOW_END        reg_capture_window_end        ; // 0x0020, input picture capture end cfg(x/y end location), each 16bit (cropping)
REG_DUMP_CFG_0                reg_dump_cfg_0                ; // 0x0024, base address for captured image
REG_DUMP_CFG_1                reg_dump_cfg_1                ; // 0x0028, dump configuration
REG_DEC_CFG                   reg_dec_cfg                   ; // 0x0030, csi pipeline dec cfg register, Horizontal/Vertical period/keep, must set to odd 
REG_OBC_CFG                   reg_obc_cfg                   ; // 0x0034, OBC(Optical Black Compensation) window height(2^HEIGHT)/OBC window width(2^WIDTH),
REG_DC_CFG_0                  reg_dc_cfg_0                  ; // 0x0040, DC axi base address register
REG_DC_CFG_1                  reg_dc_cfg_1                  ; // 0x0044, DC axi id
REG_LCCF_CFG_0                reg_lccf_cfg_0                ; // 0x0050, X/Y distance from capture window(each 15bits)
REG_LCCF_CFG_1                reg_lccf_cfg_1                ; // 0x0058, LCCF maximum distance register
REG_LCBQ_CFG_0                reg_lcbq_cfg_0                ; // 0x0074, LCBQ pseudo sub-window register
REG_LCBQ_CFG_1                reg_lcbq_cfg_1                ; // 0x007C, LCBQ X/Y coordinate register
REG_OBA_CFG_0                 reg_oba_cfg_0                 ; // 0x0090, Vertical starting point/Horizontal ending point, each 16bits (black cropping)
REG_OBA_CFG_1                 reg_oba_cfg_1                 ; // 0x0094, Vertical ending point/Horizontal ending point, each 16bits
REG_SCD_CFG_0                 reg_scd_cfg_0                 ; // 0x0098, SC dumping base address 
REG_SCD_CFG_1                 reg_scd_cfg_1                 ; // 0x009C, SC dumping axi id
REG_OBA_ACC_0                 reg_oba_acc_0                 ; // 0x00A0, OBA value for symbol 0
REG_OBA_ACC_1                 reg_oba_acc_1                 ; // 0x00A4, OBA value for symbol 1
REG_OBA_ACC_2                 reg_oba_acc_2                 ; // 0x00A8, OBA value for symbol 2
REG_OBA_ACC_3                 reg_oba_acc_3                 ; // 0x00AC, OBA value for symbol 3
REG_SC_CFG_0                  reg_sc_cfg_0                  ; // 0x00B8, SC frame cropping for sc awb
REG_SC_CFG_1                  reg_sc_cfg_1                  ; // 0x00BC, SC cfg1 register
REG_SC_AF                     reg_sc_af                     ; // 0x00C0, SC AF register
REG_SC_AWB_PS_CFG_0           reg_sc_awb_ps_cfg_0           ; // 0x00C4, SC AWB pixel sum registers0
REG_SC_AWB_PS_CFG_1           reg_sc_awb_ps_cfg_1           ; // 0x00C8, SC AWB pixel sum registers1
REG_SC_AWB_PS_CFG_2           reg_sc_awb_ps_cfg_2           ; // 0x00CC, SC AWB pixel sum registers2
REG_SC_AWB_PS_CFG_3           reg_sc_awb_ps_cfg_3           ; // 0x00D0, SC AWB pixel sum registers3
REG_SC_AWB_PS_CFG_4           reg_sc_awb_ps_cfg_4           ; // 0x00D4, SC AWB pixel sum registers4
REG_SC_DEC                    reg_sc_dec                    ; // 0x00D8, sc0 dec cfg register for sc awb, Horizontal/Vertical period/keep
REG_LCCF_CFG_2                reg_lccf_cfg_2                ; // 0x00E0, LCCF F parameter for symbol 0 register
REG_LCCF_CFG_3                reg_lccf_cfg_3                ; // 0x00E4, LCCF F parameter for symbol 1 register
REG_LCCF_CFG_4                reg_lccf_cfg_4                ; // 0x00E8, LCCF F parameter for symbol 2 register
REG_LCCF_CFG_5                reg_lccf_cfg_5                ; // 0x00EC, LCCF F parameter for symbol 3 register
REG_SCR_ADR                   reg_scr_adr                   ; // 0x00F8, SC read index
REG_SCR_DAT                   reg_scr_dat                   ; // 0x00FC, SC read data
REG_OECF_X0_CFG_0             reg_oecf_x0_cfg_0             ; // 0x0100, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X0_CFG_1             reg_oecf_x0_cfg_1             ; // 0x0104, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X0_CFG_2             reg_oecf_x0_cfg_2             ; // 0x0108, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X0_CFG_3             reg_oecf_x0_cfg_3             ; // 0x010C, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X0_CFG_4             reg_oecf_x0_cfg_4             ; // 0x0110, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X0_CFG_5             reg_oecf_x0_cfg_5             ; // 0x0114, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X0_CFG_6             reg_oecf_x0_cfg_6             ; // 0x0118, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X0_CFG_7             reg_oecf_x0_cfg_7             ; // 0x011C, OECF X parameter[0.PW.0] register for symbol 0 
REG_OECF_X1_CFG_0             reg_oecf_x1_cfg_0             ; // 0x0120, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X1_CFG_1             reg_oecf_x1_cfg_1             ; // 0x0124, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X1_CFG_2             reg_oecf_x1_cfg_2             ; // 0x0128, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X1_CFG_3             reg_oecf_x1_cfg_3             ; // 0x012C, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X1_CFG_4             reg_oecf_x1_cfg_4             ; // 0x0130, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X1_CFG_5             reg_oecf_x1_cfg_5             ; // 0x0134, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X1_CFG_6             reg_oecf_x1_cfg_6             ; // 0x0138, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X1_CFG_7             reg_oecf_x1_cfg_7             ; // 0x013C, OECF X parameter[0.PW.0] register for symbol 1 
REG_OECF_X2_CFG_0             reg_oecf_x2_cfg_0             ; // 0x0140, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X2_CFG_1             reg_oecf_x2_cfg_1             ; // 0x0144, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X2_CFG_2             reg_oecf_x2_cfg_2             ; // 0x0148, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X2_CFG_3             reg_oecf_x2_cfg_3             ; // 0x014C, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X2_CFG_4             reg_oecf_x2_cfg_4             ; // 0x0150, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X2_CFG_5             reg_oecf_x2_cfg_5             ; // 0x0154, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X2_CFG_6             reg_oecf_x2_cfg_6             ; // 0x0158, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X2_CFG_7             reg_oecf_x2_cfg_7             ; // 0x015C, OECF X parameter[0.PW.0] register for symbol 2 
REG_OECF_X3_CFG_0             reg_oecf_x3_cfg_0             ; // 0x0160, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_X3_CFG_1             reg_oecf_x3_cfg_1             ; // 0x0164, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_X3_CFG_2             reg_oecf_x3_cfg_2             ; // 0x0168, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_X3_CFG_3             reg_oecf_x3_cfg_3             ; // 0x016C, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_X3_CFG_4             reg_oecf_x3_cfg_4             ; // 0x0170, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_X3_CFG_5             reg_oecf_x3_cfg_5             ; // 0x0174, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_X3_CFG_6             reg_oecf_x3_cfg_6             ; // 0x0178, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_X3_CFG_7             reg_oecf_x3_cfg_7             ; // 0x017C, OECF X parameter[0.PW.0] register for symbol 3 
REG_OECF_Y0_CFG_0             reg_oecf_y0_cfg_0             ; // 0x0180, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y0_CFG_1             reg_oecf_y0_cfg_1             ; // 0x0184, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y0_CFG_2             reg_oecf_y0_cfg_2             ; // 0x0188, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y0_CFG_3             reg_oecf_y0_cfg_3             ; // 0x018C, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y0_CFG_4             reg_oecf_y0_cfg_4             ; // 0x0190, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y0_CFG_5             reg_oecf_y0_cfg_5             ; // 0x0194, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y0_CFG_6             reg_oecf_y0_cfg_6             ; // 0x0198, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y0_CFG_7             reg_oecf_y0_cfg_7             ; // 0x019C, OECF Y parameter[0.PW.0] register for symbol 0 
REG_OECF_Y1_CFG_0             reg_oecf_y1_cfg_0             ; // 0x01A0, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y1_CFG_1             reg_oecf_y1_cfg_1             ; // 0x01A4, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y1_CFG_2             reg_oecf_y1_cfg_2             ; // 0x01A8, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y1_CFG_3             reg_oecf_y1_cfg_3             ; // 0x01AC, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y1_CFG_4             reg_oecf_y1_cfg_4             ; // 0x01B0, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y1_CFG_5             reg_oecf_y1_cfg_5             ; // 0x01B4, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y1_CFG_6             reg_oecf_y1_cfg_6             ; // 0x01B8, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y1_CFG_7             reg_oecf_y1_cfg_7             ; // 0x01BC, OECF Y parameter[0.PW.0] register for symbol 1 
REG_OECF_Y2_CFG_0             reg_oecf_y2_cfg_0             ; // 0x01C0, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y2_CFG_1             reg_oecf_y2_cfg_1             ; // 0x01C4, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y2_CFG_2             reg_oecf_y2_cfg_2             ; // 0x01C8, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y2_CFG_3             reg_oecf_y2_cfg_3             ; // 0x01CC, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y2_CFG_4             reg_oecf_y2_cfg_4             ; // 0x01D0, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y2_CFG_5             reg_oecf_y2_cfg_5             ; // 0x01D4, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y2_CFG_6             reg_oecf_y2_cfg_6             ; // 0x01D8, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y2_CFG_7             reg_oecf_y2_cfg_7             ; // 0x01DC, OECF Y parameter[0.PW.0] register for symbol 2 
REG_OECF_Y3_CFG_0             reg_oecf_y3_cfg_0             ; // 0x01E0, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_Y3_CFG_1             reg_oecf_y3_cfg_1             ; // 0x01E4, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_Y3_CFG_2             reg_oecf_y3_cfg_2             ; // 0x01E8, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_Y3_CFG_3             reg_oecf_y3_cfg_3             ; // 0x01EC, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_Y3_CFG_4             reg_oecf_y3_cfg_4             ; // 0x01F0, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_Y3_CFG_5             reg_oecf_y3_cfg_5             ; // 0x01F4, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_Y3_CFG_6             reg_oecf_y3_cfg_6             ; // 0x01F8, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_Y3_CFG_7             reg_oecf_y3_cfg_7             ; // 0x01FC, OECF Y parameter[0.PW.0] register for symbol 3 
REG_OECF_S0_CFG_0             reg_oecf_s0_cfg_0             ; // 0x0200, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S0_CFG_1             reg_oecf_s0_cfg_1             ; // 0x0204, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S0_CFG_2             reg_oecf_s0_cfg_2             ; // 0x0208, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S0_CFG_3             reg_oecf_s0_cfg_3             ; // 0x020C, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S0_CFG_4             reg_oecf_s0_cfg_4             ; // 0x0210, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S0_CFG_5             reg_oecf_s0_cfg_5             ; // 0x0214, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S0_CFG_6             reg_oecf_s0_cfg_6             ; // 0x0218, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S0_CFG_7             reg_oecf_s0_cfg_7             ; // 0x021C, OECF [0.3.7] S parameter register for symbol 0 
REG_OECF_S1_CFG_0             reg_oecf_s1_cfg_0             ; // 0x0220, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S1_CFG_1             reg_oecf_s1_cfg_1             ; // 0x0224, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S1_CFG_2             reg_oecf_s1_cfg_2             ; // 0x0228, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S1_CFG_3             reg_oecf_s1_cfg_3             ; // 0x022C, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S1_CFG_4             reg_oecf_s1_cfg_4             ; // 0x0230, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S1_CFG_5             reg_oecf_s1_cfg_5             ; // 0x0234, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S1_CFG_6             reg_oecf_s1_cfg_6             ; // 0x0238, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S1_CFG_7             reg_oecf_s1_cfg_7             ; // 0x023C, OECF [0.3.7] S parameter register for symbol 1 
REG_OECF_S2_CFG_0             reg_oecf_s2_cfg_0             ; // 0x0240, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S2_CFG_1             reg_oecf_s2_cfg_1             ; // 0x0244, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S2_CFG_2             reg_oecf_s2_cfg_2             ; // 0x0248, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S2_CFG_3             reg_oecf_s2_cfg_3             ; // 0x024C, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S2_CFG_4             reg_oecf_s2_cfg_4             ; // 0x0250, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S2_CFG_5             reg_oecf_s2_cfg_5             ; // 0x0254, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S2_CFG_6             reg_oecf_s2_cfg_6             ; // 0x0258, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S2_CFG_7             reg_oecf_s2_cfg_7             ; // 0x025C, OECF [0.3.7] S parameter register for symbol 2 
REG_OECF_S3_CFG_0             reg_oecf_s3_cfg_0             ; // 0x0260, OECF [0.3.7] S parameter register for symbol 3 
REG_OECF_S3_CFG_1             reg_oecf_s3_cfg_1             ; // 0x0264, OECF [0.3.7] S parameter register for symbol 3 
REG_OECF_S3_CFG_2             reg_oecf_s3_cfg_2             ; // 0x0268, OECF [0.3.7] S parameter register for symbol 3 
REG_OECF_S3_CFG_3             reg_oecf_s3_cfg_3             ; // 0x026C, OECF [0.3.7] S parameter register for symbol 3 
REG_OECF_S3_CFG_4             reg_oecf_s3_cfg_4             ; // 0x0270, OECF [0.3.7] S parameter register for symbol 3 
REG_OECF_S3_CFG_5             reg_oecf_s3_cfg_5             ; // 0x0274, OECF [0.3.7] S parameter register for symbol 3 
REG_OECF_S3_CFG_6             reg_oecf_s3_cfg_6             ; // 0x0278, OECF [0.3.7] S parameter register for symbol 3 
REG_OECF_S3_CFG_7             reg_oecf_s3_cfg_7             ; // 0x027C, OECF [0.3.7] S parameter register for symbol 3 
REG_AWB_X0_CFG_0              reg_awb_x0_cfg_0              ; // 0x0280, X0/X1 for symbol 0, each 10bits
REG_AWB_X0_CFG_1              reg_awb_x0_cfg_1              ; // 0x0284, X2/X3 for symbol 0, each 10bits
REG_AWB_X1_CFG_0              reg_awb_x1_cfg_0              ; // 0x0288, X0/X1 for symbol 1, each 10bits
REG_AWB_X1_CFG_1              reg_awb_x1_cfg_1              ; // 0x028C, X2/X3 for symbol 1, each 10bits
REG_AWB_X2_CFG_0              reg_awb_x2_cfg_0              ; // 0x0290, X0/X1 for symbol 2, each 10bits
REG_AWB_X2_CFG_1              reg_awb_x2_cfg_1              ; // 0x0294, X2/X3 for symbol 2, each 10bits
REG_AWB_X3_CFG_0              reg_awb_x3_cfg_0              ; // 0x0298, X0/X1 for symbol 3, each 10bits
REG_AWB_X3_CFG_1              reg_awb_x3_cfg_1              ; // 0x029C, X2/X3 for symbol 3, each 10bits
REG_AWB_Y0_CFG_0              reg_awb_y0_cfg_0              ; // 0x02A0, Y0/Y1 for symbol 0, each 10bits
REG_AWB_Y0_CFG_1              reg_awb_y0_cfg_1              ; // 0x02A4, Y2/Y3 for symbol 0, each 10bits
REG_AWB_Y1_CFG_0              reg_awb_y1_cfg_0              ; // 0x02A8, Y0/Y1 for symbol 1, each 10bits
REG_AWB_Y1_CFG_1              reg_awb_y1_cfg_1              ; // 0x02AC, Y2/Y3 for symbol 1, each 10bits
REG_AWB_Y2_CFG_0              reg_awb_y2_cfg_0              ; // 0x02B0, Y0/Y1 for symbol 2, each 10bits
REG_AWB_Y2_CFG_1              reg_awb_y2_cfg_1              ; // 0x02B4, Y2/Y3 for symbol 2, each 10bits
REG_AWB_Y3_CFG_0              reg_awb_y3_cfg_0              ; // 0x02B8, Y0/Y1 for symbol 3, each 10bits
REG_AWB_Y3_CFG_1              reg_awb_y3_cfg_1              ; // 0x02BC, Y2/Y3 for symbol 3, each 10bits
REG_AWB_S0_CFG_0              reg_awb_s0_cfg_0              ; // 0x02C0, [0.3.7] S0/S1 for symbol 0, each 10bits
REG_AWB_S0_CFG_1              reg_awb_s0_cfg_1              ; // 0x02C4, [0.3.7] S2/S3 for symbol 0, each 10bits
REG_AWB_S1_CFG_0              reg_awb_s1_cfg_0              ; // 0x02C8, [0.3.7] S0/S1 for symbol 1, each 10bits
REG_AWB_S1_CFG_1              reg_awb_s1_cfg_1              ; // 0x02CC, [0.3.7] S2/S3 for symbol 1, each 10bits
REG_AWB_S2_CFG_0              reg_awb_s2_cfg_0              ; // 0x02D0, [0.3.7] S0/S1 for symbol 2, each 10bits
REG_AWB_S2_CFG_1              reg_awb_s2_cfg_1              ; // 0x02D4, [0.3.7] S2/S3 for symbol 2, each 10bits
REG_AWB_S3_CFG_0              reg_awb_s3_cfg_0              ; // 0x02D8, [0.3.7] S0/S1 for symbol 3, each 10bits
REG_AWB_S3_CFG_1              reg_awb_s3_cfg_1              ; // 0x02DC, [0.3.7] S2/S3 for symbol 3, each 10bits
REG_OBCG_CFG_0                reg_obcg_cfg_0                ; // 0x02E0, each symbol has four point, each point has one 8bit gain register
REG_OBCG_CFG_1                reg_obcg_cfg_1                ; // 0x02E4, each symbol has four point, each point has one 8bit gain register
REG_OBCG_CFG_2                reg_obcg_cfg_2                ; // 0x02E8, each symbol has four point, each point has one 8bit gain register
REG_OBCG_CFG_3                reg_obcg_cfg_3                ; // 0x02EC, each symbol has four point, each point has one 8bit gain register
REG_OBCO_CFG_0                reg_obco_cfg_0                ; // 0x02F0, each symbol has four points
REG_OBCO_CFG_1                reg_obco_cfg_1                ; // 0x02F4, each symbol has four points
REG_OBCO_CFG_2                reg_obco_cfg_2                ; // 0x02F8, each symbol has four points
REG_OBCO_CFG_3                reg_obco_cfg_3                ; // 0x02FC, each symbol has four points
REG_LCBQ_GAIN0_CFG_0          reg_lcbq_gain0_cfg_0          ; // 0x0300, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_1          reg_lcbq_gain0_cfg_1          ; // 0x0304, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_2          reg_lcbq_gain0_cfg_2          ; // 0x0308, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_3          reg_lcbq_gain0_cfg_3          ; // 0x030C, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_4          reg_lcbq_gain0_cfg_4          ; // 0x0310, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_5          reg_lcbq_gain0_cfg_5          ; // 0x0314, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_6          reg_lcbq_gain0_cfg_6          ; // 0x0318, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_7          reg_lcbq_gain0_cfg_7          ; // 0x031C, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_8          reg_lcbq_gain0_cfg_8          ; // 0x0320, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_9          reg_lcbq_gain0_cfg_9          ; // 0x0324, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_10         reg_lcbq_gain0_cfg_10         ; // 0x0328, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_11         reg_lcbq_gain0_cfg_11         ; // 0x032C, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN0_CFG_12         reg_lcbq_gain0_cfg_12         ; // 0x0330, LCBQ [0.1.8] Gain parameter register for symbol 0 
REG_LCBQ_GAIN1_CFG_0          reg_lcbq_gain1_cfg_0          ; // 0x0334, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_1          reg_lcbq_gain1_cfg_1          ; // 0x0338, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_2          reg_lcbq_gain1_cfg_2          ; // 0x033C, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_3          reg_lcbq_gain1_cfg_3          ; // 0x0340, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_4          reg_lcbq_gain1_cfg_4          ; // 0x0344, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_5          reg_lcbq_gain1_cfg_5          ; // 0x0348, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_6          reg_lcbq_gain1_cfg_6          ; // 0x034C, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_7          reg_lcbq_gain1_cfg_7          ; // 0x0350, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_8          reg_lcbq_gain1_cfg_8          ; // 0x0354, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_9          reg_lcbq_gain1_cfg_9          ; // 0x0358, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_10         reg_lcbq_gain1_cfg_10         ; // 0x035C, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_11         reg_lcbq_gain1_cfg_11         ; // 0x0360, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN1_CFG_12         reg_lcbq_gain1_cfg_12         ; // 0x0364, LCBQ [0.1.8] Gain parameter register for symbol 1 
REG_LCBQ_GAIN2_CFG_0          reg_lcbq_gain2_cfg_0          ; // 0x0368, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_1          reg_lcbq_gain2_cfg_1          ; // 0x036C, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_2          reg_lcbq_gain2_cfg_2          ; // 0x0370, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_3          reg_lcbq_gain2_cfg_3          ; // 0x0374, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_4          reg_lcbq_gain2_cfg_4          ; // 0x0378, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_5          reg_lcbq_gain2_cfg_5          ; // 0x037C, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_6          reg_lcbq_gain2_cfg_6          ; // 0x0380, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_7          reg_lcbq_gain2_cfg_7          ; // 0x0384, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_8          reg_lcbq_gain2_cfg_8          ; // 0x0388, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_9          reg_lcbq_gain2_cfg_9          ; // 0x038C, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_10         reg_lcbq_gain2_cfg_10         ; // 0x0390, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_11         reg_lcbq_gain2_cfg_11         ; // 0x0394, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN2_CFG_12         reg_lcbq_gain2_cfg_12         ; // 0x0398, LCBQ [0.1.8] Gain parameter register for symbol 2 
REG_LCBQ_GAIN3_CFG_0          reg_lcbq_gain3_cfg_0          ; // 0x039C, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_1          reg_lcbq_gain3_cfg_1          ; // 0x03A0, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_2          reg_lcbq_gain3_cfg_2          ; // 0x03A4, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_3          reg_lcbq_gain3_cfg_3          ; // 0x03A8, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_4          reg_lcbq_gain3_cfg_4          ; // 0x03AC, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_5          reg_lcbq_gain3_cfg_5          ; // 0x03B0, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_6          reg_lcbq_gain3_cfg_6          ; // 0x03B4, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_7          reg_lcbq_gain3_cfg_7          ; // 0x03B8, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_8          reg_lcbq_gain3_cfg_8          ; // 0x03BC, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_9          reg_lcbq_gain3_cfg_9          ; // 0x03C0, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_10         reg_lcbq_gain3_cfg_10         ; // 0x03C4, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_11         reg_lcbq_gain3_cfg_11         ; // 0x03C8, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_LCBQ_GAIN3_CFG_12         reg_lcbq_gain3_cfg_12         ; // 0x03CC, LCBQ [0.1.8] Gain parameter register for symbol 3 
REG_OECFHM_Y_CFG_0            reg_oecfhm_y_cfg_0            ; // 0x03D0, OECF Hermite
REG_OECFHM_Y_CFG_1            reg_oecfhm_y_cfg_1            ; // 0x03D4, OECF Hermite
REG_OECFHM_Y_CFG_2            reg_oecfhm_y_cfg_2            ; // 0x03D8, OECF Hermite
REG_OECFHM_S_CFG_0            reg_oecfhm_s_cfg_0            ; // 0x03DC, OECF Hermite
REG_OECFHM_S_CFG_1            reg_oecfhm_s_cfg_1            ; // 0x03E0, OECF Hermite
REG_OECFHM_S_CFG_2            reg_oecfhm_s_cfg_2            ; // 0x03E4, OECF Hermite
REG_LCBQ_OFFSET0_CFG_0        reg_lcbq_offset0_cfg_0        ; // 0x0400, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_1        reg_lcbq_offset0_cfg_1        ; // 0x0404, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_2        reg_lcbq_offset0_cfg_2        ; // 0x0408, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_3        reg_lcbq_offset0_cfg_3        ; // 0x040C, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_4        reg_lcbq_offset0_cfg_4        ; // 0x0410, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_5        reg_lcbq_offset0_cfg_5        ; // 0x0414, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_6        reg_lcbq_offset0_cfg_6        ; // 0x0418, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_7        reg_lcbq_offset0_cfg_7        ; // 0x041C, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_8        reg_lcbq_offset0_cfg_8        ; // 0x0420, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_9        reg_lcbq_offset0_cfg_9        ; // 0x0424, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_10       reg_lcbq_offset0_cfg_10       ; // 0x0428, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_11       reg_lcbq_offset0_cfg_11       ; // 0x042C, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET0_CFG_12       reg_lcbq_offset0_cfg_12       ; // 0x0430, LCBQ [1.8.0] Offset parameter register for symbol 0 
REG_LCBQ_OFFSET1_CFG_0        reg_lcbq_offset1_cfg_0        ; // 0x0434, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_1        reg_lcbq_offset1_cfg_1        ; // 0x0438, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_2        reg_lcbq_offset1_cfg_2        ; // 0x043C, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_3        reg_lcbq_offset1_cfg_3        ; // 0x0440, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_4        reg_lcbq_offset1_cfg_4        ; // 0x0444, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_5        reg_lcbq_offset1_cfg_5        ; // 0x0448, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_6        reg_lcbq_offset1_cfg_6        ; // 0x044C, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_7        reg_lcbq_offset1_cfg_7        ; // 0x0450, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_8        reg_lcbq_offset1_cfg_8        ; // 0x0454, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_9        reg_lcbq_offset1_cfg_9        ; // 0x0458, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_10       reg_lcbq_offset1_cfg_10       ; // 0x045C, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_11       reg_lcbq_offset1_cfg_11       ; // 0x0460, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET1_CFG_12       reg_lcbq_offset1_cfg_12       ; // 0x0464, LCBQ [1.8.0] Offset parameter register for symbol 1 
REG_LCBQ_OFFSET2_CFG_0        reg_lcbq_offset2_cfg_0        ; // 0x0468, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_1        reg_lcbq_offset2_cfg_1        ; // 0x046C, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_2        reg_lcbq_offset2_cfg_2        ; // 0x0470, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_3        reg_lcbq_offset2_cfg_3        ; // 0x0474, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_4        reg_lcbq_offset2_cfg_4        ; // 0x0478, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_5        reg_lcbq_offset2_cfg_5        ; // 0x047C, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_6        reg_lcbq_offset2_cfg_6        ; // 0x0480, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_7        reg_lcbq_offset2_cfg_7        ; // 0x0484, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_8        reg_lcbq_offset2_cfg_8        ; // 0x0488, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_9        reg_lcbq_offset2_cfg_9        ; // 0x048C, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_10       reg_lcbq_offset2_cfg_10       ; // 0x0490, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_11       reg_lcbq_offset2_cfg_11       ; // 0x0494, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET2_CFG_12       reg_lcbq_offset2_cfg_12       ; // 0x0498, LCBQ [1.8.0] Offset parameter register for symbol 2 
REG_LCBQ_OFFSET3_CFG_0        reg_lcbq_offset3_cfg_0        ; // 0x049C, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_1        reg_lcbq_offset3_cfg_1        ; // 0x04A0, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_2        reg_lcbq_offset3_cfg_2        ; // 0x04A4, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_3        reg_lcbq_offset3_cfg_3        ; // 0x04A8, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_4        reg_lcbq_offset3_cfg_4        ; // 0x04AC, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_5        reg_lcbq_offset3_cfg_5        ; // 0x04B0, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_6        reg_lcbq_offset3_cfg_6        ; // 0x04B4, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_7        reg_lcbq_offset3_cfg_7        ; // 0x04B8, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_8        reg_lcbq_offset3_cfg_8        ; // 0x04BC, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_9        reg_lcbq_offset3_cfg_9        ; // 0x04C0, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_10       reg_lcbq_offset3_cfg_10       ; // 0x04C4, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_11       reg_lcbq_offset3_cfg_11       ; // 0x04C8, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_LCBQ_OFFSET3_CFG_12       reg_lcbq_offset3_cfg_12       ; // 0x04CC, LCBQ [1.8.0] Offset parameter register for symbol 3 
REG_SC_AWB_WS_CW0_CFG_0       reg_sc_awb_ws_cw0_cfg_0       ; // 0x04D0, Weighting value at point(0,0~7), each 4bits
REG_SC_AWB_WS_CW0_CFG_1       reg_sc_awb_ws_cw0_cfg_1       ; // 0x04D4, Weighting value at point(0,8~12), each 4bits
REG_SC_AWB_WS_CW1_CFG_0       reg_sc_awb_ws_cw1_cfg_0       ; // 0x04D8, Weighting value at point(1,0~7), each 4bits
REG_SC_AWB_WS_CW1_CFG_1       reg_sc_awb_ws_cw1_cfg_1       ; // 0x04DC, Weighting value at point(1,8~12), each 4bits
REG_SC_AWB_WS_CW2_CFG_0       reg_sc_awb_ws_cw2_cfg_0       ; // 0x04E0, Weighting value at point(2,0~7), each 4bits
REG_SC_AWB_WS_CW2_CFG_1       reg_sc_awb_ws_cw2_cfg_1       ; // 0x04E4, Weighting value at point(2,8~12), each 4bits
REG_SC_AWB_WS_CW3_CFG_0       reg_sc_awb_ws_cw3_cfg_0       ; // 0x04E8, Weighting value at point(3,0~7), each 4bits
REG_SC_AWB_WS_CW3_CFG_1       reg_sc_awb_ws_cw3_cfg_1       ; // 0x04EC, Weighting value at point(3,8~12), each 4bits
REG_SC_AWB_WS_CW4_CFG_0       reg_sc_awb_ws_cw4_cfg_0       ; // 0x04F0, Weighting value at point(4,0~7), each 4bits
REG_SC_AWB_WS_CW4_CFG_1       reg_sc_awb_ws_cw4_cfg_1       ; // 0x04F4, Weighting value at point(4,8~12), each 4bits
REG_SC_AWB_WS_CW5_CFG_0       reg_sc_awb_ws_cw5_cfg_0       ; // 0x04F8, Weighting value at point(5,0~7), each 4bits
REG_SC_AWB_WS_CW5_CFG_1       reg_sc_awb_ws_cw5_cfg_1       ; // 0x04FC, Weighting value at point(5,8~12), each 4bits
REG_SC_AWB_WS_CW6_CFG_0       reg_sc_awb_ws_cw6_cfg_0       ; // 0x0500, Weighting value at point(6,0~7), each 4bits
REG_SC_AWB_WS_CW6_CFG_1       reg_sc_awb_ws_cw6_cfg_1       ; // 0x0504, Weighting value at point(6,8~12), each 4bits
REG_SC_AWB_WS_CW7_CFG_0       reg_sc_awb_ws_cw7_cfg_0       ; // 0x0508, Weighting value at point(7,0~7), each 4bits
REG_SC_AWB_WS_CW7_CFG_1       reg_sc_awb_ws_cw7_cfg_1       ; // 0x050C, Weighting value at point(7,8~12), each 4bits
REG_SC_AWB_WS_CW8_CFG_0       reg_sc_awb_ws_cw8_cfg_0       ; // 0x0510, Weighting value at point(8,0~7), each 4bits
REG_SC_AWB_WS_CW8_CFG_1       reg_sc_awb_ws_cw8_cfg_1       ; // 0x0514, Weighting value at point(8,8~12), each 4bits
REG_SC_AWB_WS_CW9_CFG_0       reg_sc_awb_ws_cw9_cfg_0       ; // 0x0518, Weighting value at point(9,0~7), each 4bits
REG_SC_AWB_WS_CW9_CFG_1       reg_sc_awb_ws_cw9_cfg_1       ; // 0x051C, Weighting value at point(9,8~12), each 4bits
REG_SC_AWB_WS_CW10_CFG_0      reg_sc_awb_ws_cw10_cfg_0      ; // 0x0520, Weighting value at point(10,0~7), each 4bits
REG_SC_AWB_WS_CW10_CFG_1      reg_sc_awb_ws_cw10_cfg_1      ; // 0x0524, Weighting value at point(10,8~12), each 4bits
REG_SC_AWB_WS_CW11_CFG_0      reg_sc_awb_ws_cw11_cfg_0      ; // 0x0528, Weighting value at point(11,0~7), each 4bits
REG_SC_AWB_WS_CW11_CFG_1      reg_sc_awb_ws_cw11_cfg_1      ; // 0x052C, Weighting value at point(11,8~12), each 4bits
REG_SC_AWB_WS_CW12_CFG_0      reg_sc_awb_ws_cw12_cfg_0      ; // 0x0530, Weighting value at point(12,0~7), each 4bits
REG_SC_AWB_WS_CW12_CFG_1      reg_sc_awb_ws_cw12_cfg_1      ; // 0x0534, Weighting value at point(12,8~12), each 4bits
REG_SC_AWB_WS_IWV_CFG_0       reg_sc_awb_ws_iwv_cfg_0       ; // 0x0538, Weighting value at point(0~7), each 4bits
REG_SC_AWB_WS_IWV_CFG_1       reg_sc_awb_ws_iwv_cfg_1       ; // 0x053C, Weighting value at point(8~15), each 4bits
REG_SC_AWB_WS_IWS_CFG_0       reg_sc_awb_ws_iws_cfg_0       ; // 0x0540, Slope value at point(0~3), each 8bits
REG_SC_AWB_WS_IWS_CFG_1       reg_sc_awb_ws_iws_cfg_1       ; // 0x0544, Slope value at point(4~7), each 8bits
REG_SC_AWB_WS_IWS_CFG_2       reg_sc_awb_ws_iws_cfg_2       ; // 0x0548, Slope value at point(8~11), each 8bits
REG_SC_AWB_WS_IWS_CFG_3       reg_sc_awb_ws_iws_cfg_3       ; // 0x054C, Slope value at point(12~15), each 8bits
REG_SC_AWB_WS_CFG_0           reg_sc_awb_ws_cfg_0           ; // 0x05D0, SC AWB weight sum registers0
REG_SC_AWB_WS_CFG_1           reg_sc_awb_ws_cfg_1           ; // 0x05D4, SC AWB weight sum registers1
REG_CSICBFS                   reg_csicbfs                   ; // 0x0600, Color Bar Frame Size
REG_CSICBS                    reg_csicbs                    ; // 0x0604, Color Bar Frame Start
REG_CSICBE                    reg_csicbe                    ; // 0x0608, Color Bar Frame End
REG_CSICBMD0                  reg_csicbmd0                  ; // 0x060C, Color Bar Mode 0
REG_CSICBMD1                  reg_csicbmd1                  ; // 0x0610, Color Bar Mode 1
REG_CSICBP01                  reg_csicbp01                  ; // 0x0614, Color Bar Pixel 01
REG_CSICBP23                  reg_csicbp23                  ; // 0x0618, Color Bar Pixel 23
REG_CSICBP45                  reg_csicbp45                  ; // 0x061C, Color Bar Pixel 45
REG_CSICBP67                  reg_csicbp67                  ; // 0x0620, Color Bar Pixel 67
REG_CSICBP89                  reg_csicbp89                  ; // 0x0624, Color Bar Pixel 89
REG_CSICBPAB                  reg_csicbpab                  ; // 0x0628, Color Bar Pixel AB
REG_CSICBPCD                  reg_csicbpcd                  ; // 0x062C, Color Bar Pixel CD
REG_CSICBPEF                  reg_csicbpef                  ; // 0x0630, Color Bar Pixel EF
REG_CSICBL1P01                reg_csicbl1p01                ; // 0x0634, Color Bar Line 1 Pixel 01
REG_CSICBL1P23                reg_csicbl1p23                ; // 0x0638, Color Bar Line 1 Pixel 23
REG_CSICBL1P45                reg_csicbl1p45                ; // 0x063C, Color Bar Line 1 Pixel 45
REG_CSICBL1P67                reg_csicbl1p67                ; // 0x0640, Color Bar Line 1 Pixel 67
REG_CSICBL1P89                reg_csicbl1p89                ; // 0x0644, Color Bar Line 1 Pixel 89
REG_CSICBL1PAB                reg_csicbl1pab                ; // 0x0648, Color Bar Line 1 Pixel AB
REG_CSICBL1PCD                reg_csicbl1pcd                ; // 0x064C, Color Bar Line 1 Pixel CD
REG_CSICBL1PEF                reg_csicbl1pef                ; // 0x0650, Color Bar Line 1 Pixel EF
REG_ISPCTRL0                  reg_ispctrl0                  ; // 0x0A00, ISP Control Register 0
REG_ISPSTAT0                  reg_ispstat0                  ; // 0x0A04, ISP status
REG_ISPCTRL1                  reg_ispctrl1                  ; // 0x0A08, ISP Control Register 1
REG_IFSZ                      reg_ifsz                      ; // 0x0A0C, isp pipeline X/Y size, each 13bits(after decimation)
REG_ICTC                      reg_ictc                      ; // 0x0A10, GrGb Filter threshold 1 Register
REG_IDBC                      reg_idbc                      ; // 0x0A14, GrGb filter threshold 2 Register
REG_ICFAM                     reg_icfam                     ; // 0x0A1C, CFA Mode Register
REG_ISAT0                     reg_isat0                     ; // 0x0A30, Chroma Saturation Gain
REG_ISAT1                     reg_isat1                     ; // 0x0A34, Chroma Saturation Threshold
REG_ISAT2                     reg_isat2                     ; // 0x0A38, Chroma Saturation UV Offset
REG_ISAT3                     reg_isat3                     ; // 0x0A3C, Chroma Saturation Hue Factor 
REG_ISAT4                     reg_isat4                     ; // 0x0A40, Chroma Saturation scaling coefficient
REG_IESHD                     reg_ieshd                     ; // 0x0A50, Image engine shadow control Register
REG_IYADJ0                    reg_iyadj0                    ; // 0x0A54, Y Adjustment Register 0
REG_IYADJ1                    reg_iyadj1                    ; // 0x0A58, Y Adjustment Register 1
REG_UOAY                      reg_uoay                      ; // 0x0A80, Unscaled Output Image Y Plane Start Address Register
REG_UOAUV                     reg_uoauv                     ; // 0x0A84, Unscaled Output Image UV Plane Start Address Register
REG_UOS                       reg_uos                       ; // 0x0A88, Unscaled Output Image Stride Register
REG_UOPGM                     reg_uopgm                     ; // 0x0A8C, Unscaled Output Pixel Coordinate Generator Mode Register
REG_UOAXI                     reg_uoaxi                     ; // 0x0A90, Unscaled Output AXI Control Register
REG_SS0AY                     reg_ss0ay                     ; // 0x0A94, SS0 Output Image Y Plane Start Address Register
REG_SS0AUV                    reg_ss0auv                    ; // 0x0A98, SS0 Output Image UV Plane Start Address Register
REG_SS0S                      reg_ss0s                      ; // 0x0A9C, SS0 Output Image Stride Register
REG_SS0HF                     reg_ss0hf                     ; // 0x0AA0, SS0 H Scaling Factor Register
REG_SS0VF                     reg_ss0vf                     ; // 0x0AA4, SS0 V Scaling Factor Register
REG_SS0IW                     reg_ss0iw                     ; // 0x0AA8, SS0 Output Image Size Register
REG_SS1AY                     reg_ss1ay                     ; // 0x0AAC, SS1 Output Image Y Plane Start Address Register
REG_SS1AUV                    reg_ss1auv                    ; // 0x0AB0, SS1 Output Image UV Plane Start Address Register
REG_SS1S                      reg_ss1s                      ; // 0x0AB4, SS1 Output Image Stride Register
REG_SS1HF                     reg_ss1hf                     ; // 0x0AB8, SS1 H Scaling Factor Register
REG_SS1VF                     reg_ss1vf                     ; // 0x0ABC, SS1 V Scaling Factor Register
REG_SS1IW                     reg_ss1iw                     ; // 0x0AC0, SS1 Output Image Size Register
REG_SSAXI                     reg_ssaxi                     ; // 0x0AC4, SS AXI Control Register
REG_ITIIWSR                   reg_itiiwsr                   ; // 0x0B20, ITI image window size register
REG_ITIDWLSR                  reg_itidwlsr                  ; // 0x0B24, ITI DRAM write line stride register
REG_ITIDWYSAR                 reg_itidwysar                 ; // 0x0B28, ITI DRAM write Y start address register
REG_ITIDWUSAR                 reg_itidwusar                 ; // 0x0B2C, ITI DRAM write UV start address register
REG_ITIDRYSAR                 reg_itidrysar                 ; // 0x0B30, ITI DRAM read Y start address register
REG_ITIDRUSAR                 reg_itidrusar                 ; // 0x0B34, ITI DRAM read UV start address register
REG_ITIPDFR                   reg_itipdfr                   ; // 0x0B38, ITI package data format register
REG_ITIDRLSR                  reg_itidrlsr                  ; // 0x0B3C, ITI DRAM read line stride register
REG_ITIBSR                    reg_itibsr                    ; // 0x0B40, ISP tiling interface BUSY status register
REG_ITIAIR                    reg_itiair                    ; // 0x0B44, ISP tiling interface AXI ID register
REG_ITIDPSR                   reg_itidpsr                   ; // 0x0B48, ISP tiling interface data path select register
REG_DNYUV_YSWR0               reg_dnyuv_yswr0               ; // 0x0C00, DNYUV Y channel S weight table register 0
REG_DNYUV_YSWR1               reg_dnyuv_yswr1               ; // 0x0C04, DNYUV Y channel S weight table register 1
REG_DNYUV_CSWR0               reg_dnyuv_cswr0               ; // 0x0C08, DNYUV UV channel S weight table register 0
REG_DNYUV_CSWR1               reg_dnyuv_cswr1               ; // 0x0C0C, DNYUV UV channel S weight table register  1
REG_DNYUV_YDR0                reg_dnyuv_ydr0                ; // 0x0C10, DNYUV Y Curve D component register 0
REG_DNYUV_YDR1                reg_dnyuv_ydr1                ; // 0x0C14, DNYUV Y Curve D component register 1
REG_DNYUV_YDR2                reg_dnyuv_ydr2                ; // 0x0C18, DNYUV Y Curve D component register 2
REG_DNYUV_CDR0                reg_dnyuv_cdr0                ; // 0x0C1C, DNYUV UV Curve D component register 0
REG_DNYUV_CDR1                reg_dnyuv_cdr1                ; // 0x0C20, DNYUV UV Curve D component register 1
REG_DNYUV_CDR2                reg_dnyuv_cdr2                ; // 0x0C24, DNYUV UV Curve D component register 2
REG_ICAMD_0                   reg_icamd_0                   ; // 0x0C40, Color correction matrix register
REG_ICAMD_1                   reg_icamd_1                   ; // 0x0C44, Color correction matrix Register 
REG_ICAMD_2                   reg_icamd_2                   ; // 0x0C48, Color correction matrix Register 
REG_ICAMD_3                   reg_icamd_3                   ; // 0x0C4C, Color correction matrix Register 
REG_ICAMD_4                   reg_icamd_4                   ; // 0x0C50, Color correction matrix Register 
REG_ICAMD_5                   reg_icamd_5                   ; // 0x0C54, Color correction matrix Register 
REG_ICAMD_6                   reg_icamd_6                   ; // 0x0C58, Color correction matrix Register 
REG_ICAMD_7                   reg_icamd_7                   ; // 0x0C5C, Color correction matrix Register 
REG_ICAMD_8                   reg_icamd_8                   ; // 0x0C60, Color correction matrix Register 
REG_ICAMD_9                   reg_icamd_9                   ; // 0x0C64, Color correction matrix Register 
REG_ICAMD_10                  reg_icamd_10                  ; // 0x0C68, Color correction matrix Register 
REG_ICAMD_11                  reg_icamd_11                  ; // 0x0C6C, Color correction matrix Register 
REG_ICAMD_12                  reg_icamd_12                  ; // 0x0C70, Color correction matrix Register 
REG_ICAMD_13                  reg_icamd_13                  ; // 0x0C74, Color correction matrix Register 
REG_ICAMD_14                  reg_icamd_14                  ; // 0x0C78, Color correction matrix Register 
REG_ICAMD_15                  reg_icamd_15                  ; // 0x0C7C, Color correction matrix Register 
REG_ICAMD_16                  reg_icamd_16                  ; // 0x0C80, Color correction matrix Register 
REG_ICAMD_17                  reg_icamd_17                  ; // 0x0C84, Color correction matrix Register 
REG_ICAMD_18                  reg_icamd_18                  ; // 0x0C88, Color correction matrix Register 
REG_ICAMD_19                  reg_icamd_19                  ; // 0x0C8C, Color correction matrix Register 
REG_ICAMD_20                  reg_icamd_20                  ; // 0x0C90, Color correction matrix Register 
REG_ICAMD_21                  reg_icamd_21                  ; // 0x0C94, Color correction matrix Register 
REG_ICAMD_22                  reg_icamd_22                  ; // 0x0C98, Color correction matrix Register 
REG_ICAMD_23                  reg_icamd_23                  ; // 0x0C9C, Color correction matrix Register 
REG_ICAMD_24                  reg_icamd_24                  ; // 0x0CA0, Color correction matrix Register 24, dth
REG_ICAMD_25                  reg_icamd_25                  ; // 0x0CA4, Color correction matrix Register 25, th1
REG_YHIST_CFG_0               reg_yhist_cfg_0               ; // 0x0CC8, Y Histogram Start Location Register
REG_YHIST_CFG_1               reg_yhist_cfg_1               ; // 0x0CCC, Y Histogram Size Register
REG_YHIST_CFG_2               reg_yhist_cfg_2               ; // 0x0CD0, Y Histogram Decimation Register
REG_YHIST_CFG_3               reg_yhist_cfg_3               ; // 0x0CD4, Y Histogram mux select register
REG_YHIST_CFG_4               reg_yhist_cfg_4               ; // 0x0CD8, Y histogram dumping base address 
REG_YHIST_ACC_0               reg_yhist_acc_0               ; // 0x0D00, Y Histogram result register 0
REG_YHIST_ACC_1               reg_yhist_acc_1               ; // 0x0D04, Y Histogram result register 
REG_YHIST_ACC_2               reg_yhist_acc_2               ; // 0x0D08, Y Histogram result register 
REG_YHIST_ACC_3               reg_yhist_acc_3               ; // 0x0D0C, Y Histogram result register 
REG_YHIST_ACC_4               reg_yhist_acc_4               ; // 0x0D10, Y Histogram result register 
REG_YHIST_ACC_5               reg_yhist_acc_5               ; // 0x0D14, Y Histogram result register 
REG_YHIST_ACC_6               reg_yhist_acc_6               ; // 0x0D18, Y Histogram result register 
REG_YHIST_ACC_7               reg_yhist_acc_7               ; // 0x0D1C, Y Histogram result register 
REG_YHIST_ACC_8               reg_yhist_acc_8               ; // 0x0D20, Y Histogram result register 
REG_YHIST_ACC_9               reg_yhist_acc_9               ; // 0x0D24, Y Histogram result register 
REG_YHIST_ACC_10              reg_yhist_acc_10              ; // 0x0D28, Y Histogram result register 
REG_YHIST_ACC_11              reg_yhist_acc_11              ; // 0x0D2C, Y Histogram result register 
REG_YHIST_ACC_12              reg_yhist_acc_12              ; // 0x0D30, Y Histogram result register 
REG_YHIST_ACC_13              reg_yhist_acc_13              ; // 0x0D34, Y Histogram result register 
REG_YHIST_ACC_14              reg_yhist_acc_14              ; // 0x0D38, Y Histogram result register 
REG_YHIST_ACC_15              reg_yhist_acc_15              ; // 0x0D3C, Y Histogram result register 
REG_YHIST_ACC_16              reg_yhist_acc_16              ; // 0x0D40, Y Histogram result register 
REG_YHIST_ACC_17              reg_yhist_acc_17              ; // 0x0D44, Y Histogram result register 
REG_YHIST_ACC_18              reg_yhist_acc_18              ; // 0x0D48, Y Histogram result register 
REG_YHIST_ACC_19              reg_yhist_acc_19              ; // 0x0D4C, Y Histogram result register 
REG_YHIST_ACC_20              reg_yhist_acc_20              ; // 0x0D50, Y Histogram result register 
REG_YHIST_ACC_21              reg_yhist_acc_21              ; // 0x0D54, Y Histogram result register 
REG_YHIST_ACC_22              reg_yhist_acc_22              ; // 0x0D58, Y Histogram result register 
REG_YHIST_ACC_23              reg_yhist_acc_23              ; // 0x0D5C, Y Histogram result register 
REG_YHIST_ACC_24              reg_yhist_acc_24              ; // 0x0D60, Y Histogram result register 
REG_YHIST_ACC_25              reg_yhist_acc_25              ; // 0x0D64, Y Histogram result register 
REG_YHIST_ACC_26              reg_yhist_acc_26              ; // 0x0D68, Y Histogram result register 
REG_YHIST_ACC_27              reg_yhist_acc_27              ; // 0x0D6C, Y Histogram result register 
REG_YHIST_ACC_28              reg_yhist_acc_28              ; // 0x0D70, Y Histogram result register 
REG_YHIST_ACC_29              reg_yhist_acc_29              ; // 0x0D74, Y Histogram result register 
REG_YHIST_ACC_30              reg_yhist_acc_30              ; // 0x0D78, Y Histogram result register 
REG_YHIST_ACC_31              reg_yhist_acc_31              ; // 0x0D7C, Y Histogram result register 
REG_YHIST_ACC_32              reg_yhist_acc_32              ; // 0x0D80, Y Histogram result register 
REG_YHIST_ACC_33              reg_yhist_acc_33              ; // 0x0D84, Y Histogram result register 
REG_YHIST_ACC_34              reg_yhist_acc_34              ; // 0x0D88, Y Histogram result register 
REG_YHIST_ACC_35              reg_yhist_acc_35              ; // 0x0D8C, Y Histogram result register 
REG_YHIST_ACC_36              reg_yhist_acc_36              ; // 0x0D90, Y Histogram result register 
REG_YHIST_ACC_37              reg_yhist_acc_37              ; // 0x0D94, Y Histogram result register 
REG_YHIST_ACC_38              reg_yhist_acc_38              ; // 0x0D98, Y Histogram result register 
REG_YHIST_ACC_39              reg_yhist_acc_39              ; // 0x0D9C, Y Histogram result register 
REG_YHIST_ACC_40              reg_yhist_acc_40              ; // 0x0DA0, Y Histogram result register 
REG_YHIST_ACC_41              reg_yhist_acc_41              ; // 0x0DA4, Y Histogram result register 
REG_YHIST_ACC_42              reg_yhist_acc_42              ; // 0x0DA8, Y Histogram result register 
REG_YHIST_ACC_43              reg_yhist_acc_43              ; // 0x0DAC, Y Histogram result register 
REG_YHIST_ACC_44              reg_yhist_acc_44              ; // 0x0DB0, Y Histogram result register 
REG_YHIST_ACC_45              reg_yhist_acc_45              ; // 0x0DB4, Y Histogram result register 
REG_YHIST_ACC_46              reg_yhist_acc_46              ; // 0x0DB8, Y Histogram result register 
REG_YHIST_ACC_47              reg_yhist_acc_47              ; // 0x0DBC, Y Histogram result register 
REG_YHIST_ACC_48              reg_yhist_acc_48              ; // 0x0DC0, Y Histogram result register 
REG_YHIST_ACC_49              reg_yhist_acc_49              ; // 0x0DC4, Y Histogram result register 
REG_YHIST_ACC_50              reg_yhist_acc_50              ; // 0x0DC8, Y Histogram result register 
REG_YHIST_ACC_51              reg_yhist_acc_51              ; // 0x0DCC, Y Histogram result register 
REG_YHIST_ACC_52              reg_yhist_acc_52              ; // 0x0DD0, Y Histogram result register 
REG_YHIST_ACC_53              reg_yhist_acc_53              ; // 0x0DD4, Y Histogram result register 
REG_YHIST_ACC_54              reg_yhist_acc_54              ; // 0x0DD8, Y Histogram result register 
REG_YHIST_ACC_55              reg_yhist_acc_55              ; // 0x0DDC, Y Histogram result register 
REG_YHIST_ACC_56              reg_yhist_acc_56              ; // 0x0DE0, Y Histogram result register 
REG_YHIST_ACC_57              reg_yhist_acc_57              ; // 0x0DE4, Y Histogram result register 
REG_YHIST_ACC_58              reg_yhist_acc_58              ; // 0x0DE8, Y Histogram result register 
REG_YHIST_ACC_59              reg_yhist_acc_59              ; // 0x0DEC, Y Histogram result register 
REG_YHIST_ACC_60              reg_yhist_acc_60              ; // 0x0DF0, Y Histogram result register 
REG_YHIST_ACC_61              reg_yhist_acc_61              ; // 0x0DF4, Y Histogram result register 
REG_YHIST_ACC_62              reg_yhist_acc_62              ; // 0x0DF8, Y Histogram result register 
REG_YHIST_ACC_63              reg_yhist_acc_63              ; // 0x0DFC, Y Histogram result register 
REG_IGRVAL_0                  reg_igrval_0                  ; // 0x0E00, RGB Gamma table Register 0
REG_IGRVAL_1                  reg_igrval_1                  ; // 0x0E04, RGB Gamma table Register 1
REG_IGRVAL_2                  reg_igrval_2                  ; // 0x0E08, RGB Gamma table Register 2
REG_IGRVAL_3                  reg_igrval_3                  ; // 0x0E0C, RGB Gamma table Register 3
REG_IGRVAL_4                  reg_igrval_4                  ; // 0x0E10, RGB Gamma table Register 4
REG_IGRVAL_5                  reg_igrval_5                  ; // 0x0E14, RGB Gamma table Register 5
REG_IGRVAL_6                  reg_igrval_6                  ; // 0x0E18, RGB Gamma table Register 6
REG_IGRVAL_7                  reg_igrval_7                  ; // 0x0E1C, RGB Gamma table Register 7
REG_IGRVAL_8                  reg_igrval_8                  ; // 0x0E20, RGB Gamma table Register 8
REG_IGRVAL_9                  reg_igrval_9                  ; // 0x0E24, RGB Gamma table Register 9
REG_IGRVAL_10                 reg_igrval_10                 ; // 0x0E28, RGB Gamma table Register 10
REG_IGRVAL_11                 reg_igrval_11                 ; // 0x0E2C, RGB Gamma table Register 11
REG_IGRVAL_12                 reg_igrval_12                 ; // 0x0E30, RGB Gamma table Register 12
REG_IGRVAL_13                 reg_igrval_13                 ; // 0x0E34, RGB Gamma table Register 13
REG_IGRVAL_14                 reg_igrval_14                 ; // 0x0E38, RGB Gamma table Register 14
REG_ICCONV_0                  reg_icconv_0                  ; // 0x0E40, RGB to YUV color space conversion Register
REG_ICCONV_1                  reg_icconv_1                  ; // 0x0E44, RGB to YUV color space conversion Register
REG_ICCONV_2                  reg_icconv_2                  ; // 0x0E48, RGB to YUV color space conversion Register
REG_ICCONV_3                  reg_icconv_3                  ; // 0x0E4C, RGB to YUV color space conversion Register
REG_ICCONV_4                  reg_icconv_4                  ; // 0x0E50, RGB to YUV color space conversion Register
REG_ICCONV_5                  reg_icconv_5                  ; // 0x0E54, RGB to YUV color space conversion Register
REG_ICCONV_6                  reg_icconv_6                  ; // 0x0E58, RGB to YUV color space conversion Register
REG_ICCONV_7                  reg_icconv_7                  ; // 0x0E5C, RGB to YUV color space conversion Register
REG_ICCONV_8                  reg_icconv_8                  ; // 0x0E60, RGB to YUV color space conversion Register
REG_ISHRP1_0                  reg_ishrp1_0                  ; // 0x0E80, Sharpen Edge Amplification Weight and Difference 0
REG_ISHRP1_1                  reg_ishrp1_1                  ; // 0x0E84, Sharpen Edge Amplification Weight and Difference 1
REG_ISHRP1_2                  reg_ishrp1_2                  ; // 0x0E88, Sharpen Edge Amplification Weight and Difference 2
REG_ISHRP1_3                  reg_ishrp1_3                  ; // 0x0E8C, Sharpen Edge Amplification Weight and Difference 3
REG_ISHRP1_4                  reg_ishrp1_4                  ; // 0x0E90, Sharpen Edge Amplification Weight and Difference 4
REG_ISHRP1_5                  reg_ishrp1_5                  ; // 0x0E94, Sharpen Edge Amplification Weight and Difference 5
REG_ISHRP1_6                  reg_ishrp1_6                  ; // 0x0E98, Sharpen Edge Amplification Weight and Difference 6
REG_ISHRP1_7                  reg_ishrp1_7                  ; // 0x0E9C, Sharpen Edge Amplification Weight and Difference 7
REG_ISHRP1_8                  reg_ishrp1_8                  ; // 0x0EA0, Sharpen Edge Amplification Weight and Difference 8
REG_ISHRP1_9                  reg_ishrp1_9                  ; // 0x0EA4, Sharpen Edge Amplification Weight and Difference 9
REG_ISHRP1_10                 reg_ishrp1_10                 ; // 0x0EA8, Sharpen Edge Amplification Weight and Difference 10
REG_ISHRP1_11                 reg_ishrp1_11                 ; // 0x0EAC, Sharpen Edge Amplification Weight and Difference 11
REG_ISHRP1_12                 reg_ishrp1_12                 ; // 0x0EB0, Sharpen Edge Amplification Weight and Difference 12
REG_ISHRP1_13                 reg_ishrp1_13                 ; // 0x0EB4, Sharpen Edge Amplification Weight and Difference 13
REG_ISHRP1_14                 reg_ishrp1_14                 ; // 0x0EB8, Sharpen Edge Amplification Weight and Difference 14
REG_ISHRP2_0                  reg_ishrp2_0                  ; // 0x0EBC, Sharpen Edge Amplification Factor and Slope 0
REG_ISHRP2_1                  reg_ishrp2_1                  ; // 0x0EC0, Sharpen Edge Amplification Factor and Slope 1
REG_ISHRP2_2                  reg_ishrp2_2                  ; // 0x0EC4, Sharpen Edge Amplification Factor and Slope 2
REG_ISHRP2_3                  reg_ishrp2_3                  ; // 0x0EC8, Sharpen Edge Amplification Factor and Slope 3
REG_ISHRP2_4                  reg_ishrp2_4                  ; // 0x0ECC, Sharpen Edge Amplification Factor and Slope 4
REG_ISHRP2_5                  reg_ishrp2_5                  ; // 0x0ED0, Sharpen Edge Amplification Factor and Slope 5
REG_ISHRP3                    reg_ishrp3                    ; // 0x0ED4, Sharpen Edge Amplification Weight Normalization
REG_IUVS1                     reg_iuvs1                     ; // 0x0ED8, UV smoothing Register 1
REG_IUVS2                     reg_iuvs2                     ; // 0x0EDC, UV smoothing Register 2
REG_IUVCKS1                   reg_iuvcks1                   ; // 0x0EE0, UV Color Kill Register 1
REG_IUVCKS2                   reg_iuvcks2                   ; // 0x0EE4, UV Color Kill Register 2
REG_ISHRPET                   reg_ishrpet                   ; // 0x0EE8, Sharpen Edge Threshold
REG_YCURVE_0                  reg_ycurve_0                  ; // 0x0F00, Y Curve PARAM table Register 0
REG_YCURVE_1                  reg_ycurve_1                  ; // 0x0F04, Y Curve PARAM table Register 
REG_YCURVE_2                  reg_ycurve_2                  ; // 0x0F08, Y Curve PARAM table Register 
REG_YCURVE_3                  reg_ycurve_3                  ; // 0x0F0C, Y Curve PARAM table Register 
REG_YCURVE_4                  reg_ycurve_4                  ; // 0x0F10, Y Curve PARAM table Register 
REG_YCURVE_5                  reg_ycurve_5                  ; // 0x0F14, Y Curve PARAM table Register 
REG_YCURVE_6                  reg_ycurve_6                  ; // 0x0F18, Y Curve PARAM table Register 
REG_YCURVE_7                  reg_ycurve_7                  ; // 0x0F1C, Y Curve PARAM table Register 
REG_YCURVE_8                  reg_ycurve_8                  ; // 0x0F20, Y Curve PARAM table Register 
REG_YCURVE_9                  reg_ycurve_9                  ; // 0x0F24, Y Curve PARAM table Register 
REG_YCURVE_10                 reg_ycurve_10                 ; // 0x0F28, Y Curve PARAM table Register 
REG_YCURVE_11                 reg_ycurve_11                 ; // 0x0F2C, Y Curve PARAM table Register 
REG_YCURVE_12                 reg_ycurve_12                 ; // 0x0F30, Y Curve PARAM table Register 
REG_YCURVE_13                 reg_ycurve_13                 ; // 0x0F34, Y Curve PARAM table Register 
REG_YCURVE_14                 reg_ycurve_14                 ; // 0x0F38, Y Curve PARAM table Register 
REG_YCURVE_15                 reg_ycurve_15                 ; // 0x0F3C, Y Curve PARAM table Register 
REG_YCURVE_16                 reg_ycurve_16                 ; // 0x0F40, Y Curve PARAM table Register 
REG_YCURVE_17                 reg_ycurve_17                 ; // 0x0F44, Y Curve PARAM table Register 
REG_YCURVE_18                 reg_ycurve_18                 ; // 0x0F48, Y Curve PARAM table Register 
REG_YCURVE_19                 reg_ycurve_19                 ; // 0x0F4C, Y Curve PARAM table Register 
REG_YCURVE_20                 reg_ycurve_20                 ; // 0x0F50, Y Curve PARAM table Register 
REG_YCURVE_21                 reg_ycurve_21                 ; // 0x0F54, Y Curve PARAM table Register 
REG_YCURVE_22                 reg_ycurve_22                 ; // 0x0F58, Y Curve PARAM table Register 
REG_YCURVE_23                 reg_ycurve_23                 ; // 0x0F5C, Y Curve PARAM table Register 
REG_YCURVE_24                 reg_ycurve_24                 ; // 0x0F60, Y Curve PARAM table Register 
REG_YCURVE_25                 reg_ycurve_25                 ; // 0x0F64, Y Curve PARAM table Register 
REG_YCURVE_26                 reg_ycurve_26                 ; // 0x0F68, Y Curve PARAM table Register 
REG_YCURVE_27                 reg_ycurve_27                 ; // 0x0F6C, Y Curve PARAM table Register 
REG_YCURVE_28                 reg_ycurve_28                 ; // 0x0F70, Y Curve PARAM table Register 
REG_YCURVE_29                 reg_ycurve_29                 ; // 0x0F74, Y Curve PARAM table Register 
REG_YCURVE_30                 reg_ycurve_30                 ; // 0x0F78, Y Curve PARAM table Register 
REG_YCURVE_31                 reg_ycurve_31                 ; // 0x0F7C, Y Curve PARAM table Register 
REG_YCURVE_32                 reg_ycurve_32                 ; // 0x0F80, Y Curve PARAM table Register 
REG_YCURVE_33                 reg_ycurve_33                 ; // 0x0F84, Y Curve PARAM table Register 
REG_YCURVE_34                 reg_ycurve_34                 ; // 0x0F88, Y Curve PARAM table Register 
REG_YCURVE_35                 reg_ycurve_35                 ; // 0x0F8C, Y Curve PARAM table Register 
REG_YCURVE_36                 reg_ycurve_36                 ; // 0x0F90, Y Curve PARAM table Register 
REG_YCURVE_37                 reg_ycurve_37                 ; // 0x0F94, Y Curve PARAM table Register 
REG_YCURVE_38                 reg_ycurve_38                 ; // 0x0F98, Y Curve PARAM table Register 
REG_YCURVE_39                 reg_ycurve_39                 ; // 0x0F9C, Y Curve PARAM table Register 
REG_YCURVE_40                 reg_ycurve_40                 ; // 0x0FA0, Y Curve PARAM table Register 
REG_YCURVE_41                 reg_ycurve_41                 ; // 0x0FA4, Y Curve PARAM table Register 
REG_YCURVE_42                 reg_ycurve_42                 ; // 0x0FA8, Y Curve PARAM table Register 
REG_YCURVE_43                 reg_ycurve_43                 ; // 0x0FAC, Y Curve PARAM table Register 
REG_YCURVE_44                 reg_ycurve_44                 ; // 0x0FB0, Y Curve PARAM table Register 
REG_YCURVE_45                 reg_ycurve_45                 ; // 0x0FB4, Y Curve PARAM table Register 
REG_YCURVE_46                 reg_ycurve_46                 ; // 0x0FB8, Y Curve PARAM table Register 
REG_YCURVE_47                 reg_ycurve_47                 ; // 0x0FBC, Y Curve PARAM table Register 
REG_YCURVE_48                 reg_ycurve_48                 ; // 0x0FC0, Y Curve PARAM table Register 
REG_YCURVE_49                 reg_ycurve_49                 ; // 0x0FC4, Y Curve PARAM table Register 
REG_YCURVE_50                 reg_ycurve_50                 ; // 0x0FC8, Y Curve PARAM table Register 
REG_YCURVE_51                 reg_ycurve_51                 ; // 0x0FCC, Y Curve PARAM table Register 
REG_YCURVE_52                 reg_ycurve_52                 ; // 0x0FD0, Y Curve PARAM table Register 
REG_YCURVE_53                 reg_ycurve_53                 ; // 0x0FD4, Y Curve PARAM table Register 
REG_YCURVE_54                 reg_ycurve_54                 ; // 0x0FD8, Y Curve PARAM table Register 
REG_YCURVE_55                 reg_ycurve_55                 ; // 0x0FDC, Y Curve PARAM table Register 
REG_YCURVE_56                 reg_ycurve_56                 ; // 0x0FE0, Y Curve PARAM table Register 
REG_YCURVE_57                 reg_ycurve_57                 ; // 0x0FE4, Y Curve PARAM table Register 
REG_YCURVE_58                 reg_ycurve_58                 ; // 0x0FE8, Y Curve PARAM table Register 
REG_YCURVE_59                 reg_ycurve_59                 ; // 0x0FEC, Y Curve PARAM table Register 
REG_YCURVE_60                 reg_ycurve_60                 ; // 0x0FF0, Y Curve PARAM table Register 
REG_YCURVE_61                 reg_ycurve_61                 ; // 0x0FF4, Y Curve PARAM table Register 
REG_YCURVE_62                 reg_ycurve_62                 ; // 0x0FF8, Y Curve PARAM table Register 
REG_YCURVE_63                 reg_ycurve_63                 ; // 0x0FFC, Y Curve PARAM table Register 63
REG_NL3DGSIGMAX0              reg_nl3dgsigmax0              ; // 0x1020, NL3D G SIGMA X Register 0
REG_NL3DGSIGMAX1              reg_nl3dgsigmax1              ; // 0x1024, NL3D G SIGMA X Register 1
REG_NL3DGSIGMAX2              reg_nl3dgsigmax2              ; // 0x1028, NL3D G SIGMA X Register 2
REG_NL3DGSIGMAX3              reg_nl3dgsigmax3              ; // 0x102C, NL3D G SIGMA X Register 3
REG_NL3DGSIGMAX4              reg_nl3dgsigmax4              ; // 0x1030, NL3D G SIGMA X Register 4
REG_NL3DGSIGMAX5              reg_nl3dgsigmax5              ; // 0x1034, NL3D G SIGMA X Register 5
REG_NL3DGSIGMAX6              reg_nl3dgsigmax6              ; // 0x1038, NL3D G SIGMA X Register 6
REG_NL3DGSIGMAX7              reg_nl3dgsigmax7              ; // 0x103C, NL3D G SIGMA X Register 7
REG_NL3DGSIGMAY0              reg_nl3dgsigmay0              ; // 0x10A0, NL3D G SIGMA Y Register 0
REG_NL3DGSIGMAY1              reg_nl3dgsigmay1              ; // 0x10A4, NL3D G SIGMA Y Register 1
REG_NL3DGSIGMAY2              reg_nl3dgsigmay2              ; // 0x10A8, NL3D G SIGMA Y Register 2
REG_NL3DGSIGMAY3              reg_nl3dgsigmay3              ; // 0x10AC, NL3D G SIGMA Y Register 3
REG_NL3DGSIGMAY4              reg_nl3dgsigmay4              ; // 0x10B0, NL3D G SIGMA Y Register 4
REG_NL3DGSIGMAY5              reg_nl3dgsigmay5              ; // 0x10B4, NL3D G SIGMA Y Register 5
REG_NL3DGSIGMAY6              reg_nl3dgsigmay6              ; // 0x10B8, NL3D G SIGMA Y Register 6
REG_NL3DGSIGMAY7              reg_nl3dgsigmay7              ; // 0x10BC, NL3D G SIGMA Y Register 7
REG_NL3DGSIGMAY8              reg_nl3dgsigmay8              ; // 0x10C0, NL3D G SIGMA Y Register 8
REG_NL3DGSIGMAY9              reg_nl3dgsigmay9              ; // 0x10C4, NL3D G SIGMA Y Register 9
REG_NL3DGSIGMAY10             reg_nl3dgsigmay10             ; // 0x10C8, NL3D G SIGMA Y Register 10
REG_NL3DGSIGMAY11             reg_nl3dgsigmay11             ; // 0x10CC, NL3D G SIGMA Y Register 11
REG_NL3DGSIGMAY12             reg_nl3dgsigmay12             ; // 0x10D0, NL3D G SIGMA Y Register 12
REG_NL3DGSIGMAY13             reg_nl3dgsigmay13             ; // 0x10D4, NL3D G SIGMA Y Register 13
REG_NL3DGSIGMAY14             reg_nl3dgsigmay14             ; // 0x10D8, NL3D G SIGMA Y Register 14
REG_NL3DGSIGMAY15             reg_nl3dgsigmay15             ; // 0x10DC, NL3D G SIGMA Y Register 15
REG_NL3DGSIGMAS0              reg_nl3dgsigmas0              ; // 0x1140, NL3D G SIGMA S Register 0
REG_NL3DGSIGMAS1              reg_nl3dgsigmas1              ; // 0x1144, NL3D G SIGMA S Register 1
REG_NL3DGSIGMAS2              reg_nl3dgsigmas2              ; // 0x1148, NL3D G SIGMA S Register 2
REG_NL3DGSIGMAS3              reg_nl3dgsigmas3              ; // 0x114C, NL3D G SIGMA S Register 3
REG_NL3DGSIGMAS4              reg_nl3dgsigmas4              ; // 0x1150, NL3D G SIGMA S Register 4
REG_NL3DGSIGMAS5              reg_nl3dgsigmas5              ; // 0x1154, NL3D G SIGMA S Register 5
REG_NL3DGSIGMAS6              reg_nl3dgsigmas6              ; // 0x1158, NL3D G SIGMA S Register 6
REG_NL3DGSIGMAS7              reg_nl3dgsigmas7              ; // 0x115C, NL3D G SIGMA S Register 7
REG_NL3DGFILTPARX0            reg_nl3dgfiltparx0            ; // 0x11A0, NL3D G FILTPAR X Register 0
REG_NL3DGFILTPARX1            reg_nl3dgfiltparx1            ; // 0x11A4, NL3D G FILTPAR X Register 1
REG_NL3DGFILTPARX2            reg_nl3dgfiltparx2            ; // 0x11A8, NL3D G FILTPAR X Register 2
REG_NL3DGFILTPARX3            reg_nl3dgfiltparx3            ; // 0x11AC, NL3D G FILTPAR X Register 3
REG_NL3DGFILTPARX4            reg_nl3dgfiltparx4            ; // 0x11B0, NL3D G FILTPAR X Register 4
REG_NL3DGFILTPARX5            reg_nl3dgfiltparx5            ; // 0x11B4, NL3D G FILTPAR X Register 5
REG_NL3DGFILTPARX6            reg_nl3dgfiltparx6            ; // 0x11B8, NL3D G FILTPAR X Register 6
REG_NL3DGFILTPARX7            reg_nl3dgfiltparx7            ; // 0x11BC, NL3D G FILTPAR X Register 7
REG_NL3DGFILTPARY0            reg_nl3dgfiltpary0            ; // 0x1220, NL3D G FILTPAR Y Register 0
REG_NL3DGFILTPARY1            reg_nl3dgfiltpary1            ; // 0x1224, NL3D G FILTPAR Y Register 1
REG_NL3DGFILTPARY2            reg_nl3dgfiltpary2            ; // 0x1228, NL3D G FILTPAR Y Register 2
REG_NL3DGFILTPARY3            reg_nl3dgfiltpary3            ; // 0x122C, NL3D G FILTPAR Y Register 3
REG_NL3DGFILTPARY4            reg_nl3dgfiltpary4            ; // 0x1230, NL3D G FILTPAR Y Register 4
REG_NL3DGFILTPARY5            reg_nl3dgfiltpary5            ; // 0x1234, NL3D G FILTPAR Y Register 5
REG_NL3DGFILTPARY6            reg_nl3dgfiltpary6            ; // 0x1238, NL3D G FILTPAR Y Register 6
REG_NL3DGFILTPARY7            reg_nl3dgfiltpary7            ; // 0x123C, NL3D G FILTPAR Y Register 7
REG_NL3DGFILTPARY8            reg_nl3dgfiltpary8            ; // 0x1240, NL3D G FILTPAR Y Register 8
REG_NL3DGFILTPARY9            reg_nl3dgfiltpary9            ; // 0x1244, NL3D G FILTPAR Y Register 9
REG_NL3DGFILTPARY10           reg_nl3dgfiltpary10           ; // 0x1248, NL3D G FILTPAR Y Register 10
REG_NL3DGFILTPARY11           reg_nl3dgfiltpary11           ; // 0x124C, NL3D G FILTPAR Y Register 11
REG_NL3DGFILTPARY12           reg_nl3dgfiltpary12           ; // 0x1250, NL3D G FILTPAR Y Register 12
REG_NL3DGFILTPARY13           reg_nl3dgfiltpary13           ; // 0x1254, NL3D G FILTPAR Y Register 13
REG_NL3DGFILTPARY14           reg_nl3dgfiltpary14           ; // 0x1258, NL3D G FILTPAR Y Register 14
REG_NL3DGFILTPARY15           reg_nl3dgfiltpary15           ; // 0x125C, NL3D G FILTPAR Y Register 15
REG_NL3DGFILTPARS0            reg_nl3dgfiltpars0            ; // 0x12C0, NL3D G FILTPAR S Register 0
REG_NL3DGFILTPARS1            reg_nl3dgfiltpars1            ; // 0x12C4, NL3D G FILTPAR S Register 1
REG_NL3DGFILTPARS2            reg_nl3dgfiltpars2            ; // 0x12C8, NL3D G FILTPAR S Register 2
REG_NL3DGFILTPARS3            reg_nl3dgfiltpars3            ; // 0x12CC, NL3D G FILTPAR S Register 3
REG_NL3DGFILTPARS4            reg_nl3dgfiltpars4            ; // 0x12D0, NL3D G FILTPAR S Register 4
REG_NL3DGFILTPARS5            reg_nl3dgfiltpars5            ; // 0x12D4, NL3D G FILTPAR S Register 5
REG_NL3DGFILTPARS6            reg_nl3dgfiltpars6            ; // 0x12D8, NL3D G FILTPAR S Register 6
REG_NL3DGFILTPARS7            reg_nl3dgfiltpars7            ; // 0x12DC, NL3D G FILTPAR S Register 7
REG_NL3DCFG                   reg_nl3dcfg                   ; // 0x1300, NL 3D CFG Register
REG_DNRIAY                    reg_dnriay                    ; // 0x1304, DN Reference Input Image Y Plane Start Address Register
REG_DNRFBDCAR                 reg_dnrfbdcar                 ; // 0x1308, FBDC axi read address status register
REG_DNRIS                     reg_dnris                     ; // 0x130C, DN Reference Input Image Stride Register, no use
REG_DNROAY                    reg_dnroay                    ; // 0x1310, DN Reference Output Image Y Plane Start Address Register
REG_DNRCC2                    reg_dnrcc2                    ; // 0x1314, DN Reference Buffer Compression Control Register 2
REG_DNRCC3                    reg_dnrcc3                    ; // 0x1318, DN Reference Buffer Compression Control Register 3
REG_DNRISZ                    reg_dnrisz                    ; // 0x131C, DN Reference Input Buffer Size Register, byte unit
REG_DNROSZ                    reg_dnrosz                    ; // 0x1320, DN Reference Output Buffer Size Register, byte unit
REG_DNRCC                     reg_dnrcc                     ; // 0x1324, DN Reference Buffer Compression Control Register
REG_DNRCC1                    reg_dnrcc1                    ; // 0x1328, DN Reference Buffer Compression Control Register 1
REG_DNRCS                     reg_dnrcs                     ; // 0x132C, DN Reference Buffer Compression Status Register
REG_DNRCL                     reg_dnrcl                     ; // 0x1330, DN Reference Buffer Compression had used the max buffer length.
REG_NL3D_W2D1R                reg_nl3d_w2d1r                ; // 0x1334, NL3D 1st 2D filter weight table regsiter
REG_NL3D_D2D1R0               reg_nl3d_d2d1r0               ; // 0x1338, NL3D 1st 2D filter difference table regsiter for R
REG_NL3D_D2D1R1               reg_nl3d_d2d1r1               ; // 0x133C, NL3D 1st 2D filter difference table regsiter for R
REG_NL3D_D2D1G0               reg_nl3d_d2d1g0               ; // 0x1340, NL3D 1st 2D filter difference table regsiter for G
REG_NL3D_D2D1G1               reg_nl3d_d2d1g1               ; // 0x1344, NL3D 1st 2D filter difference table regsiter for G
REG_NL3D_D2D1B0               reg_nl3d_d2d1b0               ; // 0x1348, NL3D 1st 2D filter difference table regsiter for B
REG_NL3D_D2D1B1               reg_nl3d_d2d1b1               ; // 0x134C, NL3D 1st 2D filter difference table regsiter for B
REG_NL3D_S2D1R0               reg_nl3d_s2d1r0               ; // 0x1350, NL3D 1st 2D filter spatial weight table regsiter
REG_NL3D_S2D1R1               reg_nl3d_s2d1r1               ; // 0x1354, NL3D 1st 2D filter spatial weight table regsiter
REG_NL3D_W2D2R                reg_nl3d_w2d2r                ; // 0x1358, NL3D 2nd 2D filter weight table regsiter
REG_NL3D_D2D2R0               reg_nl3d_d2d2r0               ; // 0x135C, NL3D 2nd 2D filter difference table regsiter
REG_NL3D_D2D2R1               reg_nl3d_d2d2r1               ; // 0x1360, NL3D 2nd 2D filter difference table regsiter
REG_NL3D_S2D2R0               reg_nl3d_s2d2r0               ; // 0x1364, NL3D 2nd 2D filter spatial weight table regsiter
REG_NL3D_S2D2R1               reg_nl3d_s2d2r1               ; // 0x1368, NL3D 2nd 2D filter spatial weight table regsiter
REG_NL3D_REFWCX0              reg_nl3d_refwcx0              ; // 0x136C, NL3D refw curve x register
REG_NL3D_REFWCX1              reg_nl3d_refwcx1              ; // 0x1370, NL3D  refw curve x register
REG_NL3D_REFWCY0              reg_nl3d_refwcy0              ; // 0x1374, NL3D  refw curve y register
REG_NL3D_REFWCY1              reg_nl3d_refwcy1              ; // 0x1378, NL3D  refw curve y register
REG_NL3D_MOVWCX0              reg_nl3d_movwcx0              ; // 0x137C, NL3D movw curve x register
REG_NL3D_MOVWCX1              reg_nl3d_movwcx1              ; // 0x1380, NL3D  movw curve x register
REG_NL3D_MOVWCY0              reg_nl3d_movwcy0              ; // 0x1384, NL3D  movw curve y register
REG_NL3D_MOVWCY1              reg_nl3d_movwcy1              ; // 0x1388, NL3D  movw curve y register
REG_NL3D_SNTCX0               reg_nl3d_sntcx0               ; // 0x138C, NL3D snt curve x register
REG_NL3D_SNTCX1               reg_nl3d_sntcx1               ; // 0x1390, NL3D  snt curve x register
REG_NL3D_SNTCY0               reg_nl3d_sntcy0               ; // 0x1394, NL3D  snt curve y register
REG_NL3D_SNTCY1               reg_nl3d_sntcy1               ; // 0x1398, NL3D  snt curve y register
REG_NL2DRSIGMAX0              reg_nl2drsigmax0              ; // 0x2000, NL2D R SIGMA X Register 0
REG_NL2DRSIGMAX1              reg_nl2drsigmax1              ; // 0x2004, NL2D R SIGMA X Register 1
REG_NL2DRSIGMAX2              reg_nl2drsigmax2              ; // 0x2008, NL2D R SIGMA X Register 2
REG_NL2DRSIGMAX3              reg_nl2drsigmax3              ; // 0x200C, NL2D R SIGMA X Register 3
REG_NL2DRSIGMAX4              reg_nl2drsigmax4              ; // 0x2010, NL2D R SIGMA X Register 4
REG_NL2DRSIGMAX5              reg_nl2drsigmax5              ; // 0x2014, NL2D R SIGMA X Register 5
REG_NL2DRSIGMAX6              reg_nl2drsigmax6              ; // 0x2018, NL2D R SIGMA X Register 6
REG_NL2DRSIGMAX7              reg_nl2drsigmax7              ; // 0x201C, NL2D R SIGMA X Register 7
REG_NL2DGSIGMAX0              reg_nl2dgsigmax0              ; // 0x2020, NL2D G SIGMA X Register 0
REG_NL2DGSIGMAX1              reg_nl2dgsigmax1              ; // 0x2024, NL2D G SIGMA X Register 1
REG_NL2DGSIGMAX2              reg_nl2dgsigmax2              ; // 0x2028, NL2D G SIGMA X Register 2
REG_NL2DGSIGMAX3              reg_nl2dgsigmax3              ; // 0x202C, NL2D G SIGMA X Register 3
REG_NL2DGSIGMAX4              reg_nl2dgsigmax4              ; // 0x2030, NL2D G SIGMA X Register 4
REG_NL2DGSIGMAX5              reg_nl2dgsigmax5              ; // 0x2034, NL2D G SIGMA X Register 5
REG_NL2DGSIGMAX6              reg_nl2dgsigmax6              ; // 0x2038, NL2D G SIGMA X Register 6
REG_NL2DGSIGMAX7              reg_nl2dgsigmax7              ; // 0x203C, NL2D G SIGMA X Register 7
REG_NL2DBSIGMAX0              reg_nl2dbsigmax0              ; // 0x2040, NL2D B SIGMA X Register 0
REG_NL2DBSIGMAX1              reg_nl2dbsigmax1              ; // 0x2044, NL2D B SIGMA X Register 1
REG_NL2DBSIGMAX2              reg_nl2dbsigmax2              ; // 0x2048, NL2D B SIGMA X Register 2
REG_NL2DBSIGMAX3              reg_nl2dbsigmax3              ; // 0x204C, NL2D B SIGMA X Register 3
REG_NL2DBSIGMAX4              reg_nl2dbsigmax4              ; // 0x2050, NL2D B SIGMA X Register 4
REG_NL2DBSIGMAX5              reg_nl2dbsigmax5              ; // 0x2054, NL2D B SIGMA X Register 5
REG_NL2DBSIGMAX6              reg_nl2dbsigmax6              ; // 0x2058, NL2D B SIGMA X Register 6
REG_NL2DBSIGMAX7              reg_nl2dbsigmax7              ; // 0x205C, NL2D B SIGMA X Register 7
REG_NL2DRSIGMAY0              reg_nl2drsigmay0              ; // 0x2060, NL2D R SIGMA Y Register 0
REG_NL2DRSIGMAY1              reg_nl2drsigmay1              ; // 0x2064, NL2D R SIGMA Y Register 1
REG_NL2DRSIGMAY2              reg_nl2drsigmay2              ; // 0x2068, NL2D R SIGMA Y Register 2
REG_NL2DRSIGMAY3              reg_nl2drsigmay3              ; // 0x206C, NL2D R SIGMA Y Register 3
REG_NL2DRSIGMAY4              reg_nl2drsigmay4              ; // 0x2070, NL2D R SIGMA Y Register 4
REG_NL2DRSIGMAY5              reg_nl2drsigmay5              ; // 0x2074, NL2D R SIGMA Y Register 5
REG_NL2DRSIGMAY6              reg_nl2drsigmay6              ; // 0x2078, NL2D R SIGMA Y Register 6
REG_NL2DRSIGMAY7              reg_nl2drsigmay7              ; // 0x207C, NL2D R SIGMA Y Register 7
REG_NL2DRSIGMAY8              reg_nl2drsigmay8              ; // 0x2080, NL2D R SIGMA Y Register 8
REG_NL2DRSIGMAY9              reg_nl2drsigmay9              ; // 0x2084, NL2D R SIGMA Y Register 9
REG_NL2DRSIGMAY10             reg_nl2drsigmay10             ; // 0x2088, NL2D R SIGMA Y Register 10
REG_NL2DRSIGMAY11             reg_nl2drsigmay11             ; // 0x208C, NL2D R SIGMA Y Register 11
REG_NL2DRSIGMAY12             reg_nl2drsigmay12             ; // 0x2090, NL2D R SIGMA Y Register 12
REG_NL2DRSIGMAY13             reg_nl2drsigmay13             ; // 0x2094, NL2D R SIGMA Y Register 13
REG_NL2DRSIGMAY14             reg_nl2drsigmay14             ; // 0x2098, NL2D R SIGMA Y Register 14
REG_NL2DRSIGMAY15             reg_nl2drsigmay15             ; // 0x209C, NL2D R SIGMA Y Register 15
REG_NL2DGSIGMAY0              reg_nl2dgsigmay0              ; // 0x20A0, NL2D G SIGMA Y Register 0
REG_NL2DGSIGMAY1              reg_nl2dgsigmay1              ; // 0x20A4, NL2D G SIGMA Y Register 1
REG_NL2DGSIGMAY2              reg_nl2dgsigmay2              ; // 0x20A8, NL2D G SIGMA Y Register 2
REG_NL2DGSIGMAY3              reg_nl2dgsigmay3              ; // 0x20AC, NL2D G SIGMA Y Register 3
REG_NL2DGSIGMAY4              reg_nl2dgsigmay4              ; // 0x20B0, NL2D G SIGMA Y Register 4
REG_NL2DGSIGMAY5              reg_nl2dgsigmay5              ; // 0x20B4, NL2D G SIGMA Y Register 5
REG_NL2DGSIGMAY6              reg_nl2dgsigmay6              ; // 0x20B8, NL2D G SIGMA Y Register 6
REG_NL2DGSIGMAY7              reg_nl2dgsigmay7              ; // 0x20BC, NL2D G SIGMA Y Register 7
REG_NL2DGSIGMAY8              reg_nl2dgsigmay8              ; // 0x20C0, NL2D G SIGMA Y Register 8
REG_NL2DGSIGMAY9              reg_nl2dgsigmay9              ; // 0x20C4, NL2D G SIGMA Y Register 9
REG_NL2DGSIGMAY10             reg_nl2dgsigmay10             ; // 0x20C8, NL2D G SIGMA Y Register 10
REG_NL2DGSIGMAY11             reg_nl2dgsigmay11             ; // 0x20CC, NL2D G SIGMA Y Register 11
REG_NL2DGSIGMAY12             reg_nl2dgsigmay12             ; // 0x20D0, NL2D G SIGMA Y Register 12
REG_NL2DGSIGMAY13             reg_nl2dgsigmay13             ; // 0x20D4, NL2D G SIGMA Y Register 13
REG_NL2DGSIGMAY14             reg_nl2dgsigmay14             ; // 0x20D8, NL2D G SIGMA Y Register 14
REG_NL2DGSIGMAY15             reg_nl2dgsigmay15             ; // 0x20DC, NL2D G SIGMA Y Register 15
REG_NL2DBSIGMAY0              reg_nl2dbsigmay0              ; // 0x20E0, NL2D B SIGMA Y Register 0
REG_NL2DBSIGMAY1              reg_nl2dbsigmay1              ; // 0x20E4, NL2D B SIGMA Y Register 1
REG_NL2DBSIGMAY2              reg_nl2dbsigmay2              ; // 0x20E8, NL2D B SIGMA Y Register 2
REG_NL2DBSIGMAY3              reg_nl2dbsigmay3              ; // 0x20EC, NL2D B SIGMA Y Register 3
REG_NL2DBSIGMAY4              reg_nl2dbsigmay4              ; // 0x20F0, NL2D B SIGMA Y Register 4
REG_NL2DBSIGMAY5              reg_nl2dbsigmay5              ; // 0x20F4, NL2D B SIGMA Y Register 5
REG_NL2DBSIGMAY6              reg_nl2dbsigmay6              ; // 0x20F8, NL2D B SIGMA Y Register 6
REG_NL2DBSIGMAY7              reg_nl2dbsigmay7              ; // 0x20FC, NL2D B SIGMA Y Register 7
REG_NL2DBSIGMAY8              reg_nl2dbsigmay8              ; // 0x2100, NL2D B SIGMA Y Register 8
REG_NL2DBSIGMAY9              reg_nl2dbsigmay9              ; // 0x2104, NL2D B SIGMA Y Register 9
REG_NL2DBSIGMAY10             reg_nl2dbsigmay10             ; // 0x2108, NL2D B SIGMA Y Register 10
REG_NL2DBSIGMAY11             reg_nl2dbsigmay11             ; // 0x210C, NL2D B SIGMA Y Register 11
REG_NL2DBSIGMAY12             reg_nl2dbsigmay12             ; // 0x2110, NL2D B SIGMA Y Register 12
REG_NL2DBSIGMAY13             reg_nl2dbsigmay13             ; // 0x2114, NL2D B SIGMA Y Register 13
REG_NL2DBSIGMAY14             reg_nl2dbsigmay14             ; // 0x2118, NL2D B SIGMA Y Register 14
REG_NL2DBSIGMAY15             reg_nl2dbsigmay15             ; // 0x211C, NL2D B SIGMA Y Register 15
REG_NL2DRSIGMAS0              reg_nl2drsigmas0              ; // 0x2120, NL2D R SIGMA S Register 0
REG_NL2DRSIGMAS1              reg_nl2drsigmas1              ; // 0x2124, NL2D R SIGMA S Register 1
REG_NL2DRSIGMAS2              reg_nl2drsigmas2              ; // 0x2128, NL2D R SIGMA S Register 2
REG_NL2DRSIGMAS3              reg_nl2drsigmas3              ; // 0x212C, NL2D R SIGMA S Register 3
REG_NL2DRSIGMAS4              reg_nl2drsigmas4              ; // 0x2130, NL2D R SIGMA S Register 4
REG_NL2DRSIGMAS5              reg_nl2drsigmas5              ; // 0x2134, NL2D R SIGMA S Register 5
REG_NL2DRSIGMAS6              reg_nl2drsigmas6              ; // 0x2138, NL2D R SIGMA S Register 6
REG_NL2DRSIGMAS7              reg_nl2drsigmas7              ; // 0x213C, NL2D R SIGMA S Register 7
REG_NL2DGSIGMAS0              reg_nl2dgsigmas0              ; // 0x2140, NL2D G SIGMA S Register 0
REG_NL2DGSIGMAS1              reg_nl2dgsigmas1              ; // 0x2144, NL2D G SIGMA S Register 1
REG_NL2DGSIGMAS2              reg_nl2dgsigmas2              ; // 0x2148, NL2D G SIGMA S Register 2
REG_NL2DGSIGMAS3              reg_nl2dgsigmas3              ; // 0x214C, NL2D G SIGMA S Register 3
REG_NL2DGSIGMAS4              reg_nl2dgsigmas4              ; // 0x2150, NL2D G SIGMA S Register 4
REG_NL2DGSIGMAS5              reg_nl2dgsigmas5              ; // 0x2154, NL2D G SIGMA S Register 5
REG_NL2DGSIGMAS6              reg_nl2dgsigmas6              ; // 0x2158, NL2D G SIGMA S Register 6
REG_NL2DGSIGMAS7              reg_nl2dgsigmas7              ; // 0x215C, NL2D G SIGMA S Register 7
REG_NL2DBSIGMAS0              reg_nl2dbsigmas0              ; // 0x2160, NL2D B SIGMA S Register 0
REG_NL2DBSIGMAS1              reg_nl2dbsigmas1              ; // 0x2164, NL2D B SIGMA S Register 1
REG_NL2DBSIGMAS2              reg_nl2dbsigmas2              ; // 0x2168, NL2D B SIGMA S Register 2
REG_NL2DBSIGMAS3              reg_nl2dbsigmas3              ; // 0x216C, NL2D B SIGMA S Register 3
REG_NL2DBSIGMAS4              reg_nl2dbsigmas4              ; // 0x2170, NL2D B SIGMA S Register 4
REG_NL2DBSIGMAS5              reg_nl2dbsigmas5              ; // 0x2174, NL2D B SIGMA S Register 5
REG_NL2DBSIGMAS6              reg_nl2dbsigmas6              ; // 0x2178, NL2D B SIGMA S Register 6
REG_NL2DBSIGMAS7              reg_nl2dbsigmas7              ; // 0x217C, NL2D B SIGMA S Register 7
REG_NL2DRFILTPARX0            reg_nl2drfiltparx0            ; // 0x2180, NL2D R FILTPAR X Register 0
REG_NL2DRFILTPARX1            reg_nl2drfiltparx1            ; // 0x2184, NL2D R FILTPAR X Register 1
REG_NL2DRFILTPARX2            reg_nl2drfiltparx2            ; // 0x2188, NL2D R FILTPAR X Register 2
REG_NL2DRFILTPARX3            reg_nl2drfiltparx3            ; // 0x218C, NL2D R FILTPAR X Register 3
REG_NL2DRFILTPARX4            reg_nl2drfiltparx4            ; // 0x2190, NL2D R FILTPAR X Register 4
REG_NL2DRFILTPARX5            reg_nl2drfiltparx5            ; // 0x2194, NL2D R FILTPAR X Register 5
REG_NL2DRFILTPARX6            reg_nl2drfiltparx6            ; // 0x2198, NL2D R FILTPAR X Register 6
REG_NL2DRFILTPARX7            reg_nl2drfiltparx7            ; // 0x219C, NL2D R FILTPAR X Register 7
REG_NL2DGFILTPARX0            reg_nl2dgfiltparx0            ; // 0x21A0, NL2D G FILTPAR X Register 0
REG_NL2DGFILTPARX1            reg_nl2dgfiltparx1            ; // 0x21A4, NL2D G FILTPAR X Register 1
REG_NL2DGFILTPARX2            reg_nl2dgfiltparx2            ; // 0x21A8, NL2D G FILTPAR X Register 2
REG_NL2DGFILTPARX3            reg_nl2dgfiltparx3            ; // 0x21AC, NL2D G FILTPAR X Register 3
REG_NL2DGFILTPARX4            reg_nl2dgfiltparx4            ; // 0x21B0, NL2D G FILTPAR X Register 4
REG_NL2DGFILTPARX5            reg_nl2dgfiltparx5            ; // 0x21B4, NL2D G FILTPAR X Register 5
REG_NL2DGFILTPARX6            reg_nl2dgfiltparx6            ; // 0x21B8, NL2D G FILTPAR X Register 6
REG_NL2DGFILTPARX7            reg_nl2dgfiltparx7            ; // 0x21BC, NL2D G FILTPAR X Register 7
REG_NL2DBFILTPARX0            reg_nl2dbfiltparx0            ; // 0x21C0, NL2D B FILTPAR X Register 0
REG_NL2DBFILTPARX1            reg_nl2dbfiltparx1            ; // 0x21C4, NL2D B FILTPAR X Register 1
REG_NL2DBFILTPARX2            reg_nl2dbfiltparx2            ; // 0x21C8, NL2D B FILTPAR X Register 2
REG_NL2DBFILTPARX3            reg_nl2dbfiltparx3            ; // 0x21CC, NL2D B FILTPAR X Register 3
REG_NL2DBFILTPARX4            reg_nl2dbfiltparx4            ; // 0x21D0, NL2D B FILTPAR X Register 4
REG_NL2DBFILTPARX5            reg_nl2dbfiltparx5            ; // 0x21D4, NL2D B FILTPAR X Register 5
REG_NL2DBFILTPARX6            reg_nl2dbfiltparx6            ; // 0x21D8, NL2D B FILTPAR X Register 6
REG_NL2DBFILTPARX7            reg_nl2dbfiltparx7            ; // 0x21DC, NL2D B FILTPAR X Register 7
REG_NL2DRFILTPARY0            reg_nl2drfiltpary0            ; // 0x21E0, NL2D R FILTPAR Y Register 0
REG_NL2DRFILTPARY1            reg_nl2drfiltpary1            ; // 0x21E4, NL2D R FILTPAR Y Register 1
REG_NL2DRFILTPARY2            reg_nl2drfiltpary2            ; // 0x21E8, NL2D R FILTPAR Y Register 2
REG_NL2DRFILTPARY3            reg_nl2drfiltpary3            ; // 0x21EC, NL2D R FILTPAR Y Register 3
REG_NL2DRFILTPARY4            reg_nl2drfiltpary4            ; // 0x21F0, NL2D R FILTPAR Y Register 4
REG_NL2DRFILTPARY5            reg_nl2drfiltpary5            ; // 0x21F4, NL2D R FILTPAR Y Register 5
REG_NL2DRFILTPARY6            reg_nl2drfiltpary6            ; // 0x21F8, NL2D R FILTPAR Y Register 6
REG_NL2DRFILTPARY7            reg_nl2drfiltpary7            ; // 0x21FC, NL2D R FILTPAR Y Register 7
REG_NL2DRFILTPARY8            reg_nl2drfiltpary8            ; // 0x2200, NL2D R FILTPAR Y Register 8
REG_NL2DRFILTPARY9            reg_nl2drfiltpary9            ; // 0x2204, NL2D R FILTPAR Y Register 9
REG_NL2DRFILTPARY10           reg_nl2drfiltpary10           ; // 0x2208, NL2D R FILTPAR Y Register 10
REG_NL2DRFILTPARY11           reg_nl2drfiltpary11           ; // 0x220C, NL2D R FILTPAR Y Register 11
REG_NL2DRFILTPARY12           reg_nl2drfiltpary12           ; // 0x2210, NL2D R FILTPAR Y Register 12
REG_NL2DRFILTPARY13           reg_nl2drfiltpary13           ; // 0x2214, NL2D R FILTPAR Y Register 13
REG_NL2DRFILTPARY14           reg_nl2drfiltpary14           ; // 0x2218, NL2D R FILTPAR Y Register 14
REG_NL2DRFILTPARY15           reg_nl2drfiltpary15           ; // 0x221C, NL2D R FILTPAR Y Register 15
REG_NL2DGFILTPARY0            reg_nl2dgfiltpary0            ; // 0x2220, NL2D G FILTPAR Y Register 0
REG_NL2DGFILTPARY1            reg_nl2dgfiltpary1            ; // 0x2224, NL2D G FILTPAR Y Register 1
REG_NL2DGFILTPARY2            reg_nl2dgfiltpary2            ; // 0x2228, NL2D G FILTPAR Y Register 2
REG_NL2DGFILTPARY3            reg_nl2dgfiltpary3            ; // 0x222C, NL2D G FILTPAR Y Register 3
REG_NL2DGFILTPARY4            reg_nl2dgfiltpary4            ; // 0x2230, NL2D G FILTPAR Y Register 4
REG_NL2DGFILTPARY5            reg_nl2dgfiltpary5            ; // 0x2234, NL2D G FILTPAR Y Register 5
REG_NL2DGFILTPARY6            reg_nl2dgfiltpary6            ; // 0x2238, NL2D G FILTPAR Y Register 6
REG_NL2DGFILTPARY7            reg_nl2dgfiltpary7            ; // 0x223C, NL2D G FILTPAR Y Register 7
REG_NL2DGFILTPARY8            reg_nl2dgfiltpary8            ; // 0x2240, NL2D G FILTPAR Y Register 8
REG_NL2DGFILTPARY9            reg_nl2dgfiltpary9            ; // 0x2244, NL2D G FILTPAR Y Register 9
REG_NL2DGFILTPARY10           reg_nl2dgfiltpary10           ; // 0x2248, NL2D G FILTPAR Y Register 10
REG_NL2DGFILTPARY11           reg_nl2dgfiltpary11           ; // 0x224C, NL2D G FILTPAR Y Register 11
REG_NL2DGFILTPARY12           reg_nl2dgfiltpary12           ; // 0x2250, NL2D G FILTPAR Y Register 12
REG_NL2DGFILTPARY13           reg_nl2dgfiltpary13           ; // 0x2254, NL2D G FILTPAR Y Register 13
REG_NL2DGFILTPARY14           reg_nl2dgfiltpary14           ; // 0x2258, NL2D G FILTPAR Y Register 14
REG_NL2DGFILTPARY15           reg_nl2dgfiltpary15           ; // 0x225C, NL2D G FILTPAR Y Register 15
REG_NL2DBFILTPARY0            reg_nl2dbfiltpary0            ; // 0x2260, NL2D B FILTPAR Y Register 0
REG_NL2DBFILTPARY1            reg_nl2dbfiltpary1            ; // 0x2264, NL2D B FILTPAR Y Register 1
REG_NL2DBFILTPARY2            reg_nl2dbfiltpary2            ; // 0x2268, NL2D B FILTPAR Y Register 2
REG_NL2DBFILTPARY3            reg_nl2dbfiltpary3            ; // 0x226C, NL2D B FILTPAR Y Register 3
REG_NL2DBFILTPARY4            reg_nl2dbfiltpary4            ; // 0x2270, NL2D B FILTPAR Y Register 4
REG_NL2DBFILTPARY5            reg_nl2dbfiltpary5            ; // 0x2274, NL2D B FILTPAR Y Register 5
REG_NL2DBFILTPARY6            reg_nl2dbfiltpary6            ; // 0x2278, NL2D B FILTPAR Y Register 6
REG_NL2DBFILTPARY7            reg_nl2dbfiltpary7            ; // 0x227C, NL2D B FILTPAR Y Register 7
REG_NL2DBFILTPARY8            reg_nl2dbfiltpary8            ; // 0x2280, NL2D B FILTPAR Y Register 8
REG_NL2DBFILTPARY9            reg_nl2dbfiltpary9            ; // 0x2284, NL2D B FILTPAR Y Register 9
REG_NL2DBFILTPARY10           reg_nl2dbfiltpary10           ; // 0x2288, NL2D B FILTPAR Y Register 10
REG_NL2DBFILTPARY11           reg_nl2dbfiltpary11           ; // 0x228C, NL2D B FILTPAR Y Register 11
REG_NL2DBFILTPARY12           reg_nl2dbfiltpary12           ; // 0x2290, NL2D B FILTPAR Y Register 12
REG_NL2DBFILTPARY13           reg_nl2dbfiltpary13           ; // 0x2294, NL2D B FILTPAR Y Register 13
REG_NL2DBFILTPARY14           reg_nl2dbfiltpary14           ; // 0x2298, NL2D B FILTPAR Y Register 14
REG_NL2DBFILTPARY15           reg_nl2dbfiltpary15           ; // 0x229C, NL2D B FILTPAR Y Register 15
REG_NL2DRFILTPARS0            reg_nl2drfiltpars0            ; // 0x22A0, NL2D R FILTPAR S Register 0
REG_NL2DRFILTPARS1            reg_nl2drfiltpars1            ; // 0x22A4, NL2D R FILTPAR S Register 1
REG_NL2DRFILTPARS2            reg_nl2drfiltpars2            ; // 0x22A8, NL2D R FILTPAR S Register 2
REG_NL2DRFILTPARS3            reg_nl2drfiltpars3            ; // 0x22AC, NL2D R FILTPAR S Register 3
REG_NL2DRFILTPARS4            reg_nl2drfiltpars4            ; // 0x22B0, NL2D R FILTPAR S Register 4
REG_NL2DRFILTPARS5            reg_nl2drfiltpars5            ; // 0x22B4, NL2D R FILTPAR S Register 5
REG_NL2DRFILTPARS6            reg_nl2drfiltpars6            ; // 0x22B8, NL2D R FILTPAR S Register 6
REG_NL2DRFILTPARS7            reg_nl2drfiltpars7            ; // 0x22BC, NL2D R FILTPAR S Register 7
REG_NL2DGFILTPARS0            reg_nl2dgfiltpars0            ; // 0x22C0, NL2D G FILTPAR S Register 0
REG_NL2DGFILTPARS1            reg_nl2dgfiltpars1            ; // 0x22C4, NL2D G FILTPAR S Register 1
REG_NL2DGFILTPARS2            reg_nl2dgfiltpars2            ; // 0x22C8, NL2D G FILTPAR S Register 2
REG_NL2DGFILTPARS3            reg_nl2dgfiltpars3            ; // 0x22CC, NL2D G FILTPAR S Register 3
REG_NL2DGFILTPARS4            reg_nl2dgfiltpars4            ; // 0x22D0, NL2D G FILTPAR S Register 4
REG_NL2DGFILTPARS5            reg_nl2dgfiltpars5            ; // 0x22D4, NL2D G FILTPAR S Register 5
REG_NL2DGFILTPARS6            reg_nl2dgfiltpars6            ; // 0x22D8, NL2D G FILTPAR S Register 6
REG_NL2DGFILTPARS7            reg_nl2dgfiltpars7            ; // 0x22DC, NL2D G FILTPAR S Register 7
REG_NL2DBFILTPARS0            reg_nl2dbfiltpars0            ; // 0x22E0, NL2D B FILTPAR S Register 0
REG_NL2DBFILTPARS1            reg_nl2dbfiltpars1            ; // 0x22E4, NL2D B FILTPAR S Register 1
REG_NL2DBFILTPARS2            reg_nl2dbfiltpars2            ; // 0x22E8, NL2D B FILTPAR S Register 2
REG_NL2DBFILTPARS3            reg_nl2dbfiltpars3            ; // 0x22EC, NL2D B FILTPAR S Register 3
REG_NL2DBFILTPARS4            reg_nl2dbfiltpars4            ; // 0x22F0, NL2D B FILTPAR S Register 4
REG_NL2DBFILTPARS5            reg_nl2dbfiltpars5            ; // 0x22F4, NL2D B FILTPAR S Register 5
REG_NL2DBFILTPARS6            reg_nl2dbfiltpars6            ; // 0x22F8, NL2D B FILTPAR S Register 6
REG_NL2DBFILTPARS7            reg_nl2dbfiltpars7            ; // 0x22FC, NL2D B FILTPAR S Register 7
REG_NL2DCFG                   reg_nl2dcfg                   ; // 0x2300, NL2D CFG Register
REG_NWEDYS1THX0               reg_nwedys1thx0               ; // 0x2400, NWED Y Channel S1 Threshold X Register 0
REG_NWEDYS1THX1               reg_nwedys1thx1               ; // 0x2404, NWED Y Channel S1Threshold X Register 1
REG_NWEDYS1THX2               reg_nwedys1thx2               ; // 0x2408, NWED Y Channel S1 Threshold X Register 2
REG_NWEDYS1THX3               reg_nwedys1thx3               ; // 0x240C, NWED Y Channel S1 Threshold X Register 3
REG_NWEDYS1THX4               reg_nwedys1thx4               ; // 0x2410, NWED Y Channel S1 Threshold X Register 4
REG_NWEDYS1THX5               reg_nwedys1thx5               ; // 0x2414, NWED Y Channel S1 Threshold X Register 5
REG_NWEDYS1THX6               reg_nwedys1thx6               ; // 0x2418, NWED Y Channel S1 Threshold X Register 6
REG_NWEDYS1THX7               reg_nwedys1thx7               ; // 0x241C, NWED Y Channel S1 Threshold X Register 7
REG_NWEDYS6THX0               reg_nwedys6thx0               ; // 0x2420, NWED Y Channel S6 Threshold X Register 0
REG_NWEDYS6THX1               reg_nwedys6thx1               ; // 0x2424, NWED Y Channel S6 Threshold X Register 1
REG_NWEDYS6THX2               reg_nwedys6thx2               ; // 0x2428, NWED Y Channel S6 Threshold X Register 2
REG_NWEDYS6THX3               reg_nwedys6thx3               ; // 0x242C, NWED Y Channel S6 Threshold X Register 3
REG_NWEDYS6THX4               reg_nwedys6thx4               ; // 0x2430, NWED Y Channel S6 Threshold X Register 4
REG_NWEDYS6THX5               reg_nwedys6thx5               ; // 0x2434, NWED Y Channel S6 Threshold X Register 5
REG_NWEDYS6THX6               reg_nwedys6thx6               ; // 0x2438, NWED Y Channel S6 Threshold X Register 6
REG_NWEDYS6THX7               reg_nwedys6thx7               ; // 0x243C, NWED Y Channel S6 Threshold X Register 7
REG_NWEDUVS1THX0              reg_nweduvs1thx0              ; // 0x2440, NWED UV Channel S1 Threshold X Register 0
REG_NWEDUVS1THX1              reg_nweduvs1thx1              ; // 0x2444, NWED UV Channel S1 Threshold X Register 1
REG_NWEDUVS1THX2              reg_nweduvs1thx2              ; // 0x2448, NWED UV  S1 Threshold X Register 2
REG_NWEDUVS1THX3              reg_nweduvs1thx3              ; // 0x244C, NWED UV  S1 Threshold X Register 3
REG_NWEDUVS1THX4              reg_nweduvs1thx4              ; // 0x2450, NWED UV Channel S1 Threshold X Register 4
REG_NWEDUVS1THX5              reg_nweduvs1thx5              ; // 0x2454, NWED UV  S1 Threshold X Register 5
REG_NWEDUVS1THX6              reg_nweduvs1thx6              ; // 0x2458, NWED UV  S1 Threshold X Register 6
REG_NWEDUVS1THX7              reg_nweduvs1thx7              ; // 0x245C, NWED UV Channel S1 Threshold X Register 7
REG_NWEDUVS6THX0              reg_nweduvs6thx0              ; // 0x2460, NWED UV  S6 Threshold X Register 0
REG_NWEDUVS6THX1              reg_nweduvs6thx1              ; // 0x2464, NWED UV  S6 Threshold X Register 1
REG_NWEDUVS6THX2              reg_nweduvs6thx2              ; // 0x2468, NWED UV Channel S6 Threshold X Register 2
REG_NWEDUVS6THX3              reg_nweduvs6thx3              ; // 0x246C, NWED UV Channel S6 Threshold X Register 3
REG_NWEDUVS6THX4              reg_nweduvs6thx4              ; // 0x2470, NWED UV Channel S6 Threshold X Register 4
REG_NWEDUVS6THX5              reg_nweduvs6thx5              ; // 0x2474, NWED UV Channel S6 Threshold X Register 5
REG_NWEDUVS6THX6              reg_nweduvs6thx6              ; // 0x2478, NWED UV Channel S6 Threshold X Register 6
REG_NWEDUVS6THX7              reg_nweduvs6thx7              ; // 0x247C, NWED UV Channel S6 Threshold X Register 7
REG_NWEDYS1THY0               reg_nwedys1thy0               ; // 0x2480, NWED Y Channel S1 Threshold Y Register 0
REG_NWEDYS1THY1               reg_nwedys1thy1               ; // 0x2484, NWED Y Channel S1 Threshold Y Register 1
REG_NWEDYS1THY2               reg_nwedys1thy2               ; // 0x2488, NWED Y Channel S1 Threshold Y Register 2
REG_NWEDYS1THY3               reg_nwedys1thy3               ; // 0x248C, NWED Y Channel S1 Threshold Y Register 3
REG_NWEDYS1THY4               reg_nwedys1thy4               ; // 0x2490, NWED Y Channel S1 Threshold Y Register 4
REG_NWEDYS1THY5               reg_nwedys1thy5               ; // 0x2494, NWED Y Channel S1 Threshold Y Register 5
REG_NWEDYS1THY6               reg_nwedys1thy6               ; // 0x2498, NWED Y Channel S1 Threshold Y Register 6
REG_NWEDYS1THY7               reg_nwedys1thy7               ; // 0x249C, NWED Y Channel S1 Threshold Y Register 7
REG_NWEDYS6THY0               reg_nwedys6thy0               ; // 0x24A0, NWED Y Channel S6 Threshold Y Register 0
REG_NWEDYS6THY1               reg_nwedys6thy1               ; // 0x24A4, NWED Y Channel S6 Threshold Y Register 1
REG_NWEDYS6THY2               reg_nwedys6thy2               ; // 0x24A8, NWED Y Channel S6 Threshold Y Register 2
REG_NWEDYS6THY3               reg_nwedys6thy3               ; // 0x24AC, NWED Y Channel S6 Threshold Y Register 3
REG_NWEDYS6THY4               reg_nwedys6thy4               ; // 0x24B0, NWED Y Channel S6 Threshold Y Register 4
REG_NWEDYS6THY5               reg_nwedys6thy5               ; // 0x24B4, NWED Y Channel S6 Threshold Y Register 5
REG_NWEDYS6THY6               reg_nwedys6thy6               ; // 0x24B8, NWED Y Channel S6 Threshold Y Register 6
REG_NWEDYS6THY7               reg_nwedys6thy7               ; // 0x24BC, NWED Y Channel S6 Threshold Y Register 7
REG_NWEDUVS1THY0              reg_nweduvs1thy0              ; // 0x24C0, NWED UV ChannelS1 Threshold Y Register 0
REG_NWEDUVS1THY1              reg_nweduvs1thy1              ; // 0x24C4, NWED UV Channel S1 Threshold Y Register 1
REG_NWEDUVS1THY2              reg_nweduvs1thy2              ; // 0x24C8, NWED UV Channel S1 Threshold Y Register 2
REG_NWEDUVS1THY3              reg_nweduvs1thy3              ; // 0x24CC, NWED UV Channel S1 Threshold Y Register 3
REG_NWEDUVS1THY4              reg_nweduvs1thy4              ; // 0x24D0, NWED UV Channel S1 Threshold Y Register 4
REG_NWEDUVS1THY5              reg_nweduvs1thy5              ; // 0x24D4, NWED UV Channel S1 Threshold Y Register 5
REG_NWEDUVS1THY6              reg_nweduvs1thy6              ; // 0x24D8, NWED UV Channel S1 Threshold Y Register 6
REG_NWEDUVS1THY7              reg_nweduvs1thy7              ; // 0x24DC, NWED UV Channel S1 Threshold Y Register 7
REG_NWEDUVS6THY0              reg_nweduvs6thy0              ; // 0x24E0, NWED UV ChannelS6 Threshold Y Register 0
REG_NWEDUVS6THY1              reg_nweduvs6thy1              ; // 0x24E4, NWED UV Channel S6 Threshold Y Register 1
REG_NWEDUVS6THY2              reg_nweduvs6thy2              ; // 0x24E8, NWED UV Channel S6 Threshold Y Register 2
REG_NWEDUVS6THY3              reg_nweduvs6thy3              ; // 0x24EC, NWED UV Channel S6 Threshold Y Register 3
REG_NWEDUVS6THY4              reg_nweduvs6thy4              ; // 0x24F0, NWED UV Channel S6 Threshold Y Register 4
REG_NWEDUVS6THY5              reg_nweduvs6thy5              ; // 0x24F4, NWED UV Channel S6 Threshold Y Register 5
REG_NWEDUVS6THY6              reg_nweduvs6thy6              ; // 0x24F8, NWED UV Channel S6 Threshold Y Register 6
REG_NWEDUVS6THY7              reg_nweduvs6thy7              ; // 0x24FC, NWED UV Channel S6 Threshold Y Register 7
REG_NWEDYS1THS0               reg_nwedys1ths0               ; // 0x2500, NWED Y Channel S1 Threshold S Register 0
REG_NWEDYS1THS1               reg_nwedys1ths1               ; // 0x2504, NWED Y Channel S1 Threshold S Register 1
REG_NWEDYS1THS2               reg_nwedys1ths2               ; // 0x2508, NWED Y Channel S1 Threshold S Register 2
REG_NWEDYS1THS3               reg_nwedys1ths3               ; // 0x250C, NWED Y Channel S1 Threshold S Register 3
REG_NWEDYS1THS4               reg_nwedys1ths4               ; // 0x2510, NWED Y Channel S1 Threshold S Register 4
REG_NWEDYS1THS5               reg_nwedys1ths5               ; // 0x2514, NWED Y Channel S1 Threshold S Register 5
REG_NWEDYS1THS6               reg_nwedys1ths6               ; // 0x2518, NWED Y Channel S1 Threshold S Register 6
REG_NWEDYS1THS7               reg_nwedys1ths7               ; // 0x251C, NWED Y Channel S1 Threshold S Register 7
REG_NWEDYS6THS0               reg_nwedys6ths0               ; // 0x2520, NWED Y Channel S6 Threshold S Register 0
REG_NWEDYS6THS1               reg_nwedys6ths1               ; // 0x2524, NWED Y Channel S6 Threshold S Register 1
REG_NWEDYS6THS2               reg_nwedys6ths2               ; // 0x2528, NWED Y Channel S6 Threshold S Register 2
REG_NWEDYS6THS3               reg_nwedys6ths3               ; // 0x252C, NWED Y Channel S6 Threshold S Register 3
REG_NWEDYS6THS4               reg_nwedys6ths4               ; // 0x2530, NWED Y Channel S6 Threshold S Register 4
REG_NWEDYS6THS5               reg_nwedys6ths5               ; // 0x2534, NWED Y Channel S6 Threshold S Register 5
REG_NWEDYS6THS6               reg_nwedys6ths6               ; // 0x2538, NWED Y Channel S6 Threshold S Register 6
REG_NWEDYS6THS7               reg_nwedys6ths7               ; // 0x253C, NWED Y Channel S6 Threshold S Register 7
REG_NWEDUVS1THS0              reg_nweduvs1ths0              ; // 0x2540, NWED UV Channel S1 Threshold S Register 0
REG_NWEDUVS1THS1              reg_nweduvs1ths1              ; // 0x2544, NWED UV Channel S1 Threshold S Register 1
REG_NWEDUVS1THS2              reg_nweduvs1ths2              ; // 0x2548, NWED UV Channel S1 Threshold S Register 2
REG_NWEDUVS1THS3              reg_nweduvs1ths3              ; // 0x254C, NWED UV Channel S1 Threshold S Register 3
REG_NWEDUVS1THS4              reg_nweduvs1ths4              ; // 0x2550, NWED UV Channel S1 Threshold S Register 4
REG_NWEDUVS1THS5              reg_nweduvs1ths5              ; // 0x2554, NWED UV Channel S1 Threshold S Register 5
REG_NWEDUVS1THS6              reg_nweduvs1ths6              ; // 0x2558, NWED UV Channel S1 Threshold S Register 6
REG_NWEDUVS1THS7              reg_nweduvs1ths7              ; // 0x255C, NWED UV Channel S1 Threshold S Register 7
REG_NWEDUVS6THS0              reg_nweduvs6ths0              ; // 0x2560, NWED UV Channel S6 Threshold S Register 0
REG_NWEDUVS6THS1              reg_nweduvs6ths1              ; // 0x2564, NWED UV Channel S6 Threshold S Register 1
REG_NWEDUVS6THS2              reg_nweduvs6ths2              ; // 0x2568, NWED UV Channel S6 Threshold S Register 2
REG_NWEDUVS6THS3              reg_nweduvs6ths3              ; // 0x256C, NWED UV Channel S6 Threshold S Register 3
REG_NWEDUVS6THS4              reg_nweduvs6ths4              ; // 0x2570, NWED UV Channel S6 Threshold S Register 4
REG_NWEDUVS6THS5              reg_nweduvs6ths5              ; // 0x2574, NWED UV Channel S6 Threshold S Register 5
REG_NWEDUVS6THS6              reg_nweduvs6ths6              ; // 0x2578, NWED UV Channel S6 Threshold S Register 6
REG_NWEDUVS6THS7              reg_nweduvs6ths7              ; // 0x257C, NWED UV Channel S6 Threshold S Register 7
REG_NWEDDS0                   reg_nwedds0                   ; // 0x2580, NWED DS Register 0
REG_NWEDDS1                   reg_nwedds1                   ; // 0x2584, NWED DS Register 1
REG_OBCO_CFG_4                reg_obco_cfg_4                ; // 0x3030, each symbol has four point, each point has one 6~10bit(PW-4) offset register
REG_OBCO_CFG_5                reg_obco_cfg_5                ; // 0x3034, each symbol has four point, each point has one 6~10bit(PW-4) offset register
REG_OBCO_CFG_6                reg_obco_cfg_6                ; // 0x3038, each symbol has four point, each point has one 6~10bit(PW-4) offset register
REG_OBCO_CFG_7                reg_obco_cfg_7                ; // 0x303C, each symbol has four point, each point has one 6~10bit(PW-4) offset register
REG_OECFC_X0_CFG_0            reg_oecfc_x0_cfg_0            ; // 0x3200, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X0_CFG_1            reg_oecfc_x0_cfg_1            ; // 0x3204, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X0_CFG_2            reg_oecfc_x0_cfg_2            ; // 0x3208, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X0_CFG_3            reg_oecfc_x0_cfg_3            ; // 0x320C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X0_CFG_4            reg_oecfc_x0_cfg_4            ; // 0x3210, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X0_CFG_5            reg_oecfc_x0_cfg_5            ; // 0x3214, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X0_CFG_6            reg_oecfc_x0_cfg_6            ; // 0x3218, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X0_CFG_7            reg_oecfc_x0_cfg_7            ; // 0x321C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 0 
REG_OECFC_X1_CFG_0            reg_oecfc_x1_cfg_0            ; // 0x3220, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X1_CFG_1            reg_oecfc_x1_cfg_1            ; // 0x3224, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X1_CFG_2            reg_oecfc_x1_cfg_2            ; // 0x3228, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X1_CFG_3            reg_oecfc_x1_cfg_3            ; // 0x322C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X1_CFG_4            reg_oecfc_x1_cfg_4            ; // 0x3230, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X1_CFG_5            reg_oecfc_x1_cfg_5            ; // 0x3234, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X1_CFG_6            reg_oecfc_x1_cfg_6            ; // 0x3238, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X1_CFG_7            reg_oecfc_x1_cfg_7            ; // 0x323C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 1 
REG_OECFC_X2_CFG_0            reg_oecfc_x2_cfg_0            ; // 0x3240, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X2_CFG_1            reg_oecfc_x2_cfg_1            ; // 0x3244, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X2_CFG_2            reg_oecfc_x2_cfg_2            ; // 0x3248, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X2_CFG_3            reg_oecfc_x2_cfg_3            ; // 0x324C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X2_CFG_4            reg_oecfc_x2_cfg_4            ; // 0x3250, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X2_CFG_5            reg_oecfc_x2_cfg_5            ; // 0x3254, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X2_CFG_6            reg_oecfc_x2_cfg_6            ; // 0x3258, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X2_CFG_7            reg_oecfc_x2_cfg_7            ; // 0x325C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 2 
REG_OECFC_X3_CFG_0            reg_oecfc_x3_cfg_0            ; // 0x3260, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_X3_CFG_1            reg_oecfc_x3_cfg_1            ; // 0x3264, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_X3_CFG_2            reg_oecfc_x3_cfg_2            ; // 0x3268, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_X3_CFG_3            reg_oecfc_x3_cfg_3            ; // 0x326C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_X3_CFG_4            reg_oecfc_x3_cfg_4            ; // 0x3270, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_X3_CFG_5            reg_oecfc_x3_cfg_5            ; // 0x3274, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_X3_CFG_6            reg_oecfc_x3_cfg_6            ; // 0x3278, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_X3_CFG_7            reg_oecfc_x3_cfg_7            ; // 0x327C, OECFC(raw compand) X parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y0_CFG_0            reg_oecfc_y0_cfg_0            ; // 0x3280, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y0_CFG_1            reg_oecfc_y0_cfg_1            ; // 0x3284, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y0_CFG_2            reg_oecfc_y0_cfg_2            ; // 0x3288, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y0_CFG_3            reg_oecfc_y0_cfg_3            ; // 0x328C, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y0_CFG_4            reg_oecfc_y0_cfg_4            ; // 0x3290, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y0_CFG_5            reg_oecfc_y0_cfg_5            ; // 0x3294, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y0_CFG_6            reg_oecfc_y0_cfg_6            ; // 0x3298, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y0_CFG_7            reg_oecfc_y0_cfg_7            ; // 0x329C, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 0 
REG_OECFC_Y1_CFG_0            reg_oecfc_y1_cfg_0            ; // 0x32A0, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y1_CFG_1            reg_oecfc_y1_cfg_1            ; // 0x32A4, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y1_CFG_2            reg_oecfc_y1_cfg_2            ; // 0x32A8, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y1_CFG_3            reg_oecfc_y1_cfg_3            ; // 0x32AC, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y1_CFG_4            reg_oecfc_y1_cfg_4            ; // 0x32B0, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y1_CFG_5            reg_oecfc_y1_cfg_5            ; // 0x32B4, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y1_CFG_6            reg_oecfc_y1_cfg_6            ; // 0x32B8, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y1_CFG_7            reg_oecfc_y1_cfg_7            ; // 0x32BC, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 1 
REG_OECFC_Y2_CFG_0            reg_oecfc_y2_cfg_0            ; // 0x32C0, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y2_CFG_1            reg_oecfc_y2_cfg_1            ; // 0x32C4, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y2_CFG_2            reg_oecfc_y2_cfg_2            ; // 0x32C8, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y2_CFG_3            reg_oecfc_y2_cfg_3            ; // 0x32CC, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y2_CFG_4            reg_oecfc_y2_cfg_4            ; // 0x32D0, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y2_CFG_5            reg_oecfc_y2_cfg_5            ; // 0x32D4, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y2_CFG_6            reg_oecfc_y2_cfg_6            ; // 0x32D8, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y2_CFG_7            reg_oecfc_y2_cfg_7            ; // 0x32DC, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 2 
REG_OECFC_Y3_CFG_0            reg_oecfc_y3_cfg_0            ; // 0x32E0, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y3_CFG_1            reg_oecfc_y3_cfg_1            ; // 0x32E4, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y3_CFG_2            reg_oecfc_y3_cfg_2            ; // 0x32E8, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y3_CFG_3            reg_oecfc_y3_cfg_3            ; // 0x32EC, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y3_CFG_4            reg_oecfc_y3_cfg_4            ; // 0x32F0, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y3_CFG_5            reg_oecfc_y3_cfg_5            ; // 0x32F4, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y3_CFG_6            reg_oecfc_y3_cfg_6            ; // 0x32F8, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_Y3_CFG_7            reg_oecfc_y3_cfg_7            ; // 0x32FC, OECFC(raw compand) Y parameter[0.PW.0] register for symbol 3 
REG_OECFC_S0_CFG_0            reg_oecfc_s0_cfg_0            ; // 0x3300, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S0_CFG_1            reg_oecfc_s0_cfg_1            ; // 0x3304, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S0_CFG_2            reg_oecfc_s0_cfg_2            ; // 0x3308, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S0_CFG_3            reg_oecfc_s0_cfg_3            ; // 0x330C, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S0_CFG_4            reg_oecfc_s0_cfg_4            ; // 0x3310, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S0_CFG_5            reg_oecfc_s0_cfg_5            ; // 0x3314, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S0_CFG_6            reg_oecfc_s0_cfg_6            ; // 0x3318, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S0_CFG_7            reg_oecfc_s0_cfg_7            ; // 0x331C, OECFC(raw compand) [0.3.13] S parameter register for symbol 0 
REG_OECFC_S1_CFG_0            reg_oecfc_s1_cfg_0            ; // 0x3320, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S1_CFG_1            reg_oecfc_s1_cfg_1            ; // 0x3324, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S1_CFG_2            reg_oecfc_s1_cfg_2            ; // 0x3328, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S1_CFG_3            reg_oecfc_s1_cfg_3            ; // 0x332C, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S1_CFG_4            reg_oecfc_s1_cfg_4            ; // 0x3330, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S1_CFG_5            reg_oecfc_s1_cfg_5            ; // 0x3334, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S1_CFG_6            reg_oecfc_s1_cfg_6            ; // 0x3338, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S1_CFG_7            reg_oecfc_s1_cfg_7            ; // 0x333C, OECFC(raw compand) [0.3.13] S parameter register for symbol 1 
REG_OECFC_S2_CFG_0            reg_oecfc_s2_cfg_0            ; // 0x3340, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S2_CFG_1            reg_oecfc_s2_cfg_1            ; // 0x3344, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S2_CFG_2            reg_oecfc_s2_cfg_2            ; // 0x3348, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S2_CFG_3            reg_oecfc_s2_cfg_3            ; // 0x334C, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S2_CFG_4            reg_oecfc_s2_cfg_4            ; // 0x3350, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S2_CFG_5            reg_oecfc_s2_cfg_5            ; // 0x3354, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S2_CFG_6            reg_oecfc_s2_cfg_6            ; // 0x3358, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S2_CFG_7            reg_oecfc_s2_cfg_7            ; // 0x335C, OECFC(raw compand) [0.3.13] S parameter register for symbol 2 
REG_OECFC_S3_CFG_0            reg_oecfc_s3_cfg_0            ; // 0x3360, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_OECFC_S3_CFG_1            reg_oecfc_s3_cfg_1            ; // 0x3364, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_OECFC_S3_CFG_2            reg_oecfc_s3_cfg_2            ; // 0x3368, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_OECFC_S3_CFG_3            reg_oecfc_s3_cfg_3            ; // 0x336C, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_OECFC_S3_CFG_4            reg_oecfc_s3_cfg_4            ; // 0x3370, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_OECFC_S3_CFG_5            reg_oecfc_s3_cfg_5            ; // 0x3374, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_OECFC_S3_CFG_6            reg_oecfc_s3_cfg_6            ; // 0x3378, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_OECFC_S3_CFG_7            reg_oecfc_s3_cfg_7            ; // 0x337C, OECFC(raw compand) [0.3.13] S parameter register for symbol 3 
REG_SC1_CFG_0                 reg_sc1_cfg_0                 ; // 0x3810, sc1 frame cropping for sc ae/af
REG_SC1_CFG_1                 reg_sc1_cfg_1                 ; // 0x3814, SC1 cfg1 register
REG_SC1_DEC                   reg_sc1_dec                   ; // 0x3818, sc1 dec cfg register for sc ae/af, Horizontal/Vertical period/keep
REG_SC0_CFG_0                 reg_sc0_cfg_0                 ; // 0x3820, sc0 frame cropping for sc awb
REG_SC0_CFG_1                 reg_sc0_cfg_1                 ; // 0x3824, SC0 cfg1 register
REG_SC0_DEC                   reg_sc0_dec                   ; // 0x3828, sc0 dec cfg register for sc awb, Horizontal/Vertical period/keep
REG_CLKGCFG                   reg_clkgcfg                   ; // 0x400C, module clock gate config register
REG_SENSORSZ                  reg_sensorsz                  ; // 0x4028, Sensor X/Y size
REG_PMIMR                     reg_pmimr                     ; // 0x403C, Pipeline module interrupt mux register
REG_ISPINTEN                  reg_ispinten                  ; // 0x404C, ISP Interrupt Enable Register 
REG_ITIFBC0                   reg_itifbc0                   ; // 0x4060, Tiling FBC control0 regsiter
REG_ITIFBC1                   reg_itifbc1                   ; // 0x4064, Tiling FBC control1 regsiter
REG_ITIDEC0                   reg_itidec0                   ; // 0x4068, tiling write0 DEC register, Horizontal/Vertical period/keep
REG_ITIDEC1                   reg_itidec1                   ; // 0x406C, tiling write1 DEC register, Horizontal/Vertical period/keep
REG_ITICROP0                  reg_iticrop0                  ; // 0x4070, tiling write 0 cropping register (x/y start location)
REG_ITICROP1                  reg_iticrop1                  ; // 0x4074, tiling write 0 cropping register (x/y end location)
REG_ITICROP2                  reg_iticrop2                  ; // 0x4078, tiling write 1 cropping register (x/y start location)
REG_ITICROP3                  reg_iticrop3                  ; // 0x407C, tiling write 1 cropping register (x/y end location)
REG_ITIIWSR__                 reg_itiiwsr__                 ; // 0x4080, ITI write 0 Image Window Size Register
REG_ITIRWSR__                 reg_itirwsr__                 ; // 0x4084, ITI read Image Window Size Register
REG_ITIDWLSR__                reg_itidwlsr__                ; // 0x4088, ITI DRAM WRITE Line Stride Register, 64bit align,
REG_ITIDRLSR__                reg_itidrlsr__                ; // 0x408C, ITI DRAM READ Line Stride Register, 64bit align, 
REG_ITIDWYSAR0__              reg_itidwysar0__              ; // 0x4090, ITI DRAM Write Y Start Address 0 Register, 64bit align
REG_ITIDWUSAR0__              reg_itidwusar0__              ; // 0x4094, ITI DRAM Write UV Start Address 0 Register, 64bit align
REG_ITIDRYSAR0__              reg_itidrysar0__              ; // 0x4098, ITI DRAM Read Y Start Address 0  Register, 64bit align
REG_ITIDRUSAR0__              reg_itidrusar0__              ; // 0x409C, ITI DRAM Read UV Start Address 0  Register, 64bit align
REG_ITIBSR__                  reg_itibsr__                  ; // 0x40A0, ISP Tiling Interface BUSY Status Register
REG_ITIWRDFR__                reg_itiwrdfr__                ; // 0x40A4, ITI Write Data Format  Register
REG_ITIRDDFR__                reg_itirddfr__                ; // 0x40A8, ITI  Read Data Format  Register
REG_ITIDPSR__                 reg_itidpsr__                 ; // 0x40AC, ISP Tiling Interface  Data Path Select Register
REG_ITIDWYSAR1__              reg_itidwysar1__              ; // 0x40B0, ITI DRAM Write Y Start Address 1 Register, 64bit align
REG_ITIDWUSAR1__              reg_itidwusar1__              ; // 0x40B4, ITI DRAM Write UV Start Address 1 Register, 64bit align
REG_ITIDWYSAR2__              reg_itidwysar2__              ; // 0x40B8, ITI DRAM Write Y Start Address 2 Register, 64bit align
REG_ITIDWUSAR2__              reg_itidwusar2__              ; // 0x40BC, ITI DRAM Write UV Start Address 2 Register, 64bit align
REG_ITIDWYSAR3__              reg_itidwysar3__              ; // 0x40C0, ITI DRAM Write Y Start Address 3 Register, 64bit align
REG_ITIDWUSAR3__              reg_itidwusar3__              ; // 0x40C4, ITI DRAM Write UV Start Address 3 Register, 64bit align
REG_ITIDRYSAR1__              reg_itidrysar1__              ; // 0x40C8, ITI DRAM Read Y Start Address 1 Register, 64bit align
REG_ITIDRUSAR1__              reg_itidrusar1__              ; // 0x40CC, ITI DRAM Read UV Start Address 1  Register, 64bit align
REG_ITIDRYSAR2__              reg_itidrysar2__              ; // 0x40D0, ITI DRAM Read Y Start Address 2 Register, 64bit align
REG_ITIDRUSAR2__              reg_itidrusar2__              ; // 0x40D4, ITI DRAM Read UV Start Address 2  Register, 64bit align
REG_ITIDRYSAR3__              reg_itidrysar3__              ; // 0x40D8, ITI DRAM Read Y Start Address 3 Register, 64bit align
REG_ITIDRUSAR3__              reg_itidrusar3__              ; // 0x40DC, ITI DRAM Read UV Start Address 3  Register, 64bit align
REG_ITICIWSR__                reg_iticiwsr__                ; // 0x40E0, ITI Capture Image Window Size Register
REG_ITICWLSR__                reg_iticwlsr__                ; // 0x40E4, ITI Capture WRITE Line Stride Register, 64bit align, 
REG_ITICWYSAR0__              reg_iticwysar0__              ; // 0x40E8, ITI Capture Write Start Address 0 Register, 64bit align
REG_ITICWYSAR1__              reg_iticwysar1__              ; // 0x40EC, ITI Capture Write Start Address 1  Register, 64bit align
REG_ITICWYSAR2__              reg_iticwysar2__              ; // 0x40F0, ITI Capture Write Start Address 2  Register, 64bit align
REG_ITICWYSAR3__              reg_iticwysar3__              ; // 0x40F4, ITI Capture Write Start Address 3  Register, 64bit align
REG_ITICPDFR__                reg_iticpdfr__                ; // 0x40F8, ITI  Capture Package Data Format  Register
REG_ITICDPSR__                reg_iticdpsr__                ; // 0x40FC, ITI Capture  Data Path Select Register
REG_DC_RBADR                  reg_dc_rbadr                  ; // 0x4104, DC Return Buffer Address register
REG_IGRGB0                    reg_igrgb0                    ; // 0x4120, GrGb Filter Mode Register
REG_IGRGB1                    reg_igrgb1                    ; // 0x4124, GrGb Filter threshold 1 Register
REG_IGRGB2                    reg_igrgb2                    ; // 0x4128, GrGb filter threshold 2 Register
REG_ISLS0                     reg_isls0                     ; // 0x4150, Lens shading Control 0 register
REG_ISLSGBA                   reg_islsgba                   ; // 0x4154, Lens Shading Grid Buffer Start Address Register, 64bit align
REG_ISLSGBS                   reg_islsgbs                   ; // 0x4158, Lens Shading Grid Buffer Stride Register
REG_ISLSEGC                   reg_islsegc                   ; // 0x415C, Lens Shading Eliptic Gating Center Register,CX/CY,each 13bits
REG_ISLSEGSX                  reg_islsegsx                  ; // 0x4160, Lens Shading Eliptic Gating Semi Axis X Register
REG_ISLSEGSY                  reg_islsegsy                  ; // 0x4164, Lens Shading Eliptic Gating Semi Axis Y Register
REG_ISLSEGW                   reg_islsegw                   ; // 0x4168, Lens Shading Eliptic Gating Center Width Register
REG_ISLSMRD                   reg_islsmrd                   ; // 0x416C, Lens Shading Memory Read Register, axi burst len , fifo threshold (remove id)
REG_WDR_HOR                   reg_wdr_hor                   ; // 0x4280, WDR HO register, the offsets of the 1st local window from image top-left corner
REG_WDR_LWR                   reg_wdr_lwr                   ; // 0x4284, WDR local window  register
REG_WDR_THR0                  reg_wdr_thr0                  ; // 0x4288, WDR level0 window threshold regiser
REG_WDR_SCR                   reg_wdr_scr                   ; // 0x428C, WDR scale regiser
REG_WDR_IBADDR0               reg_wdr_ibaddr0               ; // 0x4290, WDR internal buffer0 address register
REG_WDR_IBADDR1               reg_wdr_ibaddr1               ; // 0x4294, WDR internal buffer1 address register
REG_WDR_THR1                  reg_wdr_thr1                  ; // 0x4298, WDR level1 window threshold regiser
REG_WDR_THR2                  reg_wdr_thr2                  ; // 0x429C, WDR level2 window threshold regiser
REG_WDR_THR3                  reg_wdr_thr3                  ; // 0x42A0, WDR level3 window threshold regiser
REG_WDR_WSR                   reg_wdr_wsr                   ; // 0x42A4, WDR spatial weight regiser
REG_WDR_VR0                   reg_wdr_vr0                   ; // 0x42A8, WDR variance table regiser
REG_WDR_VR1                   reg_wdr_vr1                   ; // 0x42AC, WDR variance table regiser
REG_WDR_VR2                   reg_wdr_vr2                   ; // 0x42B0, WDR variance table regiser
REG_WDR_VR3                   reg_wdr_vr3                   ; // 0x42B4, WDR variance table regiser
REG_WDR_WR0                   reg_wdr_wr0                   ; // 0x42B8, WDR intensity weight table regiser
REG_WDR_WR1                   reg_wdr_wr1                   ; // 0x42BC, WDR intensity weight table regiser
REG_WDR_SR0                   reg_wdr_sr0                   ; // 0x42C0, WDR intensity weigth slope regiser
REG_WDR_SR1                   reg_wdr_sr1                   ; // 0x42C4, WDR intensity weigth slope regiser
REG_WDR_SR2                   reg_wdr_sr2                   ; // 0x42C8, WDR intensity weigth slope regiser
REG_WDR_SR3                   reg_wdr_sr3                   ; // 0x42CC, WDR intensity weigth slope regiser
REG_WDR_L3HSR                 reg_wdr_l3hsr                 ; // 0x42D0, WDR L3 histogram sum factor register
REG_IGRVAL_15                 reg_igrval_15                 ; // 0x433C, Forward Gamma table Register 0
REG_IGRVAL_16                 reg_igrval_16                 ; // 0x4340, Forward Gamma table Register 1
REG_IGRVAL_17                 reg_igrval_17                 ; // 0x4344, Forward Gamma table Register 2
REG_IGRVAL_18                 reg_igrval_18                 ; // 0x4348, Forward Gamma table Register 3
REG_IGRVAL_19                 reg_igrval_19                 ; // 0x434C, Forward Gamma table Register 4
REG_IGRVAL_20                 reg_igrval_20                 ; // 0x4350, Forward Gamma table Register 5
REG_IGRVAL_21                 reg_igrval_21                 ; // 0x4354, Forward Gamma table Register 6
REG_IGRVAL_22                 reg_igrval_22                 ; // 0x4358, Forward Gamma table Register 7
REG_IGRVAL_23                 reg_igrval_23                 ; // 0x435C, Forward Gamma table Register 8
REG_IGRVAL_24                 reg_igrval_24                 ; // 0x4360, Forward Gamma table Register 9
REG_IGRVAL_25                 reg_igrval_25                 ; // 0x4364, Forward Gamma table Register 10
REG_IGRVAL_26                 reg_igrval_26                 ; // 0x4368, Forward Gamma table Register 11
REG_IGRVAL_27                 reg_igrval_27                 ; // 0x436C, Forward Gamma table Register 12
REG_IGRVAL_28                 reg_igrval_28                 ; // 0x4370, Forward Gamma table Register 13
REG_IGRVAL_29                 reg_igrval_29                 ; // 0x4374, Forward Gamma table Register 14
REG_IGRVAL_30                 reg_igrval_30                 ; // 0x4378, Reserve Gamma table Register 0
REG_IGRVAL_31                 reg_igrval_31                 ; // 0x437C, Reserve Gamma table Register 1
REG_IGRVAL_32                 reg_igrval_32                 ; // 0x4380, Reserve Gamma table Register 2
REG_IGRVAL_33                 reg_igrval_33                 ; // 0x4384, Reserve Gamma table Register 3
REG_IGRVAL_34                 reg_igrval_34                 ; // 0x4388, Reserve Gamma table Register 4
REG_IGRVAL_35                 reg_igrval_35                 ; // 0x438C, Reserve Gamma table Register 5
REG_IGRVAL_36                 reg_igrval_36                 ; // 0x4390, Reserve Gamma table Register 6
REG_IGRVAL_37                 reg_igrval_37                 ; // 0x4394, Reserve Gamma table Register 7
REG_IGRVAL_38                 reg_igrval_38                 ; // 0x4398, Reserve Gamma table Register 8
REG_IGRVAL_39                 reg_igrval_39                 ; // 0x439C, Reserve Gamma table Register 9
REG_IGRVAL_40                 reg_igrval_40                 ; // 0x43A0, Reserve Gamma table Register 10
REG_IGRVAL_41                 reg_igrval_41                 ; // 0x43A4, Reserve Gamma table Register 11
REG_IGRVAL_42                 reg_igrval_42                 ; // 0x43A8, Reserve Gamma table Register 12
REG_IGRVAL_43                 reg_igrval_43                 ; // 0x43AC, Reserve Gamma table Register 13
REG_IGRVAL_44                 reg_igrval_44                 ; // 0x43B0, Reserve Gamma table Register 14
REG_IPF0_CB_0                 reg_ipf0_cb_0                 ; // 0x4400, Purple Fringing Correction Register 0
REG_IPF0_CB_1                 reg_ipf0_cb_1                 ; // 0x4404, Purple Fringing Correction Register 0
REG_IPF0_CB_2                 reg_ipf0_cb_2                 ; // 0x4408, Purple Fringing Correction Register 1
REG_IPF0_CB_3                 reg_ipf0_cb_3                 ; // 0x440C, Purple Fringing Correction Register 1
REG_IPF0_CB_4                 reg_ipf0_cb_4                 ; // 0x4410, Purple Fringing Correction Register 2
REG_IPF0_CB_5                 reg_ipf0_cb_5                 ; // 0x4414, Purple Fringing Correction Register 2
REG_IPF0_CB_6                 reg_ipf0_cb_6                 ; // 0x4418, Purple Fringing Correction Register 3
REG_IPF0_CB_7                 reg_ipf0_cb_7                 ; // 0x441C, Purple Fringing Correction Register 3
REG_IPF0_CB_8                 reg_ipf0_cb_8                 ; // 0x4420, Purple Fringing Correction Register 4
REG_IPF0_CB_9                 reg_ipf0_cb_9                 ; // 0x4424, Purple Fringing Correction Register 4
REG_IPF0_CB_10                reg_ipf0_cb_10                ; // 0x4428, Purple Fringing Correction Register 5
REG_IPF0_CB_11                reg_ipf0_cb_11                ; // 0x442C, Purple Fringing Correction Register 5
REG_IPF0_CB_12                reg_ipf0_cb_12                ; // 0x4430, Purple Fringing Correction Register 6
REG_IPF0_CB_13                reg_ipf0_cb_13                ; // 0x4434, Purple Fringing Correction Register 6
REG_IPF0_CB_14                reg_ipf0_cb_14                ; // 0x4438, Purple Fringing Correction Register 7
REG_IPF0_CB_15                reg_ipf0_cb_15                ; // 0x443C, Purple Fringing Correction Register 7
REG_IPF0_CB_16                reg_ipf0_cb_16                ; // 0x4440, Purple Fringing Correction Register 8
REG_IPF0_CB_17                reg_ipf0_cb_17                ; // 0x4444, Purple Fringing Correction Register 8
REG_IPF0_CB_18                reg_ipf0_cb_18                ; // 0x4448, Purple Fringing Correction Register 9
REG_IPF0_CB_19                reg_ipf0_cb_19                ; // 0x444C, Purple Fringing Correction Register 9
REG_IPF0_CB_20                reg_ipf0_cb_20                ; // 0x4450, Purple Fringing Correction Register 10
REG_IPF0_CB_21                reg_ipf0_cb_21                ; // 0x4454, Purple Fringing Correction Register 10
REG_IPF0_CB_22                reg_ipf0_cb_22                ; // 0x4458, Purple Fringing Correction Register 11
REG_IPF0_CB_23                reg_ipf0_cb_23                ; // 0x445C, Purple Fringing Correction Register 11
REG_IPF0_CB_24                reg_ipf0_cb_24                ; // 0x4460, Purple Fringing Correction Register 12
REG_IPF0_CB_25                reg_ipf0_cb_25                ; // 0x4464, Purple Fringing Correction Register 12
REG_IPF1_CRG_0                reg_ipf1_crg_0                ; // 0x4468, Purple Fringing Correction Register 0
REG_IPF1_CRG_1                reg_ipf1_crg_1                ; // 0x446C, Purple Fringing Correction Register 0
REG_IPF1_CRG_2                reg_ipf1_crg_2                ; // 0x4470, Purple Fringing Correction Register 1
REG_IPF1_CRG_3                reg_ipf1_crg_3                ; // 0x4474, Purple Fringing Correction Register 1
REG_IPF1_CRG_4                reg_ipf1_crg_4                ; // 0x4478, Purple Fringing Correction Register 2
REG_IPF1_CRG_5                reg_ipf1_crg_5                ; // 0x447C, Purple Fringing Correction Register 2
REG_IPF1_CRG_6                reg_ipf1_crg_6                ; // 0x4480, Purple Fringing Correction Register 3
REG_IPF1_CRG_7                reg_ipf1_crg_7                ; // 0x4484, Purple Fringing Correction Register 3
REG_IPF1_CRG_8                reg_ipf1_crg_8                ; // 0x4488, Purple Fringing Correction Register 4
REG_IPF1_CRG_9                reg_ipf1_crg_9                ; // 0x448C, Purple Fringing Correction Register 4
REG_IPF1_CRG_10               reg_ipf1_crg_10               ; // 0x4490, Purple Fringing Correction Register 5
REG_IPF1_CRG_11               reg_ipf1_crg_11               ; // 0x4494, Purple Fringing Correction Register 5
REG_IPF1_CRG_12               reg_ipf1_crg_12               ; // 0x4498, Purple Fringing Correction Register 6
REG_IPF1_CRG_13               reg_ipf1_crg_13               ; // 0x449C, Purple Fringing Correction Register 6
REG_IPF1_CRG_14               reg_ipf1_crg_14               ; // 0x44A0, Purple Fringing Correction Register 7
REG_IPF1_CRG_15               reg_ipf1_crg_15               ; // 0x44A4, Purple Fringing Correction Register 7
REG_IPF1_CRG_16               reg_ipf1_crg_16               ; // 0x44A8, Purple Fringing Correction Register 8
REG_IPF1_CRG_17               reg_ipf1_crg_17               ; // 0x44AC, Purple Fringing Correction Register 8
REG_IPF1_CRG_18               reg_ipf1_crg_18               ; // 0x44B0, Purple Fringing Correction Register 9
REG_IPF1_CRG_19               reg_ipf1_crg_19               ; // 0x44B4, Purple Fringing Correction Register 9
REG_IPF1_CRG_20               reg_ipf1_crg_20               ; // 0x44B8, Purple Fringing Correction Register 10
REG_IPF1_CRG_21               reg_ipf1_crg_21               ; // 0x44BC, Purple Fringing Correction Register 10
REG_IPF1_CRG_22               reg_ipf1_crg_22               ; // 0x44C0, Purple Fringing Correction Register 11
REG_IPF1_CRG_23               reg_ipf1_crg_23               ; // 0x44C4, Purple Fringing Correction Register 11
REG_IPF1_CRG_24               reg_ipf1_crg_24               ; // 0x44C8, Purple Fringing Correction Register 12
REG_IPF1_CRG_25               reg_ipf1_crg_25               ; // 0x44CC, Purple Fringing Correction Register 12
REG_IPF2_F_0                  reg_ipf2_f_0                  ; // 0x4500, Purple Fringing Correction Register 
REG_IPF2_F_1                  reg_ipf2_f_1                  ; // 0x4504, Purple Fringing Correction Register 
REG_IPF2_F_2                  reg_ipf2_f_2                  ; // 0x4508, Purple Fringing Correction Register 
REG_IPF2_F_3                  reg_ipf2_f_3                  ; // 0x450C, Purple Fringing Correction Register 
REG_IPF2_F_4                  reg_ipf2_f_4                  ; // 0x4510, Purple Fringing Correction Register 
REG_IPF2_F_5                  reg_ipf2_f_5                  ; // 0x4514, Purple Fringing Correction Register 
REG_IPF2_F_6                  reg_ipf2_f_6                  ; // 0x4518, Purple Fringing Correction Register 
REG_IPF2_F_7                  reg_ipf2_f_7                  ; // 0x451C, Purple Fringing Correction Register 
REG_IPF2_F_8                  reg_ipf2_f_8                  ; // 0x4520, Purple Fringing Correction Register 
REG_IPF2_F_9                  reg_ipf2_f_9                  ; // 0x4524, Purple Fringing Correction Register 
REG_IPF2_F_10                 reg_ipf2_f_10                 ; // 0x4528, Purple Fringing Correction Register 
REG_IPF2_F_11                 reg_ipf2_f_11                 ; // 0x452C, Purple Fringing Correction Register 
REG_IPF2_F_12                 reg_ipf2_f_12                 ; // 0x4530, Purple Fringing Correction Register 
REG_IPF2_F_13                 reg_ipf2_f_13                 ; // 0x4534, Purple Fringing Correction Register 
REG_IPF2_F_14                 reg_ipf2_f_14                 ; // 0x4538, Purple Fringing Correction Register 
REG_IPF2_F_15                 reg_ipf2_f_15                 ; // 0x453C, Purple Fringing Correction Register 
REG_IPF2_F_16                 reg_ipf2_f_16                 ; // 0x4540, Purple Fringing Correction Register 
REG_IPF2_F_17                 reg_ipf2_f_17                 ; // 0x4544, Purple Fringing Correction Register 
REG_IPF2_F_18                 reg_ipf2_f_18                 ; // 0x4548, Purple Fringing Correction Register 
REG_IPF2_F_19                 reg_ipf2_f_19                 ; // 0x454C, Purple Fringing Correction Register 
REG_IPF2_F_20                 reg_ipf2_f_20                 ; // 0x4550, Purple Fringing Correction Register 
REG_IPF2_F_21                 reg_ipf2_f_21                 ; // 0x4554, Purple Fringing Correction Register 
REG_IPF2_F_22                 reg_ipf2_f_22                 ; // 0x4558, Purple Fringing Correction Register 
REG_IPF2_F_23                 reg_ipf2_f_23                 ; // 0x455C, Purple Fringing Correction Register 
REG_IPF2_F_24                 reg_ipf2_f_24                 ; // 0x4560, Purple Fringing Correction Register 
REG_IPF2_F_25                 reg_ipf2_f_25                 ; // 0x4564, Purple Fringing Correction Register 
REG_IPF2_F_26                 reg_ipf2_f_26                 ; // 0x4568, Purple Fringing Correction Register 
REG_IPF2_F_27                 reg_ipf2_f_27                 ; // 0x456C, Purple Fringing Correction Register 
REG_IPF2_F_28                 reg_ipf2_f_28                 ; // 0x4570, Purple Fringing Correction Register 
REG_IPF2_F_29                 reg_ipf2_f_29                 ; // 0x4574, Purple Fringing Correction Register 
REG_IPF2_F_30                 reg_ipf2_f_30                 ; // 0x4578, Purple Fringing Correction Register 
REG_IPF2_F_31                 reg_ipf2_f_31                 ; // 0x457C, Purple Fringing Correction Register 
REG_IPF2_F_32                 reg_ipf2_f_32                 ; // 0x4580, Purple Fringing Correction Register 
REG_IPF2_F_33                 reg_ipf2_f_33                 ; // 0x4584, Purple Fringing Correction Register 
REG_IPF2_F_34                 reg_ipf2_f_34                 ; // 0x4588, Purple Fringing Correction Register 
REG_IPF2_F_35                 reg_ipf2_f_35                 ; // 0x458C, Purple Fringing Correction Register 
REG_IPF2_F_36                 reg_ipf2_f_36                 ; // 0x4590, Purple Fringing Correction Register 
REG_IPF2_F_37                 reg_ipf2_f_37                 ; // 0x4594, Purple Fringing Correction Register 
REG_IPF2_F_38                 reg_ipf2_f_38                 ; // 0x4598, Purple Fringing Correction Register 
REG_IPF2_F_39                 reg_ipf2_f_39                 ; // 0x459C, Purple Fringing Correction Register 
REG_IPF2_F_40                 reg_ipf2_f_40                 ; // 0x45A0, Purple Fringing Correction Register 
REG_IPF2_F_41                 reg_ipf2_f_41                 ; // 0x45A4, Purple Fringing Correction Register 
REG_IPF2_F_42                 reg_ipf2_f_42                 ; // 0x45A8, Purple Fringing Correction Register 
REG_IPF2_F_43                 reg_ipf2_f_43                 ; // 0x45AC, Purple Fringing Correction Register 
REG_IPF2_F_44                 reg_ipf2_f_44                 ; // 0x45B0, Purple Fringing Correction Register 
REG_IPF2_F_45                 reg_ipf2_f_45                 ; // 0x45B4, Purple Fringing Correction Register 
REG_IPF2_F_46                 reg_ipf2_f_46                 ; // 0x45B8, Purple Fringing Correction Register 
REG_IPF2_F_47                 reg_ipf2_f_47                 ; // 0x45BC, Purple Fringing Correction Register 
REG_IPF2_F_48                 reg_ipf2_f_48                 ; // 0x45C0, Purple Fringing Correction Register 
REG_IPF2_F_49                 reg_ipf2_f_49                 ; // 0x45C4, Purple Fringing Correction Register 
REG_IPF2_F_50                 reg_ipf2_f_50                 ; // 0x45C8, Purple Fringing Correction Register 
REG_IPF2_F_51                 reg_ipf2_f_51                 ; // 0x45CC, Purple Fringing Correction Register 
REG_IPF3_RG_MD                reg_ipf3_rg_md                ; // 0x45D0, Purple Fringing Correction Register 3
REG_ICA0_CRGX_0               reg_ica0_crgx_0               ; // 0x4600, Chromatic Aberration Correction Register 0
REG_ICA0_CRGX_1               reg_ica0_crgx_1               ; // 0x4604, Chromatic Aberration Correction Register 0
REG_ICA0_CRGX_2               reg_ica0_crgx_2               ; // 0x4608, Chromatic Aberration Correction Register 1
REG_ICA0_CRGX_3               reg_ica0_crgx_3               ; // 0x460C, Chromatic Aberration Correction Register 1
REG_ICA0_CRGX_4               reg_ica0_crgx_4               ; // 0x4610, Chromatic Aberration Correction Register 2
REG_ICA0_CRGX_5               reg_ica0_crgx_5               ; // 0x4614, Chromatic Aberration Correction Register 2
REG_ICA0_CRGX_6               reg_ica0_crgx_6               ; // 0x4618, Chromatic Aberration Correction Register 3
REG_ICA0_CRGX_7               reg_ica0_crgx_7               ; // 0x461C, Chromatic Aberration Correction Register 3
REG_ICA0_CRGX_8               reg_ica0_crgx_8               ; // 0x4620, Chromatic Aberration Correction Register 4
REG_ICA0_CRGX_9               reg_ica0_crgx_9               ; // 0x4624, Chromatic Aberration Correction Register 4
REG_ICA0_CRGX_10              reg_ica0_crgx_10              ; // 0x4628, Chromatic Aberration Correction Register 5
REG_ICA0_CRGX_11              reg_ica0_crgx_11              ; // 0x462C, Chromatic Aberration Correction Register 5
REG_ICA0_CRGX_12              reg_ica0_crgx_12              ; // 0x4630, Chromatic Aberration Correction Register 6
REG_ICA0_CRGX_13              reg_ica0_crgx_13              ; // 0x4634, Chromatic Aberration Correction Register 6
REG_ICA0_CRGX_14              reg_ica0_crgx_14              ; // 0x4638, Chromatic Aberration Correction Register 7
REG_ICA0_CRGX_15              reg_ica0_crgx_15              ; // 0x463C, Chromatic Aberration Correction Register 7
REG_ICA0_CRGX_16              reg_ica0_crgx_16              ; // 0x4640, Chromatic Aberration Correction Register 8
REG_ICA0_CRGX_17              reg_ica0_crgx_17              ; // 0x4644, Chromatic Aberration Correction Register 8
REG_ICA0_CRGX_18              reg_ica0_crgx_18              ; // 0x4648, Chromatic Aberration Correction Register 9
REG_ICA0_CRGX_19              reg_ica0_crgx_19              ; // 0x464C, Chromatic Aberration Correction Register 9
REG_ICA0_CRGX_20              reg_ica0_crgx_20              ; // 0x4650, Chromatic Aberration Correction Register 10
REG_ICA0_CRGX_21              reg_ica0_crgx_21              ; // 0x4654, Chromatic Aberration Correction Register 10
REG_ICA0_CRGX_22              reg_ica0_crgx_22              ; // 0x4658, Chromatic Aberration Correction Register 11
REG_ICA0_CRGX_23              reg_ica0_crgx_23              ; // 0x465C, Chromatic Aberration Correction Register 11
REG_ICA0_CRGX_24              reg_ica0_crgx_24              ; // 0x4660, Chromatic Aberration Correction Register 12
REG_ICA0_CRGX_25              reg_ica0_crgx_25              ; // 0x4664, Chromatic Aberration Correction Register 12
REG_ICA1_CRGY_0               reg_ica1_crgy_0               ; // 0x4668, Chromatic Aberration Correction Register 0
REG_ICA1_CRGY_1               reg_ica1_crgy_1               ; // 0x466C, Chromatic Aberration Correction Register 0
REG_ICA1_CRGY_2               reg_ica1_crgy_2               ; // 0x4670, Chromatic Aberration Correction Register 1
REG_ICA1_CRGY_3               reg_ica1_crgy_3               ; // 0x4674, Chromatic Aberration Correction Register 1
REG_ICA1_CRGY_4               reg_ica1_crgy_4               ; // 0x4678, Chromatic Aberration Correction Register 2
REG_ICA1_CRGY_5               reg_ica1_crgy_5               ; // 0x467C, Chromatic Aberration Correction Register 2
REG_ICA1_CRGY_6               reg_ica1_crgy_6               ; // 0x4680, Chromatic Aberration Correction Register 3
REG_ICA1_CRGY_7               reg_ica1_crgy_7               ; // 0x4684, Chromatic Aberration Correction Register 3
REG_ICA1_CRGY_8               reg_ica1_crgy_8               ; // 0x4688, Chromatic Aberration Correction Register 4
REG_ICA1_CRGY_9               reg_ica1_crgy_9               ; // 0x468C, Chromatic Aberration Correction Register 4
REG_ICA1_CRGY_10              reg_ica1_crgy_10              ; // 0x4690, Chromatic Aberration Correction Register 5
REG_ICA1_CRGY_11              reg_ica1_crgy_11              ; // 0x4694, Chromatic Aberration Correction Register 5
REG_ICA1_CRGY_12              reg_ica1_crgy_12              ; // 0x4698, Chromatic Aberration Correction Register 6
REG_ICA1_CRGY_13              reg_ica1_crgy_13              ; // 0x469C, Chromatic Aberration Correction Register 6
REG_ICA1_CRGY_14              reg_ica1_crgy_14              ; // 0x46A0, Chromatic Aberration Correction Register 7
REG_ICA1_CRGY_15              reg_ica1_crgy_15              ; // 0x46A4, Chromatic Aberration Correction Register 7
REG_ICA1_CRGY_16              reg_ica1_crgy_16              ; // 0x46A8, Chromatic Aberration Correction Register 8
REG_ICA1_CRGY_17              reg_ica1_crgy_17              ; // 0x46AC, Chromatic Aberration Correction Register 8
REG_ICA1_CRGY_18              reg_ica1_crgy_18              ; // 0x46B0, Chromatic Aberration Correction Register 9
REG_ICA1_CRGY_19              reg_ica1_crgy_19              ; // 0x46B4, Chromatic Aberration Correction Register 9
REG_ICA1_CRGY_20              reg_ica1_crgy_20              ; // 0x46B8, Chromatic Aberration Correction Register 10
REG_ICA1_CRGY_21              reg_ica1_crgy_21              ; // 0x46BC, Chromatic Aberration Correction Register 10
REG_ICA1_CRGY_22              reg_ica1_crgy_22              ; // 0x46C0, Chromatic Aberration Correction Register 11
REG_ICA1_CRGY_23              reg_ica1_crgy_23              ; // 0x46C4, Chromatic Aberration Correction Register 11
REG_ICA1_CRGY_24              reg_ica1_crgy_24              ; // 0x46C8, Chromatic Aberration Correction Register 12
REG_ICA1_CRGY_25              reg_ica1_crgy_25              ; // 0x46CC, Chromatic Aberration Correction Register 12
REG_ICA2_CBGX_0               reg_ica2_cbgx_0               ; // 0x4700, Chromatic Aberration Correction Register 0
REG_ICA2_CBGX_1               reg_ica2_cbgx_1               ; // 0x4704, Chromatic Aberration Correction Register 0
REG_ICA2_CBGX_2               reg_ica2_cbgx_2               ; // 0x4708, Chromatic Aberration Correction Register 1
REG_ICA2_CBGX_3               reg_ica2_cbgx_3               ; // 0x470C, Chromatic Aberration Correction Register 1
REG_ICA2_CBGX_4               reg_ica2_cbgx_4               ; // 0x4710, Chromatic Aberration Correction Register 2
REG_ICA2_CBGX_5               reg_ica2_cbgx_5               ; // 0x4714, Chromatic Aberration Correction Register 2
REG_ICA2_CBGX_6               reg_ica2_cbgx_6               ; // 0x4718, Chromatic Aberration Correction Register 3
REG_ICA2_CBGX_7               reg_ica2_cbgx_7               ; // 0x471C, Chromatic Aberration Correction Register 3
REG_ICA2_CBGX_8               reg_ica2_cbgx_8               ; // 0x4720, Chromatic Aberration Correction Register 4
REG_ICA2_CBGX_9               reg_ica2_cbgx_9               ; // 0x4724, Chromatic Aberration Correction Register 4
REG_ICA2_CBGX_10              reg_ica2_cbgx_10              ; // 0x4728, Chromatic Aberration Correction Register 5
REG_ICA2_CBGX_11              reg_ica2_cbgx_11              ; // 0x472C, Chromatic Aberration Correction Register 5
REG_ICA2_CBGX_12              reg_ica2_cbgx_12              ; // 0x4730, Chromatic Aberration Correction Register 6
REG_ICA2_CBGX_13              reg_ica2_cbgx_13              ; // 0x4734, Chromatic Aberration Correction Register 6
REG_ICA2_CBGX_14              reg_ica2_cbgx_14              ; // 0x4738, Chromatic Aberration Correction Register 7
REG_ICA2_CBGX_15              reg_ica2_cbgx_15              ; // 0x473C, Chromatic Aberration Correction Register 7
REG_ICA2_CBGX_16              reg_ica2_cbgx_16              ; // 0x4740, Chromatic Aberration Correction Register 8
REG_ICA2_CBGX_17              reg_ica2_cbgx_17              ; // 0x4744, Chromatic Aberration Correction Register 8
REG_ICA2_CBGX_18              reg_ica2_cbgx_18              ; // 0x4748, Chromatic Aberration Correction Register 9
REG_ICA2_CBGX_19              reg_ica2_cbgx_19              ; // 0x474C, Chromatic Aberration Correction Register 9
REG_ICA2_CBGX_20              reg_ica2_cbgx_20              ; // 0x4750, Chromatic Aberration Correction Register 10
REG_ICA2_CBGX_21              reg_ica2_cbgx_21              ; // 0x4754, Chromatic Aberration Correction Register 10
REG_ICA2_CBGX_22              reg_ica2_cbgx_22              ; // 0x4758, Chromatic Aberration Correction Register 11
REG_ICA2_CBGX_23              reg_ica2_cbgx_23              ; // 0x475C, Chromatic Aberration Correction Register 11
REG_ICA2_CBGX_24              reg_ica2_cbgx_24              ; // 0x4760, Chromatic Aberration Correction Register 12
REG_ICA2_CBGX_25              reg_ica2_cbgx_25              ; // 0x4764, Chromatic Aberration Correction Register 12
REG_ICA3_CBGY_0               reg_ica3_cbgy_0               ; // 0x4768, Chromatic Aberration Correction Register 0
REG_ICA3_CBGY_1               reg_ica3_cbgy_1               ; // 0x476C, Chromatic Aberration Correction Register 0
REG_ICA3_CBGY_2               reg_ica3_cbgy_2               ; // 0x4770, Chromatic Aberration Correction Register 1
REG_ICA3_CBGY_3               reg_ica3_cbgy_3               ; // 0x4774, Chromatic Aberration Correction Register 1
REG_ICA3_CBGY_4               reg_ica3_cbgy_4               ; // 0x4778, Chromatic Aberration Correction Register 2
REG_ICA3_CBGY_5               reg_ica3_cbgy_5               ; // 0x477C, Chromatic Aberration Correction Register 2
REG_ICA3_CBGY_6               reg_ica3_cbgy_6               ; // 0x4780, Chromatic Aberration Correction Register 3
REG_ICA3_CBGY_7               reg_ica3_cbgy_7               ; // 0x4784, Chromatic Aberration Correction Register 3
REG_ICA3_CBGY_8               reg_ica3_cbgy_8               ; // 0x4788, Chromatic Aberration Correction Register 4
REG_ICA3_CBGY_9               reg_ica3_cbgy_9               ; // 0x478C, Chromatic Aberration Correction Register 4
REG_ICA3_CBGY_10              reg_ica3_cbgy_10              ; // 0x4790, Chromatic Aberration Correction Register 5
REG_ICA3_CBGY_11              reg_ica3_cbgy_11              ; // 0x4794, Chromatic Aberration Correction Register 5
REG_ICA3_CBGY_12              reg_ica3_cbgy_12              ; // 0x4798, Chromatic Aberration Correction Register 6
REG_ICA3_CBGY_13              reg_ica3_cbgy_13              ; // 0x479C, Chromatic Aberration Correction Register 6
REG_ICA3_CBGY_14              reg_ica3_cbgy_14              ; // 0x47A0, Chromatic Aberration Correction Register 7
REG_ICA3_CBGY_15              reg_ica3_cbgy_15              ; // 0x47A4, Chromatic Aberration Correction Register 7
REG_ICA3_CBGY_16              reg_ica3_cbgy_16              ; // 0x47A8, Chromatic Aberration Correction Register 8
REG_ICA3_CBGY_17              reg_ica3_cbgy_17              ; // 0x47AC, Chromatic Aberration Correction Register 8
REG_ICA3_CBGY_18              reg_ica3_cbgy_18              ; // 0x47B0, Chromatic Aberration Correction Register 9
REG_ICA3_CBGY_19              reg_ica3_cbgy_19              ; // 0x47B4, Chromatic Aberration Correction Register 9
REG_ICA3_CBGY_20              reg_ica3_cbgy_20              ; // 0x47B8, Chromatic Aberration Correction Register 10
REG_ICA3_CBGY_21              reg_ica3_cbgy_21              ; // 0x47BC, Chromatic Aberration Correction Register 10
REG_ICA3_CBGY_22              reg_ica3_cbgy_22              ; // 0x47C0, Chromatic Aberration Correction Register 11
REG_ICA3_CBGY_23              reg_ica3_cbgy_23              ; // 0x47C4, Chromatic Aberration Correction Register 11
REG_ICA3_CBGY_24              reg_ica3_cbgy_24              ; // 0x47C8, Chromatic Aberration Correction Register 12
REG_ICA3_CBGY_25              reg_ica3_cbgy_25              ; // 0x47CC, Chromatic Aberration Correction Register 12
REG_ICAMD_XL_CFG0             reg_icamd_xl_cfg0             ; // 0x4868, x coordinates for luminance regiser 0
REG_ICAMD_XL_CFG1             reg_icamd_xl_cfg1             ; // 0x486C, x coordinates for luminance regiser 1
REG_ICAMD_FL_CFG0             reg_icamd_fl_cfg0             ; // 0x4870, f coordinates for luminance regiser 0
REG_ICAMD_FL_CFG1             reg_icamd_fl_cfg1             ; // 0x4874, f coordinates for luminance regiser 1
REG_ICAMD_SL_CFG0             reg_icamd_sl_cfg0             ; // 0x4878, s (slope) for luminance regiser 0
REG_ICAMD_SL_CFG1             reg_icamd_sl_cfg1             ; // 0x487C, s (slope) for luminance regiser 1
REG_ICAMD_XS_CFG0             reg_icamd_xs_cfg0             ; // 0x4880, x coordinates for color saturation regiser 0
REG_ICAMD_XS_CFG1             reg_icamd_xs_cfg1             ; // 0x4884, x coordinates for color saturation regiser 1
REG_ICAMD_FS_CFG0             reg_icamd_fs_cfg0             ; // 0x4888, f coordinates for color saturation regiser 0
REG_ICAMD_FS_CFG1             reg_icamd_fs_cfg1             ; // 0x488C, f coordinates for color saturation regiser 1
REG_ICAMD_SS_CFG0             reg_icamd_ss_cfg0             ; // 0x4890, s (slope) for color saturation regiser 0
REG_ICAMD_SS_CFG1             reg_icamd_ss_cfg1             ; // 0x4894, s (slope) for color saturation regiser 1
REG_ISHRPWS2                  reg_ishrpws2                  ; // 0x4A6C, Sharpen Wsum 2nd set register
REG_ISHRPUVSMT                reg_ishrpuvsmt                ; // 0x4A70, Sharpen UV Threshold
REG_ISFRPBUF0                 reg_isfrpbuf0                 ; // 0x4A74, Sharpen LPF Buffer 0 Register, 64bit align
REG_ISFRPBUF1                 reg_isfrpbuf1                 ; // 0x4A78, Sharpen LPF Buffer 1 Register, 64bit align
REG_ISFRPBUFST                reg_isfrpbufst                ; // 0x4A7C, Sharpen LPF Buffer Status Register
REG_OBC_SUD                   reg_obc_sud                   ; // 0x4B00, OBC shadow register update enable register
REG_NL3D_SUD                  reg_nl3d_sud                  ; // 0x4B04, NL3D shadow register update enable register
REG_NL2D_SUD                  reg_nl2d_sud                  ; // 0x4B08, NL2D shadow register update enable register
REG_GRGB_SUD                  reg_grgb_sud                  ; // 0x4B0C, GRGB shadow register update enable register
REG_AWB_SUD                   reg_awb_sud                   ; // 0x4B10, AWB shadow register update enable register
REG_CCM_SUD                   reg_ccm_sud                   ; // 0x4B14, CCM shadow register update enable register
REG_LUT_SUD                   reg_lut_sud                   ; // 0x4B18, LUT shadow register update enable register
REG_GAMRGB_SUD                reg_gamrgb_sud                ; // 0x4B1C, GAMRGB shadow register update enable register
REG_R2Y_SUD                   reg_r2y_sud                   ; // 0x4B20, R2Y shadow register update enable register
REG_YCUR_SUD                  reg_ycur_sud                  ; // 0x4B24, YCUR shadow register update enable register
REG_NWED_SUD                  reg_nwed_sud                  ; // 0x4B28, NWED shadow register update enable register
REG_SHRP_SUD                  reg_shrp_sud                  ; // 0x4B2C, SHRP shadow register update enable register
REG_SAT_SUD                   reg_sat_sud                   ; // 0x4B30, SAT shadow register update enable register
REG_SC0_SUD                   reg_sc0_sud                   ; // 0x4B34, SC0 shadow register update enable register
REG_SC1_SUD                   reg_sc1_sud                   ; // 0x4B38, SC1 shadow register update enable register
REG_YHIST_SUD                 reg_yhist_sud                 ; // 0x4B3C, YHIST shadow register update enable register
REG_ITI_SUD                   reg_iti_sud                   ; // 0x4B40, Tiling shadow register update enable register
REG_WDR_SUD                   reg_wdr_sud                   ; // 0x4B44, WDR shadow register update enable register
REG_BIYUV_SUD                 reg_biyuv_sud                 ; // 0x4B48, BIYUV shadow register update enable register
REG_CTM_SUD                   reg_ctm_sud                   ; // 0x4B4C, CTM shadow register update enable register
REG_OECF_SUD                  reg_oecf_sud                  ; // 0x4B50, OECF shadow register update enable register
REG_RDMA_ENR                  reg_rdma_enr                  ; // 0x4C00, RDMA enable register
REG_RDMA_SACKR                reg_rdma_sackr                ; // 0x4C04, RDMA Software sint ack register
REG_RDMA_DADDR                reg_rdma_daddr                ; // 0x4C08, RDMA Descriptor Start Addresse register
REG_RDMA_CADDR                reg_rdma_caddr                ; // 0x4C0C, RDMA Descriptor Current Addresse register
REG_RDMA_STSR                 reg_rdma_stsr                 ; // 0x4C10, RDMA Status Register
REG_BIYUV_YSWR0               reg_biyuv_yswr0               ; // 0x4D00, BiYUV Y channel S weight table register 0
REG_BIYUV_YSWR1               reg_biyuv_yswr1               ; // 0x4D04, BiYUV Y channel S weight table register 1
REG_BIYUV_UVSWR0              reg_biyuv_uvswr0              ; // 0x4D08, BiYUV UV channel S weight table register 0
REG_BIYUV_UVSWR1              reg_biyuv_uvswr1              ; // 0x4D0C, BiYUV UV channel S weight table register  1
REG_BIYUV_YCIR                reg_biyuv_ycir                ; // 0x4D10, BiYUV Y Curve I component register
REG_BIYUV_UVCIR               reg_biyuv_uvcir               ; // 0x4D14, BiYUV UV Curve I component register
REG_BIYUV_YCDR0               reg_biyuv_ycdr0               ; // 0x4D18, BiYUV Y Curve D component register 0
REG_BIYUV_YCDR1               reg_biyuv_ycdr1               ; // 0x4D1C, BiYUV Y Curve D component register 1
REG_BIYUV_YCDR2               reg_biyuv_ycdr2               ; // 0x4D20, BiYUV Y Curve D component register 2
REG_BIYUV_YCDR3               reg_biyuv_ycdr3               ; // 0x4D24, BiYUV Y Curve D component register 3
REG_BIYUV_UVCDR0              reg_biyuv_uvcdr0              ; // 0x4D28, BiYUV UV Curve D component register 0
REG_BIYUV_UVCDR1              reg_biyuv_uvcdr1              ; // 0x4D2C, BiYUV UV Curve D component register 1
REG_BIYUV_UVCDR2              reg_biyuv_uvcdr2              ; // 0x4D30, BiYUV UV Curve D component register 2
REG_BIYUV_UVCDR3              reg_biyuv_uvcdr3              ; // 0x4D34, BiYUV UV Curve D component register 3
REG_BIYUV_YCSR0               reg_biyuv_ycsr0               ; // 0x4D38, BiYUV Y Curve S component register 0
REG_BIYUV_YCSR1               reg_biyuv_ycsr1               ; // 0x4D3C, BiYUV Y Curve S component register 1
REG_BIYUV_YCSR2               reg_biyuv_ycsr2               ; // 0x4D40, BiYUV Y Curve S component register 2
REG_BIYUV_YCSR3               reg_biyuv_ycsr3               ; // 0x4D44, BiYUV Y Curve S component register 3
REG_BIYUV_UVCSR0              reg_biyuv_uvcsr0              ; // 0x4D48, BiYUV UV Curve S component register 0
REG_BIYUV_UVCSR1              reg_biyuv_uvcsr1              ; // 0x4D4C, BiYUV UV Curve S component register 1
REG_BIYUV_UVCSR2              reg_biyuv_uvcsr2              ; // 0x4D50, BiYUV UV Curve S component register 2
REG_BIYUV_UVCSR3              reg_biyuv_uvcsr3              ; // 0x4D54, BiYUV UV Curve S component register 3
REG_CTM_HR0                   reg_ctm_hr0                   ; // 0x4E00, Color Tone Mapping H register
REG_CTM_HR1                   reg_ctm_hr1                   ; // 0x4E04, Color Tone Mapping H register
REG_CTM_HR2                   reg_ctm_hr2                   ; // 0x4E08, Color Tone Mapping H register
REG_CTM_HR3                   reg_ctm_hr3                   ; // 0x4E0C, Color Tone Mapping H register
REG_CTM_HR4                   reg_ctm_hr4                   ; // 0x4E10, Color Tone Mapping H register
REG_CTM_HR5                   reg_ctm_hr5                   ; // 0x4E14, Color Tone Mapping H register
REG_CTM_HR6                   reg_ctm_hr6                   ; // 0x4E18, Color Tone Mapping H register
REG_CTM_HR7                   reg_ctm_hr7                   ; // 0x4E1C, Color Tone Mapping H register
REG_CTM_HR8                   reg_ctm_hr8                   ; // 0x4E20, Color Tone Mapping H register
REG_CTM_HR9                   reg_ctm_hr9                   ; // 0x4E24, Color Tone Mapping H register
REG_CTM_HR10                  reg_ctm_hr10                  ; // 0x4E28, Color Tone Mapping H register
REG_CTM_HR11                  reg_ctm_hr11                  ; // 0x4E2C, Color Tone Mapping H register
REG_CTM_HR12                  reg_ctm_hr12                  ; // 0x4E30, Color Tone Mapping H register
REG_CTM_HR13                  reg_ctm_hr13                  ; // 0x4E34, Color Tone Mapping H register
REG_CTM_HR14                  reg_ctm_hr14                  ; // 0x4E38, Color Tone Mapping H register
REG_CTM_HR15                  reg_ctm_hr15                  ; // 0x4E3C, Color Tone Mapping H register
REG_CTM_HR16                  reg_ctm_hr16                  ; // 0x4E40, Color Tone Mapping H register
REG_CTM_HR17                  reg_ctm_hr17                  ; // 0x4E44, Color Tone Mapping H register
REG_CTM_HR18                  reg_ctm_hr18                  ; // 0x4E48, Color Tone Mapping H register
REG_CTM_HR19                  reg_ctm_hr19                  ; // 0x4E4C, Color Tone Mapping H register
REG_CTM_HR20                  reg_ctm_hr20                  ; // 0x4E50, Color Tone Mapping H register
REG_CTM_HR21                  reg_ctm_hr21                  ; // 0x4E54, Color Tone Mapping H register
REG_CTM_HR22                  reg_ctm_hr22                  ; // 0x4E58, Color Tone Mapping H register
REG_CTM_HR23                  reg_ctm_hr23                  ; // 0x4E5C, Color Tone Mapping H register
REG_CTM_GSR0                  reg_ctm_gsr0                  ; // 0x4E60, Color Tone Mapping GS register
REG_CTM_GSR1                  reg_ctm_gsr1                  ; // 0x4E64, Color Tone Mapping GS register
REG_CTM_GSR2                  reg_ctm_gsr2                  ; // 0x4E68, Color Tone Mapping GS register
REG_CTM_GSR3                  reg_ctm_gsr3                  ; // 0x4E6C, Color Tone Mapping GS register
REG_CTM_GSR4                  reg_ctm_gsr4                  ; // 0x4E70, Color Tone Mapping GS register
REG_CTM_GSR5                  reg_ctm_gsr5                  ; // 0x4E74, Color Tone Mapping GS register
REG_CTM_GSR6                  reg_ctm_gsr6                  ; // 0x4E78, Color Tone Mapping GS register
REG_CTM_GSR7                  reg_ctm_gsr7                  ; // 0x4E7C, Color Tone Mapping GS register
REG_CTM_GSR8                  reg_ctm_gsr8                  ; // 0x4E80, Color Tone Mapping GS register
REG_CTM_GSR9                  reg_ctm_gsr9                  ; // 0x4E84, Color Tone Mapping GS register
REG_CTM_GSR10                 reg_ctm_gsr10                 ; // 0x4E88, Color Tone Mapping GS register
REG_CTM_GSR11                 reg_ctm_gsr11                 ; // 0x4E8C, Color Tone Mapping GS register
REG_CTM_GSR12                 reg_ctm_gsr12                 ; // 0x4E90, Color Tone Mapping GS register
REG_CTM_GSR13                 reg_ctm_gsr13                 ; // 0x4E94, Color Tone Mapping GS register
REG_CTM_GSR14                 reg_ctm_gsr14                 ; // 0x4E98, Color Tone Mapping GS register
REG_CTM_GSR15                 reg_ctm_gsr15                 ; // 0x4E9C, Color Tone Mapping GS register
REG_CTM_GSR16                 reg_ctm_gsr16                 ; // 0x4EA0, Color Tone Mapping GS register
REG_CTM_GSR17                 reg_ctm_gsr17                 ; // 0x4EA4, Color Tone Mapping GS register
REG_CTM_GSR18                 reg_ctm_gsr18                 ; // 0x4EA8, Color Tone Mapping GS register
REG_CTM_GSR19                 reg_ctm_gsr19                 ; // 0x4EAC, Color Tone Mapping GS register
REG_CTM_GSR20                 reg_ctm_gsr20                 ; // 0x4EB0, Color Tone Mapping GS register
REG_CTM_GSR21                 reg_ctm_gsr21                 ; // 0x4EB4, Color Tone Mapping GS register
REG_CTM_GSR22                 reg_ctm_gsr22                 ; // 0x4EB8, Color Tone Mapping GS register
REG_CTM_GSR23                 reg_ctm_gsr23                 ; // 0x4EBC, Color Tone Mapping GS register
REG_CTM_GVR0                  reg_ctm_gvr0                  ; // 0x4EC0, Color Tone Mapping GV register
REG_CTM_GVR1                  reg_ctm_gvr1                  ; // 0x4EC4, Color Tone Mapping GV register
REG_CTM_GVR2                  reg_ctm_gvr2                  ; // 0x4EC8, Color Tone Mapping GV register
REG_CTM_GVR3                  reg_ctm_gvr3                  ; // 0x4ECC, Color Tone Mapping GV register
REG_CTM_GVR4                  reg_ctm_gvr4                  ; // 0x4ED0, Color Tone Mapping GV register
REG_CTM_GVR5                  reg_ctm_gvr5                  ; // 0x4ED4, Color Tone Mapping GV register
REG_CTM_GVR6                  reg_ctm_gvr6                  ; // 0x4ED8, Color Tone Mapping GV register
REG_CTM_GVR7                  reg_ctm_gvr7                  ; // 0x4EDC, Color Tone Mapping GV register
REG_CTM_GVR8                  reg_ctm_gvr8                  ; // 0x4EE0, Color Tone Mapping GV register
REG_CTM_GVR9                  reg_ctm_gvr9                  ; // 0x4EE4, Color Tone Mapping GV register
REG_CTM_GVR10                 reg_ctm_gvr10                 ; // 0x4EE8, Color Tone Mapping GV register
REG_CTM_GVR11                 reg_ctm_gvr11                 ; // 0x4EEC, Color Tone Mapping GV register
REG_CTM_GVR12                 reg_ctm_gvr12                 ; // 0x4EF0, Color Tone Mapping GV register
REG_CTM_GVR13                 reg_ctm_gvr13                 ; // 0x4EF4, Color Tone Mapping GV register
REG_CTM_GVR14                 reg_ctm_gvr14                 ; // 0x4EF8, Color Tone Mapping GV register
REG_CTM_GVR15                 reg_ctm_gvr15                 ; // 0x4EFC, Color Tone Mapping GV register
REG_CTM_GVR16                 reg_ctm_gvr16                 ; // 0x4F00, Color Tone Mapping GV register
REG_CTM_GVR17                 reg_ctm_gvr17                 ; // 0x4F04, Color Tone Mapping GV register
REG_CTM_GVR18                 reg_ctm_gvr18                 ; // 0x4F08, Color Tone Mapping GV register
REG_CTM_GVR19                 reg_ctm_gvr19                 ; // 0x4F0C, Color Tone Mapping GV register
REG_CTM_GVR20                 reg_ctm_gvr20                 ; // 0x4F10, Color Tone Mapping GV register
REG_CTM_GVR21                 reg_ctm_gvr21                 ; // 0x4F14, Color Tone Mapping GV register
REG_CTM_GVR22                 reg_ctm_gvr22                 ; // 0x4F18, Color Tone Mapping GV register
REG_CTM_GVR23                 reg_ctm_gvr23                 ; // 0x4F1C, Color Tone Mapping GV register
REG_I3DLUT                    reg_i3dlut[8192]              ; // 0x8000 ~ 0xFFFF, 3D LUT Color Correction Register, 0x8000~0xFFFF(0~8191)
#endif //REG_VARIABLE_ENABLE



#ifdef REG_FUNCTION_ENABLE
////////////////////////////////////////////////////////////////////////////////////////////////////
// Function void reg_init_new().
////////////////////////////////////////////////////////////////////////////////////////////////////
void reg_init_new()
{
	int i = 0;
	reg_enable_status.value = 0;
	reg_vcnt.value = 0;
	reg_csiints.value = 0;
	reg_function_mode.value = 0;
	reg_sensor.value = 0;
	reg_cfa.value = 0;
	reg_capture_window_start.value = 0;
	reg_capture_window_end.value = 0;
	reg_dump_cfg_0.value = 0;
	reg_dump_cfg_1.value = 0;
	reg_dec_cfg.value = 0;
	reg_obc_cfg.value = 0;
	reg_dc_cfg_0.value = 0;
	reg_dc_cfg_1.value = 0;
	reg_lccf_cfg_0.value = 0;
	reg_lccf_cfg_1.value = 0;
	reg_lcbq_cfg_0.value = 0;
	reg_lcbq_cfg_1.value = 0;
	reg_oba_cfg_0.value = 0;
	reg_oba_cfg_1.value = 0;
	reg_scd_cfg_0.value = 0;
	reg_scd_cfg_1.value = 0;
	reg_oba_acc_0.value = 0;
	reg_oba_acc_1.value = 0;
	reg_oba_acc_2.value = 0;
	reg_oba_acc_3.value = 0;
	reg_sc_cfg_0.value = 0;
	reg_sc_cfg_1.value = 0;
	reg_sc_af.value = 0;
	reg_sc_awb_ps_cfg_0.value = 0;
	reg_sc_awb_ps_cfg_1.value = 0;
	reg_sc_awb_ps_cfg_2.value = 0;
	reg_sc_awb_ps_cfg_3.value = 0;
	reg_sc_awb_ps_cfg_4.value = 0;
	reg_sc_dec.value = 0;
	reg_lccf_cfg_2.value = 0;
	reg_lccf_cfg_3.value = 0;
	reg_lccf_cfg_4.value = 0;
	reg_lccf_cfg_5.value = 0;
	reg_scr_adr.value = 0;
	reg_scr_dat.value = 0;
	reg_oecf_x0_cfg_0.value = 0;
	reg_oecf_x0_cfg_1.value = 0;
	reg_oecf_x0_cfg_2.value = 0;
	reg_oecf_x0_cfg_3.value = 0;
	reg_oecf_x0_cfg_4.value = 0;
	reg_oecf_x0_cfg_5.value = 0;
	reg_oecf_x0_cfg_6.value = 0;
	reg_oecf_x0_cfg_7.value = 0;
	reg_oecf_x1_cfg_0.value = 0;
	reg_oecf_x1_cfg_1.value = 0;
	reg_oecf_x1_cfg_2.value = 0;
	reg_oecf_x1_cfg_3.value = 0;
	reg_oecf_x1_cfg_4.value = 0;
	reg_oecf_x1_cfg_5.value = 0;
	reg_oecf_x1_cfg_6.value = 0;
	reg_oecf_x1_cfg_7.value = 0;
	reg_oecf_x2_cfg_0.value = 0;
	reg_oecf_x2_cfg_1.value = 0;
	reg_oecf_x2_cfg_2.value = 0;
	reg_oecf_x2_cfg_3.value = 0;
	reg_oecf_x2_cfg_4.value = 0;
	reg_oecf_x2_cfg_5.value = 0;
	reg_oecf_x2_cfg_6.value = 0;
	reg_oecf_x2_cfg_7.value = 0;
	reg_oecf_x3_cfg_0.value = 0;
	reg_oecf_x3_cfg_1.value = 0;
	reg_oecf_x3_cfg_2.value = 0;
	reg_oecf_x3_cfg_3.value = 0;
	reg_oecf_x3_cfg_4.value = 0;
	reg_oecf_x3_cfg_5.value = 0;
	reg_oecf_x3_cfg_6.value = 0;
	reg_oecf_x3_cfg_7.value = 0;
	reg_oecf_y0_cfg_0.value = 0;
	reg_oecf_y0_cfg_1.value = 0;
	reg_oecf_y0_cfg_2.value = 0;
	reg_oecf_y0_cfg_3.value = 0;
	reg_oecf_y0_cfg_4.value = 0;
	reg_oecf_y0_cfg_5.value = 0;
	reg_oecf_y0_cfg_6.value = 0;
	reg_oecf_y0_cfg_7.value = 0;
	reg_oecf_y1_cfg_0.value = 0;
	reg_oecf_y1_cfg_1.value = 0;
	reg_oecf_y1_cfg_2.value = 0;
	reg_oecf_y1_cfg_3.value = 0;
	reg_oecf_y1_cfg_4.value = 0;
	reg_oecf_y1_cfg_5.value = 0;
	reg_oecf_y1_cfg_6.value = 0;
	reg_oecf_y1_cfg_7.value = 0;
	reg_oecf_y2_cfg_0.value = 0;
	reg_oecf_y2_cfg_1.value = 0;
	reg_oecf_y2_cfg_2.value = 0;
	reg_oecf_y2_cfg_3.value = 0;
	reg_oecf_y2_cfg_4.value = 0;
	reg_oecf_y2_cfg_5.value = 0;
	reg_oecf_y2_cfg_6.value = 0;
	reg_oecf_y2_cfg_7.value = 0;
	reg_oecf_y3_cfg_0.value = 0;
	reg_oecf_y3_cfg_1.value = 0;
	reg_oecf_y3_cfg_2.value = 0;
	reg_oecf_y3_cfg_3.value = 0;
	reg_oecf_y3_cfg_4.value = 0;
	reg_oecf_y3_cfg_5.value = 0;
	reg_oecf_y3_cfg_6.value = 0;
	reg_oecf_y3_cfg_7.value = 0;
	reg_oecf_s0_cfg_0.value = 0;
	reg_oecf_s0_cfg_1.value = 0;
	reg_oecf_s0_cfg_2.value = 0;
	reg_oecf_s0_cfg_3.value = 0;
	reg_oecf_s0_cfg_4.value = 0;
	reg_oecf_s0_cfg_5.value = 0;
	reg_oecf_s0_cfg_6.value = 0;
	reg_oecf_s0_cfg_7.value = 0;
	reg_oecf_s1_cfg_0.value = 0;
	reg_oecf_s1_cfg_1.value = 0;
	reg_oecf_s1_cfg_2.value = 0;
	reg_oecf_s1_cfg_3.value = 0;
	reg_oecf_s1_cfg_4.value = 0;
	reg_oecf_s1_cfg_5.value = 0;
	reg_oecf_s1_cfg_6.value = 0;
	reg_oecf_s1_cfg_7.value = 0;
	reg_oecf_s2_cfg_0.value = 0;
	reg_oecf_s2_cfg_1.value = 0;
	reg_oecf_s2_cfg_2.value = 0;
	reg_oecf_s2_cfg_3.value = 0;
	reg_oecf_s2_cfg_4.value = 0;
	reg_oecf_s2_cfg_5.value = 0;
	reg_oecf_s2_cfg_6.value = 0;
	reg_oecf_s2_cfg_7.value = 0;
	reg_oecf_s3_cfg_0.value = 0;
	reg_oecf_s3_cfg_1.value = 0;
	reg_oecf_s3_cfg_2.value = 0;
	reg_oecf_s3_cfg_3.value = 0;
	reg_oecf_s3_cfg_4.value = 0;
	reg_oecf_s3_cfg_5.value = 0;
	reg_oecf_s3_cfg_6.value = 0;
	reg_oecf_s3_cfg_7.value = 0;
	reg_awb_x0_cfg_0.value = 0;
	reg_awb_x0_cfg_1.value = 0;
	reg_awb_x1_cfg_0.value = 0;
	reg_awb_x1_cfg_1.value = 0;
	reg_awb_x2_cfg_0.value = 0;
	reg_awb_x2_cfg_1.value = 0;
	reg_awb_x3_cfg_0.value = 0;
	reg_awb_x3_cfg_1.value = 0;
	reg_awb_y0_cfg_0.value = 0;
	reg_awb_y0_cfg_1.value = 0;
	reg_awb_y1_cfg_0.value = 0;
	reg_awb_y1_cfg_1.value = 0;
	reg_awb_y2_cfg_0.value = 0;
	reg_awb_y2_cfg_1.value = 0;
	reg_awb_y3_cfg_0.value = 0;
	reg_awb_y3_cfg_1.value = 0;
	reg_awb_s0_cfg_0.value = 0;
	reg_awb_s0_cfg_1.value = 0;
	reg_awb_s1_cfg_0.value = 0;
	reg_awb_s1_cfg_1.value = 0;
	reg_awb_s2_cfg_0.value = 0;
	reg_awb_s2_cfg_1.value = 0;
	reg_awb_s3_cfg_0.value = 0;
	reg_awb_s3_cfg_1.value = 0;
	reg_obcg_cfg_0.value = 0;
	reg_obcg_cfg_1.value = 0;
	reg_obcg_cfg_2.value = 0;
	reg_obcg_cfg_3.value = 0;
	reg_obco_cfg_0.value = 0;
	reg_obco_cfg_1.value = 0;
	reg_obco_cfg_2.value = 0;
	reg_obco_cfg_3.value = 0;
	reg_lcbq_gain0_cfg_0.value = 0;
	reg_lcbq_gain0_cfg_1.value = 0;
	reg_lcbq_gain0_cfg_2.value = 0;
	reg_lcbq_gain0_cfg_3.value = 0;
	reg_lcbq_gain0_cfg_4.value = 0;
	reg_lcbq_gain0_cfg_5.value = 0;
	reg_lcbq_gain0_cfg_6.value = 0;
	reg_lcbq_gain0_cfg_7.value = 0;
	reg_lcbq_gain0_cfg_8.value = 0;
	reg_lcbq_gain0_cfg_9.value = 0;
	reg_lcbq_gain0_cfg_10.value = 0;
	reg_lcbq_gain0_cfg_11.value = 0;
	reg_lcbq_gain0_cfg_12.value = 0;
	reg_lcbq_gain1_cfg_0.value = 0;
	reg_lcbq_gain1_cfg_1.value = 0;
	reg_lcbq_gain1_cfg_2.value = 0;
	reg_lcbq_gain1_cfg_3.value = 0;
	reg_lcbq_gain1_cfg_4.value = 0;
	reg_lcbq_gain1_cfg_5.value = 0;
	reg_lcbq_gain1_cfg_6.value = 0;
	reg_lcbq_gain1_cfg_7.value = 0;
	reg_lcbq_gain1_cfg_8.value = 0;
	reg_lcbq_gain1_cfg_9.value = 0;
	reg_lcbq_gain1_cfg_10.value = 0;
	reg_lcbq_gain1_cfg_11.value = 0;
	reg_lcbq_gain1_cfg_12.value = 0;
	reg_lcbq_gain2_cfg_0.value = 0;
	reg_lcbq_gain2_cfg_1.value = 0;
	reg_lcbq_gain2_cfg_2.value = 0;
	reg_lcbq_gain2_cfg_3.value = 0;
	reg_lcbq_gain2_cfg_4.value = 0;
	reg_lcbq_gain2_cfg_5.value = 0;
	reg_lcbq_gain2_cfg_6.value = 0;
	reg_lcbq_gain2_cfg_7.value = 0;
	reg_lcbq_gain2_cfg_8.value = 0;
	reg_lcbq_gain2_cfg_9.value = 0;
	reg_lcbq_gain2_cfg_10.value = 0;
	reg_lcbq_gain2_cfg_11.value = 0;
	reg_lcbq_gain2_cfg_12.value = 0;
	reg_lcbq_gain3_cfg_0.value = 0;
	reg_lcbq_gain3_cfg_1.value = 0;
	reg_lcbq_gain3_cfg_2.value = 0;
	reg_lcbq_gain3_cfg_3.value = 0;
	reg_lcbq_gain3_cfg_4.value = 0;
	reg_lcbq_gain3_cfg_5.value = 0;
	reg_lcbq_gain3_cfg_6.value = 0;
	reg_lcbq_gain3_cfg_7.value = 0;
	reg_lcbq_gain3_cfg_8.value = 0;
	reg_lcbq_gain3_cfg_9.value = 0;
	reg_lcbq_gain3_cfg_10.value = 0;
	reg_lcbq_gain3_cfg_11.value = 0;
	reg_lcbq_gain3_cfg_12.value = 0;
	reg_oecfhm_y_cfg_0.value = 0;
	reg_oecfhm_y_cfg_1.value = 0;
	reg_oecfhm_y_cfg_2.value = 0;
	reg_oecfhm_s_cfg_0.value = 0;
	reg_oecfhm_s_cfg_1.value = 0;
	reg_oecfhm_s_cfg_2.value = 0;
	reg_lcbq_offset0_cfg_0.value = 0;
	reg_lcbq_offset0_cfg_1.value = 0;
	reg_lcbq_offset0_cfg_2.value = 0;
	reg_lcbq_offset0_cfg_3.value = 0;
	reg_lcbq_offset0_cfg_4.value = 0;
	reg_lcbq_offset0_cfg_5.value = 0;
	reg_lcbq_offset0_cfg_6.value = 0;
	reg_lcbq_offset0_cfg_7.value = 0;
	reg_lcbq_offset0_cfg_8.value = 0;
	reg_lcbq_offset0_cfg_9.value = 0;
	reg_lcbq_offset0_cfg_10.value = 0;
	reg_lcbq_offset0_cfg_11.value = 0;
	reg_lcbq_offset0_cfg_12.value = 0;
	reg_lcbq_offset1_cfg_0.value = 0;
	reg_lcbq_offset1_cfg_1.value = 0;
	reg_lcbq_offset1_cfg_2.value = 0;
	reg_lcbq_offset1_cfg_3.value = 0;
	reg_lcbq_offset1_cfg_4.value = 0;
	reg_lcbq_offset1_cfg_5.value = 0;
	reg_lcbq_offset1_cfg_6.value = 0;
	reg_lcbq_offset1_cfg_7.value = 0;
	reg_lcbq_offset1_cfg_8.value = 0;
	reg_lcbq_offset1_cfg_9.value = 0;
	reg_lcbq_offset1_cfg_10.value = 0;
	reg_lcbq_offset1_cfg_11.value = 0;
	reg_lcbq_offset1_cfg_12.value = 0;
	reg_lcbq_offset2_cfg_0.value = 0;
	reg_lcbq_offset2_cfg_1.value = 0;
	reg_lcbq_offset2_cfg_2.value = 0;
	reg_lcbq_offset2_cfg_3.value = 0;
	reg_lcbq_offset2_cfg_4.value = 0;
	reg_lcbq_offset2_cfg_5.value = 0;
	reg_lcbq_offset2_cfg_6.value = 0;
	reg_lcbq_offset2_cfg_7.value = 0;
	reg_lcbq_offset2_cfg_8.value = 0;
	reg_lcbq_offset2_cfg_9.value = 0;
	reg_lcbq_offset2_cfg_10.value = 0;
	reg_lcbq_offset2_cfg_11.value = 0;
	reg_lcbq_offset2_cfg_12.value = 0;
	reg_lcbq_offset3_cfg_0.value = 0;
	reg_lcbq_offset3_cfg_1.value = 0;
	reg_lcbq_offset3_cfg_2.value = 0;
	reg_lcbq_offset3_cfg_3.value = 0;
	reg_lcbq_offset3_cfg_4.value = 0;
	reg_lcbq_offset3_cfg_5.value = 0;
	reg_lcbq_offset3_cfg_6.value = 0;
	reg_lcbq_offset3_cfg_7.value = 0;
	reg_lcbq_offset3_cfg_8.value = 0;
	reg_lcbq_offset3_cfg_9.value = 0;
	reg_lcbq_offset3_cfg_10.value = 0;
	reg_lcbq_offset3_cfg_11.value = 0;
	reg_lcbq_offset3_cfg_12.value = 0;
	reg_sc_awb_ws_cw0_cfg_0.value = 0;
	reg_sc_awb_ws_cw0_cfg_1.value = 0;
	reg_sc_awb_ws_cw1_cfg_0.value = 0;
	reg_sc_awb_ws_cw1_cfg_1.value = 0;
	reg_sc_awb_ws_cw2_cfg_0.value = 0;
	reg_sc_awb_ws_cw2_cfg_1.value = 0;
	reg_sc_awb_ws_cw3_cfg_0.value = 0;
	reg_sc_awb_ws_cw3_cfg_1.value = 0;
	reg_sc_awb_ws_cw4_cfg_0.value = 0;
	reg_sc_awb_ws_cw4_cfg_1.value = 0;
	reg_sc_awb_ws_cw5_cfg_0.value = 0;
	reg_sc_awb_ws_cw5_cfg_1.value = 0;
	reg_sc_awb_ws_cw6_cfg_0.value = 0;
	reg_sc_awb_ws_cw6_cfg_1.value = 0;
	reg_sc_awb_ws_cw7_cfg_0.value = 0;
	reg_sc_awb_ws_cw7_cfg_1.value = 0;
	reg_sc_awb_ws_cw8_cfg_0.value = 0;
	reg_sc_awb_ws_cw8_cfg_1.value = 0;
	reg_sc_awb_ws_cw9_cfg_0.value = 0;
	reg_sc_awb_ws_cw9_cfg_1.value = 0;
	reg_sc_awb_ws_cw10_cfg_0.value = 0;
	reg_sc_awb_ws_cw10_cfg_1.value = 0;
	reg_sc_awb_ws_cw11_cfg_0.value = 0;
	reg_sc_awb_ws_cw11_cfg_1.value = 0;
	reg_sc_awb_ws_cw12_cfg_0.value = 0;
	reg_sc_awb_ws_cw12_cfg_1.value = 0;
	reg_sc_awb_ws_iwv_cfg_0.value = 0;
	reg_sc_awb_ws_iwv_cfg_1.value = 0;
	reg_sc_awb_ws_iws_cfg_0.value = 0;
	reg_sc_awb_ws_iws_cfg_1.value = 0;
	reg_sc_awb_ws_iws_cfg_2.value = 0;
	reg_sc_awb_ws_iws_cfg_3.value = 0;
	reg_sc_awb_ws_cfg_0.value = 0;
	reg_sc_awb_ws_cfg_1.value = 0;
	reg_csicbfs.value = 0;
	reg_csicbs.value = 0;
	reg_csicbe.value = 0;
	reg_csicbmd0.value = 0;
	reg_csicbmd1.value = 0;
	reg_csicbp01.value = 0;
	reg_csicbp23.value = 0;
	reg_csicbp45.value = 0;
	reg_csicbp67.value = 0;
	reg_csicbp89.value = 0;
	reg_csicbpab.value = 0;
	reg_csicbpcd.value = 0;
	reg_csicbpef.value = 0;
	reg_csicbl1p01.value = 0;
	reg_csicbl1p23.value = 0;
	reg_csicbl1p45.value = 0;
	reg_csicbl1p67.value = 0;
	reg_csicbl1p89.value = 0;
	reg_csicbl1pab.value = 0;
	reg_csicbl1pcd.value = 0;
	reg_csicbl1pef.value = 0;
	reg_ispctrl0.value = 0;
	reg_ispstat0.value = 0;
	reg_ispctrl1.value = 0;
	reg_ifsz.value = 0;
	reg_ictc.value = 0;
	reg_idbc.value = 0;
	reg_icfam.value = 0;
	reg_isat0.value = 0;
	reg_isat1.value = 0;
	reg_isat2.value = 0;
	reg_isat3.value = 0;
	reg_isat4.value = 0;
	reg_ieshd.value = 0;
	reg_iyadj0.value = 0;
	reg_iyadj1.value = 0;
	reg_uoay.value = 0;
	reg_uoauv.value = 0;
	reg_uos.value = 0;
	reg_uopgm.value = 0;
	reg_uoaxi.value = 0;
	reg_ss0ay.value = 0;
	reg_ss0auv.value = 0;
	reg_ss0s.value = 0;
	reg_ss0hf.value = 0;
	reg_ss0vf.value = 0;
	reg_ss0iw.value = 0;
	reg_ss1ay.value = 0;
	reg_ss1auv.value = 0;
	reg_ss1s.value = 0;
	reg_ss1hf.value = 0;
	reg_ss1vf.value = 0;
	reg_ss1iw.value = 0;
	reg_ssaxi.value = 0;
	reg_itiiwsr.value = 0;
	reg_itidwlsr.value = 0;
	reg_itidwysar.value = 0;
	reg_itidwusar.value = 0;
	reg_itidrysar.value = 0;
	reg_itidrusar.value = 0;
	reg_itipdfr.value = 0;
	reg_itidrlsr.value = 0;
	reg_itibsr.value = 0;
	reg_itiair.value = 0;
	reg_itidpsr.value = 0;
	reg_dnyuv_yswr0.value = 0;
	reg_dnyuv_yswr1.value = 0;
	reg_dnyuv_cswr0.value = 0;
	reg_dnyuv_cswr1.value = 0;
	reg_dnyuv_ydr0.value = 0;
	reg_dnyuv_ydr1.value = 0;
	reg_dnyuv_ydr2.value = 0;
	reg_dnyuv_cdr0.value = 0;
	reg_dnyuv_cdr1.value = 0;
	reg_dnyuv_cdr2.value = 0;
	reg_icamd_0.value = 0;
	reg_icamd_1.value = 0;
	reg_icamd_2.value = 0;
	reg_icamd_3.value = 0;
	reg_icamd_4.value = 0;
	reg_icamd_5.value = 0;
	reg_icamd_6.value = 0;
	reg_icamd_7.value = 0;
	reg_icamd_8.value = 0;
	reg_icamd_9.value = 0;
	reg_icamd_10.value = 0;
	reg_icamd_11.value = 0;
	reg_icamd_12.value = 0;
	reg_icamd_13.value = 0;
	reg_icamd_14.value = 0;
	reg_icamd_15.value = 0;
	reg_icamd_16.value = 0;
	reg_icamd_17.value = 0;
	reg_icamd_18.value = 0;
	reg_icamd_19.value = 0;
	reg_icamd_20.value = 0;
	reg_icamd_21.value = 0;
	reg_icamd_22.value = 0;
	reg_icamd_23.value = 0;
	reg_icamd_24.value = 0;
	reg_icamd_25.value = 0;
	reg_yhist_cfg_0.value = 0;
	reg_yhist_cfg_1.value = 0;
	reg_yhist_cfg_2.value = 0;
	reg_yhist_cfg_3.value = 0;
	reg_yhist_cfg_4.value = 0;
	reg_yhist_acc_0.value = 0;
	reg_yhist_acc_1.value = 0;
	reg_yhist_acc_2.value = 0;
	reg_yhist_acc_3.value = 0;
	reg_yhist_acc_4.value = 0;
	reg_yhist_acc_5.value = 0;
	reg_yhist_acc_6.value = 0;
	reg_yhist_acc_7.value = 0;
	reg_yhist_acc_8.value = 0;
	reg_yhist_acc_9.value = 0;
	reg_yhist_acc_10.value = 0;
	reg_yhist_acc_11.value = 0;
	reg_yhist_acc_12.value = 0;
	reg_yhist_acc_13.value = 0;
	reg_yhist_acc_14.value = 0;
	reg_yhist_acc_15.value = 0;
	reg_yhist_acc_16.value = 0;
	reg_yhist_acc_17.value = 0;
	reg_yhist_acc_18.value = 0;
	reg_yhist_acc_19.value = 0;
	reg_yhist_acc_20.value = 0;
	reg_yhist_acc_21.value = 0;
	reg_yhist_acc_22.value = 0;
	reg_yhist_acc_23.value = 0;
	reg_yhist_acc_24.value = 0;
	reg_yhist_acc_25.value = 0;
	reg_yhist_acc_26.value = 0;
	reg_yhist_acc_27.value = 0;
	reg_yhist_acc_28.value = 0;
	reg_yhist_acc_29.value = 0;
	reg_yhist_acc_30.value = 0;
	reg_yhist_acc_31.value = 0;
	reg_yhist_acc_32.value = 0;
	reg_yhist_acc_33.value = 0;
	reg_yhist_acc_34.value = 0;
	reg_yhist_acc_35.value = 0;
	reg_yhist_acc_36.value = 0;
	reg_yhist_acc_37.value = 0;
	reg_yhist_acc_38.value = 0;
	reg_yhist_acc_39.value = 0;
	reg_yhist_acc_40.value = 0;
	reg_yhist_acc_41.value = 0;
	reg_yhist_acc_42.value = 0;
	reg_yhist_acc_43.value = 0;
	reg_yhist_acc_44.value = 0;
	reg_yhist_acc_45.value = 0;
	reg_yhist_acc_46.value = 0;
	reg_yhist_acc_47.value = 0;
	reg_yhist_acc_48.value = 0;
	reg_yhist_acc_49.value = 0;
	reg_yhist_acc_50.value = 0;
	reg_yhist_acc_51.value = 0;
	reg_yhist_acc_52.value = 0;
	reg_yhist_acc_53.value = 0;
	reg_yhist_acc_54.value = 0;
	reg_yhist_acc_55.value = 0;
	reg_yhist_acc_56.value = 0;
	reg_yhist_acc_57.value = 0;
	reg_yhist_acc_58.value = 0;
	reg_yhist_acc_59.value = 0;
	reg_yhist_acc_60.value = 0;
	reg_yhist_acc_61.value = 0;
	reg_yhist_acc_62.value = 0;
	reg_yhist_acc_63.value = 0;
	reg_igrval_0.value = 0;
	reg_igrval_1.value = 0;
	reg_igrval_2.value = 0;
	reg_igrval_3.value = 0;
	reg_igrval_4.value = 0;
	reg_igrval_5.value = 0;
	reg_igrval_6.value = 0;
	reg_igrval_7.value = 0;
	reg_igrval_8.value = 0;
	reg_igrval_9.value = 0;
	reg_igrval_10.value = 0;
	reg_igrval_11.value = 0;
	reg_igrval_12.value = 0;
	reg_igrval_13.value = 0;
	reg_igrval_14.value = 0;
	reg_icconv_0.value = 0;
	reg_icconv_1.value = 0;
	reg_icconv_2.value = 0;
	reg_icconv_3.value = 0;
	reg_icconv_4.value = 0;
	reg_icconv_5.value = 0;
	reg_icconv_6.value = 0;
	reg_icconv_7.value = 0;
	reg_icconv_8.value = 0;
	reg_ishrp1_0.value = 0;
	reg_ishrp1_1.value = 0;
	reg_ishrp1_2.value = 0;
	reg_ishrp1_3.value = 0;
	reg_ishrp1_4.value = 0;
	reg_ishrp1_5.value = 0;
	reg_ishrp1_6.value = 0;
	reg_ishrp1_7.value = 0;
	reg_ishrp1_8.value = 0;
	reg_ishrp1_9.value = 0;
	reg_ishrp1_10.value = 0;
	reg_ishrp1_11.value = 0;
	reg_ishrp1_12.value = 0;
	reg_ishrp1_13.value = 0;
	reg_ishrp1_14.value = 0;
	reg_ishrp2_0.value = 0;
	reg_ishrp2_1.value = 0;
	reg_ishrp2_2.value = 0;
	reg_ishrp2_3.value = 0;
	reg_ishrp2_4.value = 0;
	reg_ishrp2_5.value = 0;
	reg_ishrp3.value = 0;
	reg_iuvs1.value = 0;
	reg_iuvs2.value = 0;
	reg_iuvcks1.value = 0;
	reg_iuvcks2.value = 0;
	reg_ishrpet.value = 0;
	reg_ycurve_0.value = 0;
	reg_ycurve_1.value = 0;
	reg_ycurve_2.value = 0;
	reg_ycurve_3.value = 0;
	reg_ycurve_4.value = 0;
	reg_ycurve_5.value = 0;
	reg_ycurve_6.value = 0;
	reg_ycurve_7.value = 0;
	reg_ycurve_8.value = 0;
	reg_ycurve_9.value = 0;
	reg_ycurve_10.value = 0;
	reg_ycurve_11.value = 0;
	reg_ycurve_12.value = 0;
	reg_ycurve_13.value = 0;
	reg_ycurve_14.value = 0;
	reg_ycurve_15.value = 0;
	reg_ycurve_16.value = 0;
	reg_ycurve_17.value = 0;
	reg_ycurve_18.value = 0;
	reg_ycurve_19.value = 0;
	reg_ycurve_20.value = 0;
	reg_ycurve_21.value = 0;
	reg_ycurve_22.value = 0;
	reg_ycurve_23.value = 0;
	reg_ycurve_24.value = 0;
	reg_ycurve_25.value = 0;
	reg_ycurve_26.value = 0;
	reg_ycurve_27.value = 0;
	reg_ycurve_28.value = 0;
	reg_ycurve_29.value = 0;
	reg_ycurve_30.value = 0;
	reg_ycurve_31.value = 0;
	reg_ycurve_32.value = 0;
	reg_ycurve_33.value = 0;
	reg_ycurve_34.value = 0;
	reg_ycurve_35.value = 0;
	reg_ycurve_36.value = 0;
	reg_ycurve_37.value = 0;
	reg_ycurve_38.value = 0;
	reg_ycurve_39.value = 0;
	reg_ycurve_40.value = 0;
	reg_ycurve_41.value = 0;
	reg_ycurve_42.value = 0;
	reg_ycurve_43.value = 0;
	reg_ycurve_44.value = 0;
	reg_ycurve_45.value = 0;
	reg_ycurve_46.value = 0;
	reg_ycurve_47.value = 0;
	reg_ycurve_48.value = 0;
	reg_ycurve_49.value = 0;
	reg_ycurve_50.value = 0;
	reg_ycurve_51.value = 0;
	reg_ycurve_52.value = 0;
	reg_ycurve_53.value = 0;
	reg_ycurve_54.value = 0;
	reg_ycurve_55.value = 0;
	reg_ycurve_56.value = 0;
	reg_ycurve_57.value = 0;
	reg_ycurve_58.value = 0;
	reg_ycurve_59.value = 0;
	reg_ycurve_60.value = 0;
	reg_ycurve_61.value = 0;
	reg_ycurve_62.value = 0;
	reg_ycurve_63.value = 0;
	reg_nl3dgsigmax0.value = 0;
	reg_nl3dgsigmax1.value = 0;
	reg_nl3dgsigmax2.value = 0;
	reg_nl3dgsigmax3.value = 0;
	reg_nl3dgsigmax4.value = 0;
	reg_nl3dgsigmax5.value = 0;
	reg_nl3dgsigmax6.value = 0;
	reg_nl3dgsigmax7.value = 0;
	reg_nl3dgsigmay0.value = 0;
	reg_nl3dgsigmay1.value = 0;
	reg_nl3dgsigmay2.value = 0;
	reg_nl3dgsigmay3.value = 0;
	reg_nl3dgsigmay4.value = 0;
	reg_nl3dgsigmay5.value = 0;
	reg_nl3dgsigmay6.value = 0;
	reg_nl3dgsigmay7.value = 0;
	reg_nl3dgsigmay8.value = 0;
	reg_nl3dgsigmay9.value = 0;
	reg_nl3dgsigmay10.value = 0;
	reg_nl3dgsigmay11.value = 0;
	reg_nl3dgsigmay12.value = 0;
	reg_nl3dgsigmay13.value = 0;
	reg_nl3dgsigmay14.value = 0;
	reg_nl3dgsigmay15.value = 0;
	reg_nl3dgsigmas0.value = 0;
	reg_nl3dgsigmas1.value = 0;
	reg_nl3dgsigmas2.value = 0;
	reg_nl3dgsigmas3.value = 0;
	reg_nl3dgsigmas4.value = 0;
	reg_nl3dgsigmas5.value = 0;
	reg_nl3dgsigmas6.value = 0;
	reg_nl3dgsigmas7.value = 0;
	reg_nl3dgfiltparx0.value = 0;
	reg_nl3dgfiltparx1.value = 0;
	reg_nl3dgfiltparx2.value = 0;
	reg_nl3dgfiltparx3.value = 0;
	reg_nl3dgfiltparx4.value = 0;
	reg_nl3dgfiltparx5.value = 0;
	reg_nl3dgfiltparx6.value = 0;
	reg_nl3dgfiltparx7.value = 0;
	reg_nl3dgfiltpary0.value = 0;
	reg_nl3dgfiltpary1.value = 0;
	reg_nl3dgfiltpary2.value = 0;
	reg_nl3dgfiltpary3.value = 0;
	reg_nl3dgfiltpary4.value = 0;
	reg_nl3dgfiltpary5.value = 0;
	reg_nl3dgfiltpary6.value = 0;
	reg_nl3dgfiltpary7.value = 0;
	reg_nl3dgfiltpary8.value = 0;
	reg_nl3dgfiltpary9.value = 0;
	reg_nl3dgfiltpary10.value = 0;
	reg_nl3dgfiltpary11.value = 0;
	reg_nl3dgfiltpary12.value = 0;
	reg_nl3dgfiltpary13.value = 0;
	reg_nl3dgfiltpary14.value = 0;
	reg_nl3dgfiltpary15.value = 0;
	reg_nl3dgfiltpars0.value = 0;
	reg_nl3dgfiltpars1.value = 0;
	reg_nl3dgfiltpars2.value = 0;
	reg_nl3dgfiltpars3.value = 0;
	reg_nl3dgfiltpars4.value = 0;
	reg_nl3dgfiltpars5.value = 0;
	reg_nl3dgfiltpars6.value = 0;
	reg_nl3dgfiltpars7.value = 0;
	reg_nl3dcfg.value = 0;
	reg_dnriay.value = 0;
	reg_dnrfbdcar.value = 0;
	reg_dnris.value = 0;
	reg_dnroay.value = 0;
	reg_dnrcc2.value = 0;
	reg_dnrcc3.value = 0;
	reg_dnrisz.value = 0;
	reg_dnrosz.value = 0;
	reg_dnrcc.value = 0;
	reg_dnrcc1.value = 0;
	reg_dnrcs.value = 0;
	reg_dnrcl.value = 0;
	reg_nl3d_w2d1r.value = 0;
	reg_nl3d_d2d1r0.value = 0;
	reg_nl3d_d2d1r1.value = 0;
	reg_nl3d_d2d1g0.value = 0;
	reg_nl3d_d2d1g1.value = 0;
	reg_nl3d_d2d1b0.value = 0;
	reg_nl3d_d2d1b1.value = 0;
	reg_nl3d_s2d1r0.value = 0;
	reg_nl3d_s2d1r1.value = 0;
	reg_nl3d_w2d2r.value = 0;
	reg_nl3d_d2d2r0.value = 0;
	reg_nl3d_d2d2r1.value = 0;
	reg_nl3d_s2d2r0.value = 0;
	reg_nl3d_s2d2r1.value = 0;
	reg_nl3d_refwcx0.value = 0;
	reg_nl3d_refwcx1.value = 0;
	reg_nl3d_refwcy0.value = 0;
	reg_nl3d_refwcy1.value = 0;
	reg_nl3d_movwcx0.value = 0;
	reg_nl3d_movwcx1.value = 0;
	reg_nl3d_movwcy0.value = 0;
	reg_nl3d_movwcy1.value = 0;
	reg_nl3d_sntcx0.value = 0;
	reg_nl3d_sntcx1.value = 0;
	reg_nl3d_sntcy0.value = 0;
	reg_nl3d_sntcy1.value = 0;
	reg_nl2drsigmax0.value = 0;
	reg_nl2drsigmax1.value = 0;
	reg_nl2drsigmax2.value = 0;
	reg_nl2drsigmax3.value = 0;
	reg_nl2drsigmax4.value = 0;
	reg_nl2drsigmax5.value = 0;
	reg_nl2drsigmax6.value = 0;
	reg_nl2drsigmax7.value = 0;
	reg_nl2dgsigmax0.value = 0;
	reg_nl2dgsigmax1.value = 0;
	reg_nl2dgsigmax2.value = 0;
	reg_nl2dgsigmax3.value = 0;
	reg_nl2dgsigmax4.value = 0;
	reg_nl2dgsigmax5.value = 0;
	reg_nl2dgsigmax6.value = 0;
	reg_nl2dgsigmax7.value = 0;
	reg_nl2dbsigmax0.value = 0;
	reg_nl2dbsigmax1.value = 0;
	reg_nl2dbsigmax2.value = 0;
	reg_nl2dbsigmax3.value = 0;
	reg_nl2dbsigmax4.value = 0;
	reg_nl2dbsigmax5.value = 0;
	reg_nl2dbsigmax6.value = 0;
	reg_nl2dbsigmax7.value = 0;
	reg_nl2drsigmay0.value = 0;
	reg_nl2drsigmay1.value = 0;
	reg_nl2drsigmay2.value = 0;
	reg_nl2drsigmay3.value = 0;
	reg_nl2drsigmay4.value = 0;
	reg_nl2drsigmay5.value = 0;
	reg_nl2drsigmay6.value = 0;
	reg_nl2drsigmay7.value = 0;
	reg_nl2drsigmay8.value = 0;
	reg_nl2drsigmay9.value = 0;
	reg_nl2drsigmay10.value = 0;
	reg_nl2drsigmay11.value = 0;
	reg_nl2drsigmay12.value = 0;
	reg_nl2drsigmay13.value = 0;
	reg_nl2drsigmay14.value = 0;
	reg_nl2drsigmay15.value = 0;
	reg_nl2dgsigmay0.value = 0;
	reg_nl2dgsigmay1.value = 0;
	reg_nl2dgsigmay2.value = 0;
	reg_nl2dgsigmay3.value = 0;
	reg_nl2dgsigmay4.value = 0;
	reg_nl2dgsigmay5.value = 0;
	reg_nl2dgsigmay6.value = 0;
	reg_nl2dgsigmay7.value = 0;
	reg_nl2dgsigmay8.value = 0;
	reg_nl2dgsigmay9.value = 0;
	reg_nl2dgsigmay10.value = 0;
	reg_nl2dgsigmay11.value = 0;
	reg_nl2dgsigmay12.value = 0;
	reg_nl2dgsigmay13.value = 0;
	reg_nl2dgsigmay14.value = 0;
	reg_nl2dgsigmay15.value = 0;
	reg_nl2dbsigmay0.value = 0;
	reg_nl2dbsigmay1.value = 0;
	reg_nl2dbsigmay2.value = 0;
	reg_nl2dbsigmay3.value = 0;
	reg_nl2dbsigmay4.value = 0;
	reg_nl2dbsigmay5.value = 0;
	reg_nl2dbsigmay6.value = 0;
	reg_nl2dbsigmay7.value = 0;
	reg_nl2dbsigmay8.value = 0;
	reg_nl2dbsigmay9.value = 0;
	reg_nl2dbsigmay10.value = 0;
	reg_nl2dbsigmay11.value = 0;
	reg_nl2dbsigmay12.value = 0;
	reg_nl2dbsigmay13.value = 0;
	reg_nl2dbsigmay14.value = 0;
	reg_nl2dbsigmay15.value = 0;
	reg_nl2drsigmas0.value = 0;
	reg_nl2drsigmas1.value = 0;
	reg_nl2drsigmas2.value = 0;
	reg_nl2drsigmas3.value = 0;
	reg_nl2drsigmas4.value = 0;
	reg_nl2drsigmas5.value = 0;
	reg_nl2drsigmas6.value = 0;
	reg_nl2drsigmas7.value = 0;
	reg_nl2dgsigmas0.value = 0;
	reg_nl2dgsigmas1.value = 0;
	reg_nl2dgsigmas2.value = 0;
	reg_nl2dgsigmas3.value = 0;
	reg_nl2dgsigmas4.value = 0;
	reg_nl2dgsigmas5.value = 0;
	reg_nl2dgsigmas6.value = 0;
	reg_nl2dgsigmas7.value = 0;
	reg_nl2dbsigmas0.value = 0;
	reg_nl2dbsigmas1.value = 0;
	reg_nl2dbsigmas2.value = 0;
	reg_nl2dbsigmas3.value = 0;
	reg_nl2dbsigmas4.value = 0;
	reg_nl2dbsigmas5.value = 0;
	reg_nl2dbsigmas6.value = 0;
	reg_nl2dbsigmas7.value = 0;
	reg_nl2drfiltparx0.value = 0;
	reg_nl2drfiltparx1.value = 0;
	reg_nl2drfiltparx2.value = 0;
	reg_nl2drfiltparx3.value = 0;
	reg_nl2drfiltparx4.value = 0;
	reg_nl2drfiltparx5.value = 0;
	reg_nl2drfiltparx6.value = 0;
	reg_nl2drfiltparx7.value = 0;
	reg_nl2dgfiltparx0.value = 0;
	reg_nl2dgfiltparx1.value = 0;
	reg_nl2dgfiltparx2.value = 0;
	reg_nl2dgfiltparx3.value = 0;
	reg_nl2dgfiltparx4.value = 0;
	reg_nl2dgfiltparx5.value = 0;
	reg_nl2dgfiltparx6.value = 0;
	reg_nl2dgfiltparx7.value = 0;
	reg_nl2dbfiltparx0.value = 0;
	reg_nl2dbfiltparx1.value = 0;
	reg_nl2dbfiltparx2.value = 0;
	reg_nl2dbfiltparx3.value = 0;
	reg_nl2dbfiltparx4.value = 0;
	reg_nl2dbfiltparx5.value = 0;
	reg_nl2dbfiltparx6.value = 0;
	reg_nl2dbfiltparx7.value = 0;
	reg_nl2drfiltpary0.value = 0;
	reg_nl2drfiltpary1.value = 0;
	reg_nl2drfiltpary2.value = 0;
	reg_nl2drfiltpary3.value = 0;
	reg_nl2drfiltpary4.value = 0;
	reg_nl2drfiltpary5.value = 0;
	reg_nl2drfiltpary6.value = 0;
	reg_nl2drfiltpary7.value = 0;
	reg_nl2drfiltpary8.value = 0;
	reg_nl2drfiltpary9.value = 0;
	reg_nl2drfiltpary10.value = 0;
	reg_nl2drfiltpary11.value = 0;
	reg_nl2drfiltpary12.value = 0;
	reg_nl2drfiltpary13.value = 0;
	reg_nl2drfiltpary14.value = 0;
	reg_nl2drfiltpary15.value = 0;
	reg_nl2dgfiltpary0.value = 0;
	reg_nl2dgfiltpary1.value = 0;
	reg_nl2dgfiltpary2.value = 0;
	reg_nl2dgfiltpary3.value = 0;
	reg_nl2dgfiltpary4.value = 0;
	reg_nl2dgfiltpary5.value = 0;
	reg_nl2dgfiltpary6.value = 0;
	reg_nl2dgfiltpary7.value = 0;
	reg_nl2dgfiltpary8.value = 0;
	reg_nl2dgfiltpary9.value = 0;
	reg_nl2dgfiltpary10.value = 0;
	reg_nl2dgfiltpary11.value = 0;
	reg_nl2dgfiltpary12.value = 0;
	reg_nl2dgfiltpary13.value = 0;
	reg_nl2dgfiltpary14.value = 0;
	reg_nl2dgfiltpary15.value = 0;
	reg_nl2dbfiltpary0.value = 0;
	reg_nl2dbfiltpary1.value = 0;
	reg_nl2dbfiltpary2.value = 0;
	reg_nl2dbfiltpary3.value = 0;
	reg_nl2dbfiltpary4.value = 0;
	reg_nl2dbfiltpary5.value = 0;
	reg_nl2dbfiltpary6.value = 0;
	reg_nl2dbfiltpary7.value = 0;
	reg_nl2dbfiltpary8.value = 0;
	reg_nl2dbfiltpary9.value = 0;
	reg_nl2dbfiltpary10.value = 0;
	reg_nl2dbfiltpary11.value = 0;
	reg_nl2dbfiltpary12.value = 0;
	reg_nl2dbfiltpary13.value = 0;
	reg_nl2dbfiltpary14.value = 0;
	reg_nl2dbfiltpary15.value = 0;
	reg_nl2drfiltpars0.value = 0;
	reg_nl2drfiltpars1.value = 0;
	reg_nl2drfiltpars2.value = 0;
	reg_nl2drfiltpars3.value = 0;
	reg_nl2drfiltpars4.value = 0;
	reg_nl2drfiltpars5.value = 0;
	reg_nl2drfiltpars6.value = 0;
	reg_nl2drfiltpars7.value = 0;
	reg_nl2dgfiltpars0.value = 0;
	reg_nl2dgfiltpars1.value = 0;
	reg_nl2dgfiltpars2.value = 0;
	reg_nl2dgfiltpars3.value = 0;
	reg_nl2dgfiltpars4.value = 0;
	reg_nl2dgfiltpars5.value = 0;
	reg_nl2dgfiltpars6.value = 0;
	reg_nl2dgfiltpars7.value = 0;
	reg_nl2dbfiltpars0.value = 0;
	reg_nl2dbfiltpars1.value = 0;
	reg_nl2dbfiltpars2.value = 0;
	reg_nl2dbfiltpars3.value = 0;
	reg_nl2dbfiltpars4.value = 0;
	reg_nl2dbfiltpars5.value = 0;
	reg_nl2dbfiltpars6.value = 0;
	reg_nl2dbfiltpars7.value = 0;
	reg_nl2dcfg.value = 0;
	reg_nwedys1thx0.value = 0;
	reg_nwedys1thx1.value = 0;
	reg_nwedys1thx2.value = 0;
	reg_nwedys1thx3.value = 0;
	reg_nwedys1thx4.value = 0;
	reg_nwedys1thx5.value = 0;
	reg_nwedys1thx6.value = 0;
	reg_nwedys1thx7.value = 0;
	reg_nwedys6thx0.value = 0;
	reg_nwedys6thx1.value = 0;
	reg_nwedys6thx2.value = 0;
	reg_nwedys6thx3.value = 0;
	reg_nwedys6thx4.value = 0;
	reg_nwedys6thx5.value = 0;
	reg_nwedys6thx6.value = 0;
	reg_nwedys6thx7.value = 0;
	reg_nweduvs1thx0.value = 0;
	reg_nweduvs1thx1.value = 0;
	reg_nweduvs1thx2.value = 0;
	reg_nweduvs1thx3.value = 0;
	reg_nweduvs1thx4.value = 0;
	reg_nweduvs1thx5.value = 0;
	reg_nweduvs1thx6.value = 0;
	reg_nweduvs1thx7.value = 0;
	reg_nweduvs6thx0.value = 0;
	reg_nweduvs6thx1.value = 0;
	reg_nweduvs6thx2.value = 0;
	reg_nweduvs6thx3.value = 0;
	reg_nweduvs6thx4.value = 0;
	reg_nweduvs6thx5.value = 0;
	reg_nweduvs6thx6.value = 0;
	reg_nweduvs6thx7.value = 0;
	reg_nwedys1thy0.value = 0;
	reg_nwedys1thy1.value = 0;
	reg_nwedys1thy2.value = 0;
	reg_nwedys1thy3.value = 0;
	reg_nwedys1thy4.value = 0;
	reg_nwedys1thy5.value = 0;
	reg_nwedys1thy6.value = 0;
	reg_nwedys1thy7.value = 0;
	reg_nwedys6thy0.value = 0;
	reg_nwedys6thy1.value = 0;
	reg_nwedys6thy2.value = 0;
	reg_nwedys6thy3.value = 0;
	reg_nwedys6thy4.value = 0;
	reg_nwedys6thy5.value = 0;
	reg_nwedys6thy6.value = 0;
	reg_nwedys6thy7.value = 0;
	reg_nweduvs1thy0.value = 0;
	reg_nweduvs1thy1.value = 0;
	reg_nweduvs1thy2.value = 0;
	reg_nweduvs1thy3.value = 0;
	reg_nweduvs1thy4.value = 0;
	reg_nweduvs1thy5.value = 0;
	reg_nweduvs1thy6.value = 0;
	reg_nweduvs1thy7.value = 0;
	reg_nweduvs6thy0.value = 0;
	reg_nweduvs6thy1.value = 0;
	reg_nweduvs6thy2.value = 0;
	reg_nweduvs6thy3.value = 0;
	reg_nweduvs6thy4.value = 0;
	reg_nweduvs6thy5.value = 0;
	reg_nweduvs6thy6.value = 0;
	reg_nweduvs6thy7.value = 0;
	reg_nwedys1ths0.value = 0;
	reg_nwedys1ths1.value = 0;
	reg_nwedys1ths2.value = 0;
	reg_nwedys1ths3.value = 0;
	reg_nwedys1ths4.value = 0;
	reg_nwedys1ths5.value = 0;
	reg_nwedys1ths6.value = 0;
	reg_nwedys1ths7.value = 0;
	reg_nwedys6ths0.value = 0;
	reg_nwedys6ths1.value = 0;
	reg_nwedys6ths2.value = 0;
	reg_nwedys6ths3.value = 0;
	reg_nwedys6ths4.value = 0;
	reg_nwedys6ths5.value = 0;
	reg_nwedys6ths6.value = 0;
	reg_nwedys6ths7.value = 0;
	reg_nweduvs1ths0.value = 0;
	reg_nweduvs1ths1.value = 0;
	reg_nweduvs1ths2.value = 0;
	reg_nweduvs1ths3.value = 0;
	reg_nweduvs1ths4.value = 0;
	reg_nweduvs1ths5.value = 0;
	reg_nweduvs1ths6.value = 0;
	reg_nweduvs1ths7.value = 0;
	reg_nweduvs6ths0.value = 0;
	reg_nweduvs6ths1.value = 0;
	reg_nweduvs6ths2.value = 0;
	reg_nweduvs6ths3.value = 0;
	reg_nweduvs6ths4.value = 0;
	reg_nweduvs6ths5.value = 0;
	reg_nweduvs6ths6.value = 0;
	reg_nweduvs6ths7.value = 0;
	reg_nwedds0.value = 0;
	reg_nwedds1.value = 0;
	reg_obco_cfg_4.value = 0;
	reg_obco_cfg_5.value = 0;
	reg_obco_cfg_6.value = 0;
	reg_obco_cfg_7.value = 0;
	reg_oecfc_x0_cfg_0.value = 0;
	reg_oecfc_x0_cfg_1.value = 0;
	reg_oecfc_x0_cfg_2.value = 0;
	reg_oecfc_x0_cfg_3.value = 0;
	reg_oecfc_x0_cfg_4.value = 0;
	reg_oecfc_x0_cfg_5.value = 0;
	reg_oecfc_x0_cfg_6.value = 0;
	reg_oecfc_x0_cfg_7.value = 0;
	reg_oecfc_x1_cfg_0.value = 0;
	reg_oecfc_x1_cfg_1.value = 0;
	reg_oecfc_x1_cfg_2.value = 0;
	reg_oecfc_x1_cfg_3.value = 0;
	reg_oecfc_x1_cfg_4.value = 0;
	reg_oecfc_x1_cfg_5.value = 0;
	reg_oecfc_x1_cfg_6.value = 0;
	reg_oecfc_x1_cfg_7.value = 0;
	reg_oecfc_x2_cfg_0.value = 0;
	reg_oecfc_x2_cfg_1.value = 0;
	reg_oecfc_x2_cfg_2.value = 0;
	reg_oecfc_x2_cfg_3.value = 0;
	reg_oecfc_x2_cfg_4.value = 0;
	reg_oecfc_x2_cfg_5.value = 0;
	reg_oecfc_x2_cfg_6.value = 0;
	reg_oecfc_x2_cfg_7.value = 0;
	reg_oecfc_x3_cfg_0.value = 0;
	reg_oecfc_x3_cfg_1.value = 0;
	reg_oecfc_x3_cfg_2.value = 0;
	reg_oecfc_x3_cfg_3.value = 0;
	reg_oecfc_x3_cfg_4.value = 0;
	reg_oecfc_x3_cfg_5.value = 0;
	reg_oecfc_x3_cfg_6.value = 0;
	reg_oecfc_x3_cfg_7.value = 0;
	reg_oecfc_y0_cfg_0.value = 0;
	reg_oecfc_y0_cfg_1.value = 0;
	reg_oecfc_y0_cfg_2.value = 0;
	reg_oecfc_y0_cfg_3.value = 0;
	reg_oecfc_y0_cfg_4.value = 0;
	reg_oecfc_y0_cfg_5.value = 0;
	reg_oecfc_y0_cfg_6.value = 0;
	reg_oecfc_y0_cfg_7.value = 0;
	reg_oecfc_y1_cfg_0.value = 0;
	reg_oecfc_y1_cfg_1.value = 0;
	reg_oecfc_y1_cfg_2.value = 0;
	reg_oecfc_y1_cfg_3.value = 0;
	reg_oecfc_y1_cfg_4.value = 0;
	reg_oecfc_y1_cfg_5.value = 0;
	reg_oecfc_y1_cfg_6.value = 0;
	reg_oecfc_y1_cfg_7.value = 0;
	reg_oecfc_y2_cfg_0.value = 0;
	reg_oecfc_y2_cfg_1.value = 0;
	reg_oecfc_y2_cfg_2.value = 0;
	reg_oecfc_y2_cfg_3.value = 0;
	reg_oecfc_y2_cfg_4.value = 0;
	reg_oecfc_y2_cfg_5.value = 0;
	reg_oecfc_y2_cfg_6.value = 0;
	reg_oecfc_y2_cfg_7.value = 0;
	reg_oecfc_y3_cfg_0.value = 0;
	reg_oecfc_y3_cfg_1.value = 0;
	reg_oecfc_y3_cfg_2.value = 0;
	reg_oecfc_y3_cfg_3.value = 0;
	reg_oecfc_y3_cfg_4.value = 0;
	reg_oecfc_y3_cfg_5.value = 0;
	reg_oecfc_y3_cfg_6.value = 0;
	reg_oecfc_y3_cfg_7.value = 0;
	reg_oecfc_s0_cfg_0.value = 0;
	reg_oecfc_s0_cfg_1.value = 0;
	reg_oecfc_s0_cfg_2.value = 0;
	reg_oecfc_s0_cfg_3.value = 0;
	reg_oecfc_s0_cfg_4.value = 0;
	reg_oecfc_s0_cfg_5.value = 0;
	reg_oecfc_s0_cfg_6.value = 0;
	reg_oecfc_s0_cfg_7.value = 0;
	reg_oecfc_s1_cfg_0.value = 0;
	reg_oecfc_s1_cfg_1.value = 0;
	reg_oecfc_s1_cfg_2.value = 0;
	reg_oecfc_s1_cfg_3.value = 0;
	reg_oecfc_s1_cfg_4.value = 0;
	reg_oecfc_s1_cfg_5.value = 0;
	reg_oecfc_s1_cfg_6.value = 0;
	reg_oecfc_s1_cfg_7.value = 0;
	reg_oecfc_s2_cfg_0.value = 0;
	reg_oecfc_s2_cfg_1.value = 0;
	reg_oecfc_s2_cfg_2.value = 0;
	reg_oecfc_s2_cfg_3.value = 0;
	reg_oecfc_s2_cfg_4.value = 0;
	reg_oecfc_s2_cfg_5.value = 0;
	reg_oecfc_s2_cfg_6.value = 0;
	reg_oecfc_s2_cfg_7.value = 0;
	reg_oecfc_s3_cfg_0.value = 0;
	reg_oecfc_s3_cfg_1.value = 0;
	reg_oecfc_s3_cfg_2.value = 0;
	reg_oecfc_s3_cfg_3.value = 0;
	reg_oecfc_s3_cfg_4.value = 0;
	reg_oecfc_s3_cfg_5.value = 0;
	reg_oecfc_s3_cfg_6.value = 0;
	reg_oecfc_s3_cfg_7.value = 0;
	reg_sc1_cfg_0.value = 0;
	reg_sc1_cfg_1.value = 0;
	reg_sc1_dec.value = 0;
	reg_sc0_cfg_0.value = 0;
	reg_sc0_cfg_1.value = 0;
	reg_sc0_dec.value = 0;
	reg_clkgcfg.value = 0;
	reg_sensorsz.value = 0;
	reg_pmimr.value = 0;
	reg_ispinten.value = 0;
	reg_itifbc0.value = 0;
	reg_itifbc1.value = 0;
	reg_itidec0.value = 0;
	reg_itidec1.value = 0;
	reg_iticrop0.value = 0;
	reg_iticrop1.value = 0;
	reg_iticrop2.value = 0;
	reg_iticrop3.value = 0;
	reg_itiiwsr__.value = 0;
	reg_itirwsr__.value = 0;
	reg_itidwlsr__.value = 0;
	reg_itidrlsr__.value = 0;
	reg_itidwysar0__.value = 0;
	reg_itidwusar0__.value = 0;
	reg_itidrysar0__.value = 0;
	reg_itidrusar0__.value = 0;
	reg_itibsr__.value = 0;
	reg_itiwrdfr__.value = 0;
	reg_itirddfr__.value = 0;
	reg_itidpsr__.value = 0;
	reg_itidwysar1__.value = 0;
	reg_itidwusar1__.value = 0;
	reg_itidwysar2__.value = 0;
	reg_itidwusar2__.value = 0;
	reg_itidwysar3__.value = 0;
	reg_itidwusar3__.value = 0;
	reg_itidrysar1__.value = 0;
	reg_itidrusar1__.value = 0;
	reg_itidrysar2__.value = 0;
	reg_itidrusar2__.value = 0;
	reg_itidrysar3__.value = 0;
	reg_itidrusar3__.value = 0;
	reg_iticiwsr__.value = 0;
	reg_iticwlsr__.value = 0;
	reg_iticwysar0__.value = 0;
	reg_iticwysar1__.value = 0;
	reg_iticwysar2__.value = 0;
	reg_iticwysar3__.value = 0;
	reg_iticpdfr__.value = 0;
	reg_iticdpsr__.value = 0;
	reg_dc_rbadr.value = 0;
	reg_igrgb0.value = 0;
	reg_igrgb1.value = 0;
	reg_igrgb2.value = 0;
	reg_isls0.value = 0;
	reg_islsgba.value = 0;
	reg_islsgbs.value = 0;
	reg_islsegc.value = 0;
	reg_islsegsx.value = 0;
	reg_islsegsy.value = 0;
	reg_islsegw.value = 0;
	reg_islsmrd.value = 0;
	reg_wdr_hor.value = 0;
	reg_wdr_lwr.value = 0;
	reg_wdr_thr0.value = 0;
	reg_wdr_scr.value = 0;
	reg_wdr_ibaddr0.value = 0;
	reg_wdr_ibaddr1.value = 0;
	reg_wdr_thr1.value = 0;
	reg_wdr_thr2.value = 0;
	reg_wdr_thr3.value = 0;
	reg_wdr_wsr.value = 0;
	reg_wdr_vr0.value = 0;
	reg_wdr_vr1.value = 0;
	reg_wdr_vr2.value = 0;
	reg_wdr_vr3.value = 0;
	reg_wdr_wr0.value = 0;
	reg_wdr_wr1.value = 0;
	reg_wdr_sr0.value = 0;
	reg_wdr_sr1.value = 0;
	reg_wdr_sr2.value = 0;
	reg_wdr_sr3.value = 0;
	reg_wdr_l3hsr.value = 0;
	reg_igrval_15.value = 0;
	reg_igrval_16.value = 0;
	reg_igrval_17.value = 0;
	reg_igrval_18.value = 0;
	reg_igrval_19.value = 0;
	reg_igrval_20.value = 0;
	reg_igrval_21.value = 0;
	reg_igrval_22.value = 0;
	reg_igrval_23.value = 0;
	reg_igrval_24.value = 0;
	reg_igrval_25.value = 0;
	reg_igrval_26.value = 0;
	reg_igrval_27.value = 0;
	reg_igrval_28.value = 0;
	reg_igrval_29.value = 0;
	reg_igrval_30.value = 0;
	reg_igrval_31.value = 0;
	reg_igrval_32.value = 0;
	reg_igrval_33.value = 0;
	reg_igrval_34.value = 0;
	reg_igrval_35.value = 0;
	reg_igrval_36.value = 0;
	reg_igrval_37.value = 0;
	reg_igrval_38.value = 0;
	reg_igrval_39.value = 0;
	reg_igrval_40.value = 0;
	reg_igrval_41.value = 0;
	reg_igrval_42.value = 0;
	reg_igrval_43.value = 0;
	reg_igrval_44.value = 0;
	reg_ipf0_cb_0.value = 0;
	reg_ipf0_cb_1.value = 0;
	reg_ipf0_cb_2.value = 0;
	reg_ipf0_cb_3.value = 0;
	reg_ipf0_cb_4.value = 0;
	reg_ipf0_cb_5.value = 0;
	reg_ipf0_cb_6.value = 0;
	reg_ipf0_cb_7.value = 0;
	reg_ipf0_cb_8.value = 0;
	reg_ipf0_cb_9.value = 0;
	reg_ipf0_cb_10.value = 0;
	reg_ipf0_cb_11.value = 0;
	reg_ipf0_cb_12.value = 0;
	reg_ipf0_cb_13.value = 0;
	reg_ipf0_cb_14.value = 0;
	reg_ipf0_cb_15.value = 0;
	reg_ipf0_cb_16.value = 0;
	reg_ipf0_cb_17.value = 0;
	reg_ipf0_cb_18.value = 0;
	reg_ipf0_cb_19.value = 0;
	reg_ipf0_cb_20.value = 0;
	reg_ipf0_cb_21.value = 0;
	reg_ipf0_cb_22.value = 0;
	reg_ipf0_cb_23.value = 0;
	reg_ipf0_cb_24.value = 0;
	reg_ipf0_cb_25.value = 0;
	reg_ipf1_crg_0.value = 0;
	reg_ipf1_crg_1.value = 0;
	reg_ipf1_crg_2.value = 0;
	reg_ipf1_crg_3.value = 0;
	reg_ipf1_crg_4.value = 0;
	reg_ipf1_crg_5.value = 0;
	reg_ipf1_crg_6.value = 0;
	reg_ipf1_crg_7.value = 0;
	reg_ipf1_crg_8.value = 0;
	reg_ipf1_crg_9.value = 0;
	reg_ipf1_crg_10.value = 0;
	reg_ipf1_crg_11.value = 0;
	reg_ipf1_crg_12.value = 0;
	reg_ipf1_crg_13.value = 0;
	reg_ipf1_crg_14.value = 0;
	reg_ipf1_crg_15.value = 0;
	reg_ipf1_crg_16.value = 0;
	reg_ipf1_crg_17.value = 0;
	reg_ipf1_crg_18.value = 0;
	reg_ipf1_crg_19.value = 0;
	reg_ipf1_crg_20.value = 0;
	reg_ipf1_crg_21.value = 0;
	reg_ipf1_crg_22.value = 0;
	reg_ipf1_crg_23.value = 0;
	reg_ipf1_crg_24.value = 0;
	reg_ipf1_crg_25.value = 0;
	reg_ipf2_f_0.value = 0;
	reg_ipf2_f_1.value = 0;
	reg_ipf2_f_2.value = 0;
	reg_ipf2_f_3.value = 0;
	reg_ipf2_f_4.value = 0;
	reg_ipf2_f_5.value = 0;
	reg_ipf2_f_6.value = 0;
	reg_ipf2_f_7.value = 0;
	reg_ipf2_f_8.value = 0;
	reg_ipf2_f_9.value = 0;
	reg_ipf2_f_10.value = 0;
	reg_ipf2_f_11.value = 0;
	reg_ipf2_f_12.value = 0;
	reg_ipf2_f_13.value = 0;
	reg_ipf2_f_14.value = 0;
	reg_ipf2_f_15.value = 0;
	reg_ipf2_f_16.value = 0;
	reg_ipf2_f_17.value = 0;
	reg_ipf2_f_18.value = 0;
	reg_ipf2_f_19.value = 0;
	reg_ipf2_f_20.value = 0;
	reg_ipf2_f_21.value = 0;
	reg_ipf2_f_22.value = 0;
	reg_ipf2_f_23.value = 0;
	reg_ipf2_f_24.value = 0;
	reg_ipf2_f_25.value = 0;
	reg_ipf2_f_26.value = 0;
	reg_ipf2_f_27.value = 0;
	reg_ipf2_f_28.value = 0;
	reg_ipf2_f_29.value = 0;
	reg_ipf2_f_30.value = 0;
	reg_ipf2_f_31.value = 0;
	reg_ipf2_f_32.value = 0;
	reg_ipf2_f_33.value = 0;
	reg_ipf2_f_34.value = 0;
	reg_ipf2_f_35.value = 0;
	reg_ipf2_f_36.value = 0;
	reg_ipf2_f_37.value = 0;
	reg_ipf2_f_38.value = 0;
	reg_ipf2_f_39.value = 0;
	reg_ipf2_f_40.value = 0;
	reg_ipf2_f_41.value = 0;
	reg_ipf2_f_42.value = 0;
	reg_ipf2_f_43.value = 0;
	reg_ipf2_f_44.value = 0;
	reg_ipf2_f_45.value = 0;
	reg_ipf2_f_46.value = 0;
	reg_ipf2_f_47.value = 0;
	reg_ipf2_f_48.value = 0;
	reg_ipf2_f_49.value = 0;
	reg_ipf2_f_50.value = 0;
	reg_ipf2_f_51.value = 0;
	reg_ipf3_rg_md.value = 0;
	reg_ica0_crgx_0.value = 0;
	reg_ica0_crgx_1.value = 0;
	reg_ica0_crgx_2.value = 0;
	reg_ica0_crgx_3.value = 0;
	reg_ica0_crgx_4.value = 0;
	reg_ica0_crgx_5.value = 0;
	reg_ica0_crgx_6.value = 0;
	reg_ica0_crgx_7.value = 0;
	reg_ica0_crgx_8.value = 0;
	reg_ica0_crgx_9.value = 0;
	reg_ica0_crgx_10.value = 0;
	reg_ica0_crgx_11.value = 0;
	reg_ica0_crgx_12.value = 0;
	reg_ica0_crgx_13.value = 0;
	reg_ica0_crgx_14.value = 0;
	reg_ica0_crgx_15.value = 0;
	reg_ica0_crgx_16.value = 0;
	reg_ica0_crgx_17.value = 0;
	reg_ica0_crgx_18.value = 0;
	reg_ica0_crgx_19.value = 0;
	reg_ica0_crgx_20.value = 0;
	reg_ica0_crgx_21.value = 0;
	reg_ica0_crgx_22.value = 0;
	reg_ica0_crgx_23.value = 0;
	reg_ica0_crgx_24.value = 0;
	reg_ica0_crgx_25.value = 0;
	reg_ica1_crgy_0.value = 0;
	reg_ica1_crgy_1.value = 0;
	reg_ica1_crgy_2.value = 0;
	reg_ica1_crgy_3.value = 0;
	reg_ica1_crgy_4.value = 0;
	reg_ica1_crgy_5.value = 0;
	reg_ica1_crgy_6.value = 0;
	reg_ica1_crgy_7.value = 0;
	reg_ica1_crgy_8.value = 0;
	reg_ica1_crgy_9.value = 0;
	reg_ica1_crgy_10.value = 0;
	reg_ica1_crgy_11.value = 0;
	reg_ica1_crgy_12.value = 0;
	reg_ica1_crgy_13.value = 0;
	reg_ica1_crgy_14.value = 0;
	reg_ica1_crgy_15.value = 0;
	reg_ica1_crgy_16.value = 0;
	reg_ica1_crgy_17.value = 0;
	reg_ica1_crgy_18.value = 0;
	reg_ica1_crgy_19.value = 0;
	reg_ica1_crgy_20.value = 0;
	reg_ica1_crgy_21.value = 0;
	reg_ica1_crgy_22.value = 0;
	reg_ica1_crgy_23.value = 0;
	reg_ica1_crgy_24.value = 0;
	reg_ica1_crgy_25.value = 0;
	reg_ica2_cbgx_0.value = 0;
	reg_ica2_cbgx_1.value = 0;
	reg_ica2_cbgx_2.value = 0;
	reg_ica2_cbgx_3.value = 0;
	reg_ica2_cbgx_4.value = 0;
	reg_ica2_cbgx_5.value = 0;
	reg_ica2_cbgx_6.value = 0;
	reg_ica2_cbgx_7.value = 0;
	reg_ica2_cbgx_8.value = 0;
	reg_ica2_cbgx_9.value = 0;
	reg_ica2_cbgx_10.value = 0;
	reg_ica2_cbgx_11.value = 0;
	reg_ica2_cbgx_12.value = 0;
	reg_ica2_cbgx_13.value = 0;
	reg_ica2_cbgx_14.value = 0;
	reg_ica2_cbgx_15.value = 0;
	reg_ica2_cbgx_16.value = 0;
	reg_ica2_cbgx_17.value = 0;
	reg_ica2_cbgx_18.value = 0;
	reg_ica2_cbgx_19.value = 0;
	reg_ica2_cbgx_20.value = 0;
	reg_ica2_cbgx_21.value = 0;
	reg_ica2_cbgx_22.value = 0;
	reg_ica2_cbgx_23.value = 0;
	reg_ica2_cbgx_24.value = 0;
	reg_ica2_cbgx_25.value = 0;
	reg_ica3_cbgy_0.value = 0;
	reg_ica3_cbgy_1.value = 0;
	reg_ica3_cbgy_2.value = 0;
	reg_ica3_cbgy_3.value = 0;
	reg_ica3_cbgy_4.value = 0;
	reg_ica3_cbgy_5.value = 0;
	reg_ica3_cbgy_6.value = 0;
	reg_ica3_cbgy_7.value = 0;
	reg_ica3_cbgy_8.value = 0;
	reg_ica3_cbgy_9.value = 0;
	reg_ica3_cbgy_10.value = 0;
	reg_ica3_cbgy_11.value = 0;
	reg_ica3_cbgy_12.value = 0;
	reg_ica3_cbgy_13.value = 0;
	reg_ica3_cbgy_14.value = 0;
	reg_ica3_cbgy_15.value = 0;
	reg_ica3_cbgy_16.value = 0;
	reg_ica3_cbgy_17.value = 0;
	reg_ica3_cbgy_18.value = 0;
	reg_ica3_cbgy_19.value = 0;
	reg_ica3_cbgy_20.value = 0;
	reg_ica3_cbgy_21.value = 0;
	reg_ica3_cbgy_22.value = 0;
	reg_ica3_cbgy_23.value = 0;
	reg_ica3_cbgy_24.value = 0;
	reg_ica3_cbgy_25.value = 0;
	reg_icamd_xl_cfg0.value = 0;
	reg_icamd_xl_cfg1.value = 0;
	reg_icamd_fl_cfg0.value = 0;
	reg_icamd_fl_cfg1.value = 0;
	reg_icamd_sl_cfg0.value = 0;
	reg_icamd_sl_cfg1.value = 0;
	reg_icamd_xs_cfg0.value = 0;
	reg_icamd_xs_cfg1.value = 0;
	reg_icamd_fs_cfg0.value = 0;
	reg_icamd_fs_cfg1.value = 0;
	reg_icamd_ss_cfg0.value = 0;
	reg_icamd_ss_cfg1.value = 0;
	reg_ishrpws2.value = 0;
	reg_ishrpuvsmt.value = 0;
	reg_isfrpbuf0.value = 0;
	reg_isfrpbuf1.value = 0;
	reg_isfrpbufst.value = 0;
	reg_obc_sud.value = 0;
	reg_nl3d_sud.value = 0;
	reg_nl2d_sud.value = 0;
	reg_grgb_sud.value = 0;
	reg_awb_sud.value = 0;
	reg_ccm_sud.value = 0;
	reg_lut_sud.value = 0;
	reg_gamrgb_sud.value = 0;
	reg_r2y_sud.value = 0;
	reg_ycur_sud.value = 0;
	reg_nwed_sud.value = 0;
	reg_shrp_sud.value = 0;
	reg_sat_sud.value = 0;
	reg_sc0_sud.value = 0;
	reg_sc1_sud.value = 0;
	reg_yhist_sud.value = 0;
	reg_iti_sud.value = 0;
	reg_wdr_sud.value = 0;
	reg_biyuv_sud.value = 0;
	reg_ctm_sud.value = 0;
	reg_oecf_sud.value = 0;
	reg_rdma_enr.value = 0;
	reg_rdma_sackr.value = 0;
	reg_rdma_daddr.value = 0;
	reg_rdma_caddr.value = 0;
	reg_rdma_stsr.value = 0;
	reg_biyuv_yswr0.value = 0;
	reg_biyuv_yswr1.value = 0;
	reg_biyuv_uvswr0.value = 0;
	reg_biyuv_uvswr1.value = 0;
	reg_biyuv_ycir.value = 0;
	reg_biyuv_uvcir.value = 0;
	reg_biyuv_ycdr0.value = 0;
	reg_biyuv_ycdr1.value = 0;
	reg_biyuv_ycdr2.value = 0;
	reg_biyuv_ycdr3.value = 0;
	reg_biyuv_uvcdr0.value = 0;
	reg_biyuv_uvcdr1.value = 0;
	reg_biyuv_uvcdr2.value = 0;
	reg_biyuv_uvcdr3.value = 0;
	reg_biyuv_ycsr0.value = 0;
	reg_biyuv_ycsr1.value = 0;
	reg_biyuv_ycsr2.value = 0;
	reg_biyuv_ycsr3.value = 0;
	reg_biyuv_uvcsr0.value = 0;
	reg_biyuv_uvcsr1.value = 0;
	reg_biyuv_uvcsr2.value = 0;
	reg_biyuv_uvcsr3.value = 0;
	reg_ctm_hr0.value = 0;
	reg_ctm_hr1.value = 0;
	reg_ctm_hr2.value = 0;
	reg_ctm_hr3.value = 0;
	reg_ctm_hr4.value = 0;
	reg_ctm_hr5.value = 0;
	reg_ctm_hr6.value = 0;
	reg_ctm_hr7.value = 0;
	reg_ctm_hr8.value = 0;
	reg_ctm_hr9.value = 0;
	reg_ctm_hr10.value = 0;
	reg_ctm_hr11.value = 0;
	reg_ctm_hr12.value = 0;
	reg_ctm_hr13.value = 0;
	reg_ctm_hr14.value = 0;
	reg_ctm_hr15.value = 0;
	reg_ctm_hr16.value = 0;
	reg_ctm_hr17.value = 0;
	reg_ctm_hr18.value = 0;
	reg_ctm_hr19.value = 0;
	reg_ctm_hr20.value = 0;
	reg_ctm_hr21.value = 0;
	reg_ctm_hr22.value = 0;
	reg_ctm_hr23.value = 0;
	reg_ctm_gsr0.value = 0;
	reg_ctm_gsr1.value = 0;
	reg_ctm_gsr2.value = 0;
	reg_ctm_gsr3.value = 0;
	reg_ctm_gsr4.value = 0;
	reg_ctm_gsr5.value = 0;
	reg_ctm_gsr6.value = 0;
	reg_ctm_gsr7.value = 0;
	reg_ctm_gsr8.value = 0;
	reg_ctm_gsr9.value = 0;
	reg_ctm_gsr10.value = 0;
	reg_ctm_gsr11.value = 0;
	reg_ctm_gsr12.value = 0;
	reg_ctm_gsr13.value = 0;
	reg_ctm_gsr14.value = 0;
	reg_ctm_gsr15.value = 0;
	reg_ctm_gsr16.value = 0;
	reg_ctm_gsr17.value = 0;
	reg_ctm_gsr18.value = 0;
	reg_ctm_gsr19.value = 0;
	reg_ctm_gsr20.value = 0;
	reg_ctm_gsr21.value = 0;
	reg_ctm_gsr22.value = 0;
	reg_ctm_gsr23.value = 0;
	reg_ctm_gvr0.value = 0;
	reg_ctm_gvr1.value = 0;
	reg_ctm_gvr2.value = 0;
	reg_ctm_gvr3.value = 0;
	reg_ctm_gvr4.value = 0;
	reg_ctm_gvr5.value = 0;
	reg_ctm_gvr6.value = 0;
	reg_ctm_gvr7.value = 0;
	reg_ctm_gvr8.value = 0;
	reg_ctm_gvr9.value = 0;
	reg_ctm_gvr10.value = 0;
	reg_ctm_gvr11.value = 0;
	reg_ctm_gvr12.value = 0;
	reg_ctm_gvr13.value = 0;
	reg_ctm_gvr14.value = 0;
	reg_ctm_gvr15.value = 0;
	reg_ctm_gvr16.value = 0;
	reg_ctm_gvr17.value = 0;
	reg_ctm_gvr18.value = 0;
	reg_ctm_gvr19.value = 0;
	reg_ctm_gvr20.value = 0;
	reg_ctm_gvr21.value = 0;
	reg_ctm_gvr22.value = 0;
	reg_ctm_gvr23.value = 0;
	for (i = 0; i < 8192; i++)
		reg_i3dlut[i].value = 0;
}



////////////////////////////////////////////////////////////////////////////////////////////////////
// Function void reg_write_new().
////////////////////////////////////////////////////////////////////////////////////////////////////
void reg_write_new(UINT32 addr, UINT32 data, UINT32 byte, UINT32 mask, UINT32 line_no)
{
	UINT32 d_tmp, m_tmp;

	// adjust mask acc to byte enable (ignore mask value for now)
	mask = 0;

	if (byte & 0x01) mask |= 0x000000ff;
	if (byte & 0x02) mask |= 0x0000ff00;
	if (byte & 0x04) mask |= 0x00ff0000;
	if (byte & 0x08) mask |= 0xff000000;

	switch (addr)
	{
		case 0x0000:
			// Lsb: 0, Len: 1, [0] CSI enable.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_enable_status.field.csi_en = (d_tmp & m_tmp) | (reg_enable_status.field.csi_en & ~m_tmp);

			// Lsb: 1, Len: 1, [1] (Read-Only)
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_enable_status.field.csi_busy = (d_tmp & m_tmp) | (reg_enable_status.field.csi_busy & ~m_tmp);

			// Lsb: 2, Len: 1, [2] (Read-Only)
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_enable_status.field.scd_done = (d_tmp & m_tmp) | (reg_enable_status.field.scd_done & ~m_tmp);

			// Lsb: 3, Len: 1, [3] (Read-Only)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_enable_status.field.itu656_field = (d_tmp & m_tmp) | (reg_enable_status.field.itu656_field & ~m_tmp);

			// Lsb: 4, Len: 1, [4] (Read-Only)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_enable_status.field.itu656_error = (d_tmp & m_tmp) | (reg_enable_status.field.itu656_error & ~m_tmp);

			// Lsb: 5, Len: 1, [5] Reserved.
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_enable_status.field.vs_done = (d_tmp & m_tmp) | (reg_enable_status.field.vs_done & ~m_tmp);

			// Lsb: 6, Len: 1, [6] (Read-Only).
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000001;
			reg_enable_status.field.scd_error = (d_tmp & m_tmp) | (reg_enable_status.field.scd_error & ~m_tmp);

			// Lsb: 7, Len: 25, [31:7] Reserved.
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x01FFFFFF;
			reg_enable_status.field.rsvd7 = (d_tmp & m_tmp) | (reg_enable_status.field.rsvd7 & ~m_tmp);
			break;

		case 0x0004:
			// Lsb: 0, Len: 16, [15:0] V counter.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_vcnt.field.cro_vcnt = (d_tmp & m_tmp) | (reg_vcnt.field.cro_vcnt & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserved.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_vcnt.field.remainder_wcnt = (d_tmp & m_tmp) | (reg_vcnt.field.remainder_wcnt & ~m_tmp);
			break;

		case 0x0008:
			// Lsb: 0, Len: 16, [15:0] Line interrupt line number
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_csiints.field.int = (d_tmp & m_tmp) | (reg_csiints.field.int & ~m_tmp);

			// Lsb: 16, Len: 1, [16] Shadow update enable
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000001;
			reg_csiints.field.ud = (d_tmp & m_tmp) | (reg_csiints.field.ud & ~m_tmp);

			// Lsb: 17, Len: 1, [17] Shadow update mode
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000001;
			reg_csiints.field.udm = (d_tmp & m_tmp) | (reg_csiints.field.udm & ~m_tmp);
			break;

		case 0x0010:
			// Lsb: 0, Len: 1, [0] enable DC .
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_function_mode.field.dc_en = (d_tmp & m_tmp) | (reg_function_mode.field.dc_en & ~m_tmp);

			// Lsb: 1, Len: 1, [1] enable Raw Decimation .
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_function_mode.field.dec_en = (d_tmp & m_tmp) | (reg_function_mode.field.dec_en & ~m_tmp);

			// Lsb: 2, Len: 1, [2] enable OBC .
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_function_mode.field.obc_en = (d_tmp & m_tmp) | (reg_function_mode.field.obc_en & ~m_tmp);

			// Lsb: 3, Len: 1, [3] enable LCBQ .
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_function_mode.field.lcbq_en = (d_tmp & m_tmp) | (reg_function_mode.field.lcbq_en & ~m_tmp);

			// Lsb: 4, Len: 1, [4] enable OECF .
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_function_mode.field.oecf_en = (d_tmp & m_tmp) | (reg_function_mode.field.oecf_en & ~m_tmp);

			// Lsb: 5, Len: 1, [5] enable OECF Hermite .
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_function_mode.field.oecfhm_en = (d_tmp & m_tmp) | (reg_function_mode.field.oecfhm_en & ~m_tmp);

			// Lsb: 6, Len: 1, [6] enable LCCF .
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000001;
			reg_function_mode.field.lccf_en = (d_tmp & m_tmp) | (reg_function_mode.field.lccf_en & ~m_tmp);

			// Lsb: 7, Len: 1, [7] enable AWB WB Gain.
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_function_mode.field.awb_en = (d_tmp & m_tmp) | (reg_function_mode.field.awb_en & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] reserved
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_function_mode.field.rsvd8 = (d_tmp & m_tmp) | (reg_function_mode.field.rsvd8 & ~m_tmp);

			// Lsb: 16, Len: 1, [16] enable OBA .
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000001;
			reg_function_mode.field.oba_en = (d_tmp & m_tmp) | (reg_function_mode.field.oba_en & ~m_tmp);

			// Lsb: 17, Len: 1, [17] enable SC.
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000001;
			reg_function_mode.field.sc_en = (d_tmp & m_tmp) | (reg_function_mode.field.sc_en & ~m_tmp);

			// Lsb: 18, Len: 1, [18] Reserved.
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_function_mode.field.vs_en = (d_tmp & m_tmp) | (reg_function_mode.field.vs_en & ~m_tmp);

			// Lsb: 19, Len: 1, [19] enable DUMP.
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_function_mode.field.dump_en = (d_tmp & m_tmp) | (reg_function_mode.field.dump_en & ~m_tmp);
			break;

		case 0x0014:
			// Lsb: 0, Len: 1, [0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_sensor.field.imager_sel = (d_tmp & m_tmp) | (reg_sensor.field.imager_sel & ~m_tmp);

			// Lsb: 1, Len: 1, [1] 
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_sensor.field.itu656_en = (d_tmp & m_tmp) | (reg_sensor.field.itu656_en & ~m_tmp);

			// Lsb: 2, Len: 2, [3:2] inveret when set to high
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000003;
			reg_sensor.field.dvp_sync_pol = (d_tmp & m_tmp) | (reg_sensor.field.dvp_sync_pol & ~m_tmp);
			break;

		case 0x0018:
			// Lsb: 0, Len: 2, [1:0] Symbol of the 1st Pixel on the 1st Line
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_cfa.field.sym00 = (d_tmp & m_tmp) | (reg_cfa.field.sym00 & ~m_tmp);

			// Lsb: 2, Len: 2, [3:2] Symbol of the 2nd Pixel on the 1st Line
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000003;
			reg_cfa.field.sym01 = (d_tmp & m_tmp) | (reg_cfa.field.sym01 & ~m_tmp);

			// Lsb: 4, Len: 2, [5:4] Symbol of the 3rd Pixel on the 1st Line
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000003;
			reg_cfa.field.sym02 = (d_tmp & m_tmp) | (reg_cfa.field.sym02 & ~m_tmp);

			// Lsb: 6, Len: 2, [7:6] Symbol of the 4th Pixel on the 1st Line
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000003;
			reg_cfa.field.sym03 = (d_tmp & m_tmp) | (reg_cfa.field.sym03 & ~m_tmp);

			// Lsb: 8, Len: 2, [9:8] Symbol of the 1st Pixel on the 2nd Line
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000003;
			reg_cfa.field.sym10 = (d_tmp & m_tmp) | (reg_cfa.field.sym10 & ~m_tmp);

			// Lsb: 10, Len: 2, [11:10] Symbol of the 2nd Pixel on the 2nd Line
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000003;
			reg_cfa.field.sym11 = (d_tmp & m_tmp) | (reg_cfa.field.sym11 & ~m_tmp);

			// Lsb: 12, Len: 2, [13:12] Symbol of the 3rd Pixel on the 2nd Line
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000003;
			reg_cfa.field.sym12 = (d_tmp & m_tmp) | (reg_cfa.field.sym12 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] Symbol of the 4th Pixel on the 2nd Line
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_cfa.field.sym13 = (d_tmp & m_tmp) | (reg_cfa.field.sym13 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserved.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_cfa.field.reserved = (d_tmp & m_tmp) | (reg_cfa.field.reserved & ~m_tmp);
			break;

		case 0x001C:
			// Lsb: 0, Len: 16, [15:0] Horizontal starting point of capture window
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_capture_window_start.field.hstart = (d_tmp & m_tmp) | (reg_capture_window_start.field.hstart & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical starting point of capture window
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_capture_window_start.field.vstart = (d_tmp & m_tmp) | (reg_capture_window_start.field.vstart & ~m_tmp);
			break;

		case 0x0020:
			// Lsb: 0, Len: 16, [15:0] Horizontal ending point of capture window
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_capture_window_end.field.hend = (d_tmp & m_tmp) | (reg_capture_window_end.field.hend & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical ending point of capture window
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_capture_window_end.field.vend = (d_tmp & m_tmp) | (reg_capture_window_end.field.vend & ~m_tmp);
			break;

		case 0x0024:
			// Lsb: 0, Len: 7, [6:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000007F;
			reg_dump_cfg_0.field.rsvd0 = (d_tmp & m_tmp) | (reg_dump_cfg_0.field.rsvd0 & ~m_tmp);

			// Lsb: 7, Len: 25, [31:7] base address for captured image 8x16 byte aligned
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x01FFFFFF;
			reg_dump_cfg_0.field.base_adr = (d_tmp & m_tmp) | (reg_dump_cfg_0.field.base_adr & ~m_tmp);
			break;

		case 0x0028:
			// Lsb: 0, Len: 7, [6:0] Reserved.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000007F;
			reg_dump_cfg_1.field.rsvd0 = (d_tmp & m_tmp) | (reg_dump_cfg_1.field.rsvd0 & ~m_tmp);

			// Lsb: 7, Len: 9, [15:7] Stride address for captured image 8x16 byte aligned.
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x000001FF;
			reg_dump_cfg_1.field.sd = (d_tmp & m_tmp) | (reg_dump_cfg_1.field.sd & ~m_tmp);

			// Lsb: 16, Len: 2, [17:16] AXI memory write burst length.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000003;
			reg_dump_cfg_1.field.burst_len = (d_tmp & m_tmp) | (reg_dump_cfg_1.field.burst_len & ~m_tmp);

			// Lsb: 18, Len: 2, [19:18] Reserved.
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000003;
			reg_dump_cfg_1.field.rsvd18 = (d_tmp & m_tmp) | (reg_dump_cfg_1.field.rsvd18 & ~m_tmp);

			// Lsb: 20, Len: 3, [22:20] Pixel right shift number.
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000007;
			reg_dump_cfg_1.field.sht = (d_tmp & m_tmp) | (reg_dump_cfg_1.field.sht & ~m_tmp);

			// Lsb: 23, Len: 1, [23] Reserved.
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x00000001;
			reg_dump_cfg_1.field.rsvd23 = (d_tmp & m_tmp) | (reg_dump_cfg_1.field.rsvd23 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] AXI memory write ID.
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_dump_cfg_1.field.id = (d_tmp & m_tmp) | (reg_dump_cfg_1.field.id & ~m_tmp);
			break;

		case 0x0030:
			// Lsb: 0, Len: 5, [4:0] Horizontal period(zero base)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_dec_cfg.field.hperiod = (d_tmp & m_tmp) | (reg_dec_cfg.field.hperiod & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_dec_cfg.field.rsvd5 = (d_tmp & m_tmp) | (reg_dec_cfg.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Horizontal keep(zero base)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_dec_cfg.field.hkeep = (d_tmp & m_tmp) | (reg_dec_cfg.field.hkeep & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_dec_cfg.field.rsvd13 = (d_tmp & m_tmp) | (reg_dec_cfg.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] Vertical period(zero base)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_dec_cfg.field.vperiod = (d_tmp & m_tmp) | (reg_dec_cfg.field.vperiod & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_dec_cfg.field.rsvd21 = (d_tmp & m_tmp) | (reg_dec_cfg.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] Vertical keep(zero base)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_dec_cfg.field.vkeep = (d_tmp & m_tmp) | (reg_dec_cfg.field.vkeep & ~m_tmp);
			break;

		case 0x0034:
			// Lsb: 0, Len: 4, [3:0] OBC window width
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_obc_cfg.field.width = (d_tmp & m_tmp) | (reg_obc_cfg.field.width & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] OBC window height
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_obc_cfg.field.height = (d_tmp & m_tmp) | (reg_obc_cfg.field.height & ~m_tmp);
			break;

		case 0x0040:
			// Lsb: 0, Len: 3, [2:0] vpos[13:0]/mode[1:0]/hpos[13:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_dc_cfg_0.field.rsvd0 = (d_tmp & m_tmp) | (reg_dc_cfg_0.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] DC axi base address (8 byte aligned)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_dc_cfg_0.field.base_adr = (d_tmp & m_tmp) | (reg_dc_cfg_0.field.base_adr & ~m_tmp);
			break;

		case 0x0044:
			// Lsb: 0, Len: 8, [7:0] AXI ID
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_dc_cfg_1.field.axi_id = (d_tmp & m_tmp) | (reg_dc_cfg_1.field.axi_id & ~m_tmp);
			break;

		case 0x0050:
			// Lsb: 0, Len: 15, [14:0] X distance from capture window
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00007FFF;
			reg_lccf_cfg_0.field.xd = (d_tmp & m_tmp) | (reg_lccf_cfg_0.field.xd & ~m_tmp);

			// Lsb: 15, Len: 1, [15] 
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_lccf_cfg_0.field.rsvd15 = (d_tmp & m_tmp) | (reg_lccf_cfg_0.field.rsvd15 & ~m_tmp);

			// Lsb: 16, Len: 15, [30:16] Y distance from capture window
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00007FFF;
			reg_lccf_cfg_0.field.yd = (d_tmp & m_tmp) | (reg_lccf_cfg_0.field.yd & ~m_tmp);
			break;

		case 0x0058:
			// Lsb: 0, Len: 4, [3:0] Parameter for typical maximum distance (dM = 2^M), 4bits
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_lccf_cfg_1.field.m = (d_tmp & m_tmp) | (reg_lccf_cfg_1.field.m & ~m_tmp);
			break;

		case 0x0074:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_lcbq_cfg_0.field.rsvd0 = (d_tmp & m_tmp) | (reg_lcbq_cfg_0.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] LCBQ Width of pseudo sub-window (2^WIDTH)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_lcbq_cfg_0.field.width = (d_tmp & m_tmp) | (reg_lcbq_cfg_0.field.width & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] LCBQ Height of pseudo sub-window (2^HEIGHT)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_lcbq_cfg_0.field.height = (d_tmp & m_tmp) | (reg_lcbq_cfg_0.field.height & ~m_tmp);
			break;

		case 0x007C:
			// Lsb: 0, Len: 12, [11:0] X coordinate
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_lcbq_cfg_1.field.x = (d_tmp & m_tmp) | (reg_lcbq_cfg_1.field.x & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_lcbq_cfg_1.field.rsvd12 = (d_tmp & m_tmp) | (reg_lcbq_cfg_1.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Y coordinate
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_lcbq_cfg_1.field.y = (d_tmp & m_tmp) | (reg_lcbq_cfg_1.field.y & ~m_tmp);
			break;

		case 0x0090:
			// Lsb: 0, Len: 16, [15:0] Horizontal starting point
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oba_cfg_0.field.hstart = (d_tmp & m_tmp) | (reg_oba_cfg_0.field.hstart & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical starting point
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oba_cfg_0.field.vstart = (d_tmp & m_tmp) | (reg_oba_cfg_0.field.vstart & ~m_tmp);
			break;

		case 0x0094:
			// Lsb: 0, Len: 16, [15:0] Horizontal ending point
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oba_cfg_1.field.hend = (d_tmp & m_tmp) | (reg_oba_cfg_1.field.hend & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical ending point
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oba_cfg_1.field.vend = (d_tmp & m_tmp) | (reg_oba_cfg_1.field.vend & ~m_tmp);
			break;

		case 0x0098:
			// Lsb: 0, Len: 7, [6:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000007F;
			reg_scd_cfg_0.field.rsvd0 = (d_tmp & m_tmp) | (reg_scd_cfg_0.field.rsvd0 & ~m_tmp);

			// Lsb: 7, Len: 25, [31:7] SC dumping base address(8x16byte align), need use AWB WB frame_start generate interrupt & sync address
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x01FFFFFF;
			reg_scd_cfg_0.field.base_adr = (d_tmp & m_tmp) | (reg_scd_cfg_0.field.base_adr & ~m_tmp);
			break;

		case 0x009C:
			// Lsb: 0, Len: 24, [23:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00FFFFFF;
			reg_scd_cfg_1.field.rsvd0 = (d_tmp & m_tmp) | (reg_scd_cfg_1.field.rsvd0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] AXI ID
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_scd_cfg_1.field.axi_id = (d_tmp & m_tmp) | (reg_scd_cfg_1.field.axi_id & ~m_tmp);
			break;

		case 0x00A0:
			// Lsb: 0, Len: 32, [31:0] oba symbol 0 return acc(read only)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_oba_acc_0.field.acc0 = (d_tmp & m_tmp) | (reg_oba_acc_0.field.acc0 & ~m_tmp);
			break;

		case 0x00A4:
			// Lsb: 0, Len: 32, [31:0] oba symbol 1 return acc(read only)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_oba_acc_1.field.acc1 = (d_tmp & m_tmp) | (reg_oba_acc_1.field.acc1 & ~m_tmp);
			break;

		case 0x00A8:
			// Lsb: 0, Len: 32, [31:0] oba symbol 2 return acc(read only)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_oba_acc_2.field.acc2 = (d_tmp & m_tmp) | (reg_oba_acc_2.field.acc2 & ~m_tmp);
			break;

		case 0x00AC:
			// Lsb: 0, Len: 32, [31:0] oba symbol 3 return acc(read only)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_oba_acc_3.field.acc3 = (d_tmp & m_tmp) | (reg_oba_acc_3.field.acc3 & ~m_tmp);
			break;

		case 0x00B8:
			// Lsb: 0, Len: 16, [15:0] Horizontal starting point for frame cropping
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_sc_cfg_0.field.hstart = (d_tmp & m_tmp) | (reg_sc_cfg_0.field.hstart & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical starting point for frame cropping
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_sc_cfg_0.field.vstart = (d_tmp & m_tmp) | (reg_sc_cfg_0.field.vstart & ~m_tmp);
			break;

		case 0x00BC:
			// Lsb: 0, Len: 5, [4:0] Width of SC sub-window(SC_WIDTH+1)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_sc_cfg_1.field.width = (d_tmp & m_tmp) | (reg_sc_cfg_1.field.width & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_sc_cfg_1.field.rsvd5 = (d_tmp & m_tmp) | (reg_sc_cfg_1.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Height of SC sub-window(SC_HEIGHT+1)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_sc_cfg_1.field.height = (d_tmp & m_tmp) | (reg_sc_cfg_1.field.height & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_sc_cfg_1.field.rsvd13 = (d_tmp & m_tmp) | (reg_sc_cfg_1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.4.4] awb b/a value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_cfg_1.field.awb_ps_grb_ba = (d_tmp & m_tmp) | (reg_sc_cfg_1.field.awb_ps_grb_ba & ~m_tmp);

			// Lsb: 24, Len: 6, [29:24] 
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000003F;
			reg_sc_cfg_1.field.rsvd24 = (d_tmp & m_tmp) | (reg_sc_cfg_1.field.rsvd24 & ~m_tmp);

			// Lsb: 30, Len: 2, [31:30] sc0 input mux for sc awb
			d_tmp = (data >> 30); m_tmp = (mask >> 30) & 0x00000003;
			reg_sc_cfg_1.field.sel = (d_tmp & m_tmp) | (reg_sc_cfg_1.field.sel & ~m_tmp);
			break;

		case 0x00C0:
			// Lsb: 0, Len: 1, [0] Horizontal mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_sc_af.field.af_es_hm = (d_tmp & m_tmp) | (reg_sc_af.field.af_es_hm & ~m_tmp);

			// Lsb: 1, Len: 1, [1] 0:Absolute sum, 1:Squared sum
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_sc_af.field.af_es_sm = (d_tmp & m_tmp) | (reg_sc_af.field.af_es_sm & ~m_tmp);

			// Lsb: 2, Len: 1, [2] Horizontal enable
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_sc_af.field.af_es_he = (d_tmp & m_tmp) | (reg_sc_af.field.af_es_he & ~m_tmp);

			// Lsb: 3, Len: 1, [3] Vertical enable
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_sc_af.field.af_es_ve = (d_tmp & m_tmp) | (reg_sc_af.field.af_es_ve & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] 
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_af.field.rsvd4 = (d_tmp & m_tmp) | (reg_sc_af.field.rsvd4 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] Vertical threshold
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_af.field.af_es_vthr = (d_tmp & m_tmp) | (reg_sc_af.field.af_es_vthr & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] Horizontal threshold
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_sc_af.field.af_es_hthr = (d_tmp & m_tmp) | (reg_sc_af.field.af_es_hthr & ~m_tmp);
			break;

		case 0x00C4:
			// Lsb: 0, Len: 8, [7:0] [0.8.0]Lower boundary of R value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ps_cfg_0.field.awb_ps_rl = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_0.field.awb_ps_rl & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0]Upper boundary of R value
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ps_cfg_0.field.awb_ps_ru = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_0.field.awb_ps_ru & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0]Lower boundary of G value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ps_cfg_0.field.awb_ps_gl = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_0.field.awb_ps_gl & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0]Upper boundary of G value
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ps_cfg_0.field.awb_ps_gu = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_0.field.awb_ps_gu & ~m_tmp);
			break;

		case 0x00C8:
			// Lsb: 0, Len: 8, [7:0] [0.8.0]Lower boundary of B value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ps_cfg_1.field.awb_ps_bl = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_1.field.awb_ps_bl & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0]Upper boundary of B value
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ps_cfg_1.field.awb_ps_bu = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_1.field.awb_ps_bu & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0]Lower boundary of Y value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ps_cfg_1.field.awb_ps_yl = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_1.field.awb_ps_yl & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0]Upper boundary of Y value
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ps_cfg_1.field.awb_ps_yu = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_1.field.awb_ps_yu & ~m_tmp);
			break;

		case 0x00CC:
			// Lsb: 0, Len: 16, [15:0] [0.8.8]Lower boundary of G/R ratio
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_sc_awb_ps_cfg_2.field.awb_ps_grl = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_2.field.awb_ps_grl & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] [0.8.8]Upper boundary of G/R ratio
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_sc_awb_ps_cfg_2.field.awb_ps_gru = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_2.field.awb_ps_gru & ~m_tmp);
			break;

		case 0x00D0:
			// Lsb: 0, Len: 16, [15:0] [0.8.8]Lower boundary of G/B ratio
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_sc_awb_ps_cfg_3.field.awb_ps_gbl = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_3.field.awb_ps_gbl & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] [0.8.8]Upper boundary of G/B ratio
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_sc_awb_ps_cfg_3.field.awb_ps_gbu = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_3.field.awb_ps_gbu & ~m_tmp);
			break;

		case 0x00D4:
			// Lsb: 0, Len: 16, [15:0] [0.8.8]Lower boundary of (Gr/R + b/a * Gb/B)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_sc_awb_ps_cfg_4.field.awb_ps_grbl = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_4.field.awb_ps_grbl & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] [0.8.8]Upper boundary of (Gr/R + b/a * Gb/B)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_sc_awb_ps_cfg_4.field.awb_ps_grbu = (d_tmp & m_tmp) | (reg_sc_awb_ps_cfg_4.field.awb_ps_grbu & ~m_tmp);
			break;

		case 0x00D8:
			// Lsb: 0, Len: 5, [4:0] Horizontal period(zero base)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_sc_dec.field.hperiod = (d_tmp & m_tmp) | (reg_sc_dec.field.hperiod & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_sc_dec.field.rsvd5 = (d_tmp & m_tmp) | (reg_sc_dec.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Horizontal keep(zero base)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_sc_dec.field.hkeep = (d_tmp & m_tmp) | (reg_sc_dec.field.hkeep & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_sc_dec.field.rsvd13 = (d_tmp & m_tmp) | (reg_sc_dec.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] Vertical period(zero base)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_sc_dec.field.vperiod = (d_tmp & m_tmp) | (reg_sc_dec.field.vperiod & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_sc_dec.field.rsvd21 = (d_tmp & m_tmp) | (reg_sc_dec.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] Vertical keep(zero base)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_sc_dec.field.vkeep = (d_tmp & m_tmp) | (reg_sc_dec.field.vkeep & ~m_tmp);
			break;

		case 0x00E0:
			// Lsb: 0, Len: 13, [12:0] [0.3.10]F1 parameter for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_lccf_cfg_2.field.f1_s0 = (d_tmp & m_tmp) | (reg_lccf_cfg_2.field.f1_s0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_lccf_cfg_2.field.rsvd13 = (d_tmp & m_tmp) | (reg_lccf_cfg_2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] [0.2.10]F2 parameter for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_lccf_cfg_2.field.f2_s0 = (d_tmp & m_tmp) | (reg_lccf_cfg_2.field.f2_s0 & ~m_tmp);
			break;

		case 0x00E4:
			// Lsb: 0, Len: 13, [12:0] [0.3.10]F1 parameter for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_lccf_cfg_3.field.f1_s1 = (d_tmp & m_tmp) | (reg_lccf_cfg_3.field.f1_s1 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_lccf_cfg_3.field.rsvd13 = (d_tmp & m_tmp) | (reg_lccf_cfg_3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] [0.2.10]F2 parameter for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_lccf_cfg_3.field.f2_s1 = (d_tmp & m_tmp) | (reg_lccf_cfg_3.field.f2_s1 & ~m_tmp);
			break;

		case 0x00E8:
			// Lsb: 0, Len: 13, [12:0] [0.3.10]F1 parameter for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_lccf_cfg_4.field.f1_s2 = (d_tmp & m_tmp) | (reg_lccf_cfg_4.field.f1_s2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_lccf_cfg_4.field.rsvd13 = (d_tmp & m_tmp) | (reg_lccf_cfg_4.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] [0.2.10]F2 parameter for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_lccf_cfg_4.field.f2_s2 = (d_tmp & m_tmp) | (reg_lccf_cfg_4.field.f2_s2 & ~m_tmp);
			break;

		case 0x00EC:
			// Lsb: 0, Len: 13, [12:0] [0.3.10]F1 parameter for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_lccf_cfg_5.field.f1_s3 = (d_tmp & m_tmp) | (reg_lccf_cfg_5.field.f1_s3 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_lccf_cfg_5.field.rsvd13 = (d_tmp & m_tmp) | (reg_lccf_cfg_5.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] [0.2.10]F2 parameter for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_lccf_cfg_5.field.f2_s3 = (d_tmp & m_tmp) | (reg_lccf_cfg_5.field.f2_s3 & ~m_tmp);
			break;

		case 0x00F8:
			// Lsb: 0, Len: 8, [7:0] Select SC data.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_scr_adr.field.adr = (d_tmp & m_tmp) | (reg_scr_adr.field.adr & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] 
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_scr_adr.field.rsvd8 = (d_tmp & m_tmp) | (reg_scr_adr.field.rsvd8 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] Select SC method.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_scr_adr.field.idx = (d_tmp & m_tmp) | (reg_scr_adr.field.idx & ~m_tmp);
			break;

		case 0x00FC:
			// Lsb: 0, Len: 32, [31:0] SC data readout.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_scr_dat.field.dat = (d_tmp & m_tmp) | (reg_scr_dat.field.dat & ~m_tmp);
			break;

		case 0x0100:
			// Lsb: 0, Len: 10, [9:0] X0 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_0.field.x0_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_0.field.x0_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_0.field.x1_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_0.field.x1_s0 & ~m_tmp);
			break;

		case 0x0104:
			// Lsb: 0, Len: 10, [9:0] X2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_1.field.x2_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_1.field.x2_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_1.field.x3_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_1.field.x3_s0 & ~m_tmp);
			break;

		case 0x0108:
			// Lsb: 0, Len: 10, [9:0] X4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_2.field.x4_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_2.field.x4_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_2.field.x5_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_2.field.x5_s0 & ~m_tmp);
			break;

		case 0x010C:
			// Lsb: 0, Len: 10, [9:0] X6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_3.field.x6_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_3.field.x6_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_3.field.x7_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_3.field.x7_s0 & ~m_tmp);
			break;

		case 0x0110:
			// Lsb: 0, Len: 10, [9:0] X8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_4.field.x8_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_4.field.x8_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_4.field.x9_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_4.field.x9_s0 & ~m_tmp);
			break;

		case 0x0114:
			// Lsb: 0, Len: 10, [9:0] X10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_5.field.x10_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_5.field.x10_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_5.field.x11_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_5.field.x11_s0 & ~m_tmp);
			break;

		case 0x0118:
			// Lsb: 0, Len: 10, [9:0] X12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_6.field.x12_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_6.field.x12_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_6.field.x13_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_6.field.x13_s0 & ~m_tmp);
			break;

		case 0x011C:
			// Lsb: 0, Len: 10, [9:0] X14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x0_cfg_7.field.x14_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_7.field.x14_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x0_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x0_cfg_7.field.x15_s0 = (d_tmp & m_tmp) | (reg_oecf_x0_cfg_7.field.x15_s0 & ~m_tmp);
			break;

		case 0x0120:
			// Lsb: 0, Len: 10, [9:0] X0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_0.field.x0_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_0.field.x0_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_0.field.x1_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_0.field.x1_s1 & ~m_tmp);
			break;

		case 0x0124:
			// Lsb: 0, Len: 10, [9:0] X2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_1.field.x2_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_1.field.x2_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_1.field.x3_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_1.field.x3_s1 & ~m_tmp);
			break;

		case 0x0128:
			// Lsb: 0, Len: 10, [9:0] X4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_2.field.x4_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_2.field.x4_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_2.field.x5_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_2.field.x5_s1 & ~m_tmp);
			break;

		case 0x012C:
			// Lsb: 0, Len: 10, [9:0] X6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_3.field.x6_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_3.field.x6_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_3.field.x7_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_3.field.x7_s1 & ~m_tmp);
			break;

		case 0x0130:
			// Lsb: 0, Len: 10, [9:0] X8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_4.field.x8_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_4.field.x8_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_4.field.x9_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_4.field.x9_s1 & ~m_tmp);
			break;

		case 0x0134:
			// Lsb: 0, Len: 10, [9:0] X10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_5.field.x10_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_5.field.x10_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_5.field.x11_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_5.field.x11_s1 & ~m_tmp);
			break;

		case 0x0138:
			// Lsb: 0, Len: 10, [9:0] X12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_6.field.x12_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_6.field.x12_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_6.field.x13_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_6.field.x13_s1 & ~m_tmp);
			break;

		case 0x013C:
			// Lsb: 0, Len: 10, [9:0] X14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x1_cfg_7.field.x14_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_7.field.x14_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x1_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x1_cfg_7.field.x15_s1 = (d_tmp & m_tmp) | (reg_oecf_x1_cfg_7.field.x15_s1 & ~m_tmp);
			break;

		case 0x0140:
			// Lsb: 0, Len: 10, [9:0] X0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_0.field.x0_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_0.field.x0_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_0.field.x1_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_0.field.x1_s2 & ~m_tmp);
			break;

		case 0x0144:
			// Lsb: 0, Len: 10, [9:0] X2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_1.field.x2_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_1.field.x2_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_1.field.x3_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_1.field.x3_s2 & ~m_tmp);
			break;

		case 0x0148:
			// Lsb: 0, Len: 10, [9:0] X4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_2.field.x4_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_2.field.x4_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_2.field.x5_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_2.field.x5_s2 & ~m_tmp);
			break;

		case 0x014C:
			// Lsb: 0, Len: 10, [9:0] X6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_3.field.x6_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_3.field.x6_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_3.field.x7_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_3.field.x7_s2 & ~m_tmp);
			break;

		case 0x0150:
			// Lsb: 0, Len: 10, [9:0] X8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_4.field.x8_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_4.field.x8_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_4.field.x9_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_4.field.x9_s2 & ~m_tmp);
			break;

		case 0x0154:
			// Lsb: 0, Len: 10, [9:0] X10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_5.field.x10_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_5.field.x10_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_5.field.x11_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_5.field.x11_s2 & ~m_tmp);
			break;

		case 0x0158:
			// Lsb: 0, Len: 10, [9:0] X12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_6.field.x12_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_6.field.x12_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_6.field.x13_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_6.field.x13_s2 & ~m_tmp);
			break;

		case 0x015C:
			// Lsb: 0, Len: 10, [9:0] X14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x2_cfg_7.field.x14_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_7.field.x14_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x2_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x2_cfg_7.field.x15_s2 = (d_tmp & m_tmp) | (reg_oecf_x2_cfg_7.field.x15_s2 & ~m_tmp);
			break;

		case 0x0160:
			// Lsb: 0, Len: 10, [9:0] X0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_0.field.x0_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_0.field.x0_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_0.field.x1_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_0.field.x1_s3 & ~m_tmp);
			break;

		case 0x0164:
			// Lsb: 0, Len: 10, [9:0] X2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_1.field.x2_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_1.field.x2_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_1.field.x3_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_1.field.x3_s3 & ~m_tmp);
			break;

		case 0x0168:
			// Lsb: 0, Len: 10, [9:0] X4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_2.field.x4_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_2.field.x4_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_2.field.x5_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_2.field.x5_s3 & ~m_tmp);
			break;

		case 0x016C:
			// Lsb: 0, Len: 10, [9:0] X6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_3.field.x6_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_3.field.x6_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_3.field.x7_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_3.field.x7_s3 & ~m_tmp);
			break;

		case 0x0170:
			// Lsb: 0, Len: 10, [9:0] X8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_4.field.x8_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_4.field.x8_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_4.field.x9_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_4.field.x9_s3 & ~m_tmp);
			break;

		case 0x0174:
			// Lsb: 0, Len: 10, [9:0] X10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_5.field.x10_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_5.field.x10_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_5.field.x11_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_5.field.x11_s3 & ~m_tmp);
			break;

		case 0x0178:
			// Lsb: 0, Len: 10, [9:0] X12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_6.field.x12_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_6.field.x12_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_6.field.x13_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_6.field.x13_s3 & ~m_tmp);
			break;

		case 0x017C:
			// Lsb: 0, Len: 10, [9:0] X14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_x3_cfg_7.field.x14_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_7.field.x14_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_x3_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] X15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_x3_cfg_7.field.x15_s3 = (d_tmp & m_tmp) | (reg_oecf_x3_cfg_7.field.x15_s3 & ~m_tmp);
			break;

		case 0x0180:
			// Lsb: 0, Len: 10, [9:0] Y0 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_0.field.y0_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_0.field.y0_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_0.field.y1_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_0.field.y1_s0 & ~m_tmp);
			break;

		case 0x0184:
			// Lsb: 0, Len: 10, [9:0] Y2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_1.field.y2_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_1.field.y2_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_1.field.y3_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_1.field.y3_s0 & ~m_tmp);
			break;

		case 0x0188:
			// Lsb: 0, Len: 10, [9:0] Y4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_2.field.y4_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_2.field.y4_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_2.field.y5_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_2.field.y5_s0 & ~m_tmp);
			break;

		case 0x018C:
			// Lsb: 0, Len: 10, [9:0] Y6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_3.field.y6_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_3.field.y6_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_3.field.y7_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_3.field.y7_s0 & ~m_tmp);
			break;

		case 0x0190:
			// Lsb: 0, Len: 10, [9:0] Y8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_4.field.y8_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_4.field.y8_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_4.field.y9_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_4.field.y9_s0 & ~m_tmp);
			break;

		case 0x0194:
			// Lsb: 0, Len: 10, [9:0] Y10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_5.field.y10_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_5.field.y10_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_5.field.y11_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_5.field.y11_s0 & ~m_tmp);
			break;

		case 0x0198:
			// Lsb: 0, Len: 10, [9:0] Y12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_6.field.y12_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_6.field.y12_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_6.field.y13_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_6.field.y13_s0 & ~m_tmp);
			break;

		case 0x019C:
			// Lsb: 0, Len: 10, [9:0] Y14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y0_cfg_7.field.y14_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_7.field.y14_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y0_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y0_cfg_7.field.y15_s0 = (d_tmp & m_tmp) | (reg_oecf_y0_cfg_7.field.y15_s0 & ~m_tmp);
			break;

		case 0x01A0:
			// Lsb: 0, Len: 10, [9:0] Y0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_0.field.y0_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_0.field.y0_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_0.field.y1_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_0.field.y1_s1 & ~m_tmp);
			break;

		case 0x01A4:
			// Lsb: 0, Len: 10, [9:0] Y2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_1.field.y2_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_1.field.y2_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_1.field.y3_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_1.field.y3_s1 & ~m_tmp);
			break;

		case 0x01A8:
			// Lsb: 0, Len: 10, [9:0] Y4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_2.field.y4_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_2.field.y4_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_2.field.y5_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_2.field.y5_s1 & ~m_tmp);
			break;

		case 0x01AC:
			// Lsb: 0, Len: 10, [9:0] Y6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_3.field.y6_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_3.field.y6_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_3.field.y7_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_3.field.y7_s1 & ~m_tmp);
			break;

		case 0x01B0:
			// Lsb: 0, Len: 10, [9:0] Y8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_4.field.y8_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_4.field.y8_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_4.field.y9_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_4.field.y9_s1 & ~m_tmp);
			break;

		case 0x01B4:
			// Lsb: 0, Len: 10, [9:0] Y10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_5.field.y10_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_5.field.y10_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_5.field.y11_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_5.field.y11_s1 & ~m_tmp);
			break;

		case 0x01B8:
			// Lsb: 0, Len: 10, [9:0] Y12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_6.field.y12_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_6.field.y12_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_6.field.y13_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_6.field.y13_s1 & ~m_tmp);
			break;

		case 0x01BC:
			// Lsb: 0, Len: 10, [9:0] Y14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y1_cfg_7.field.y14_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_7.field.y14_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y1_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y1_cfg_7.field.y15_s1 = (d_tmp & m_tmp) | (reg_oecf_y1_cfg_7.field.y15_s1 & ~m_tmp);
			break;

		case 0x01C0:
			// Lsb: 0, Len: 10, [9:0] Y0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_0.field.y0_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_0.field.y0_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_0.field.y1_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_0.field.y1_s2 & ~m_tmp);
			break;

		case 0x01C4:
			// Lsb: 0, Len: 10, [9:0] Y2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_1.field.y2_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_1.field.y2_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_1.field.y3_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_1.field.y3_s2 & ~m_tmp);
			break;

		case 0x01C8:
			// Lsb: 0, Len: 10, [9:0] Y4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_2.field.y4_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_2.field.y4_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_2.field.y5_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_2.field.y5_s2 & ~m_tmp);
			break;

		case 0x01CC:
			// Lsb: 0, Len: 10, [9:0] Y6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_3.field.y6_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_3.field.y6_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_3.field.y7_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_3.field.y7_s2 & ~m_tmp);
			break;

		case 0x01D0:
			// Lsb: 0, Len: 10, [9:0] Y8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_4.field.y8_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_4.field.y8_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_4.field.y9_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_4.field.y9_s2 & ~m_tmp);
			break;

		case 0x01D4:
			// Lsb: 0, Len: 10, [9:0] Y10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_5.field.y10_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_5.field.y10_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_5.field.y11_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_5.field.y11_s2 & ~m_tmp);
			break;

		case 0x01D8:
			// Lsb: 0, Len: 10, [9:0] Y12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_6.field.y12_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_6.field.y12_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_6.field.y13_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_6.field.y13_s2 & ~m_tmp);
			break;

		case 0x01DC:
			// Lsb: 0, Len: 10, [9:0] Y14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y2_cfg_7.field.y14_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_7.field.y14_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y2_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y2_cfg_7.field.y15_s2 = (d_tmp & m_tmp) | (reg_oecf_y2_cfg_7.field.y15_s2 & ~m_tmp);
			break;

		case 0x01E0:
			// Lsb: 0, Len: 10, [9:0] Y0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_0.field.y0_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_0.field.y0_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_0.field.y1_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_0.field.y1_s3 & ~m_tmp);
			break;

		case 0x01E4:
			// Lsb: 0, Len: 10, [9:0] Y2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_1.field.y2_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_1.field.y2_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_1.field.y3_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_1.field.y3_s3 & ~m_tmp);
			break;

		case 0x01E8:
			// Lsb: 0, Len: 10, [9:0] Y4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_2.field.y4_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_2.field.y4_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_2.field.y5_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_2.field.y5_s3 & ~m_tmp);
			break;

		case 0x01EC:
			// Lsb: 0, Len: 10, [9:0] Y6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_3.field.y6_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_3.field.y6_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_3.field.y7_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_3.field.y7_s3 & ~m_tmp);
			break;

		case 0x01F0:
			// Lsb: 0, Len: 10, [9:0] Y8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_4.field.y8_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_4.field.y8_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_4.field.y9_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_4.field.y9_s3 & ~m_tmp);
			break;

		case 0x01F4:
			// Lsb: 0, Len: 10, [9:0] Y10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_5.field.y10_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_5.field.y10_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_5.field.y11_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_5.field.y11_s3 & ~m_tmp);
			break;

		case 0x01F8:
			// Lsb: 0, Len: 10, [9:0] Y12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_6.field.y12_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_6.field.y12_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_6.field.y13_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_6.field.y13_s3 & ~m_tmp);
			break;

		case 0x01FC:
			// Lsb: 0, Len: 10, [9:0] Y14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_y3_cfg_7.field.y14_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_7.field.y14_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_y3_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_y3_cfg_7.field.y15_s3 = (d_tmp & m_tmp) | (reg_oecf_y3_cfg_7.field.y15_s3 & ~m_tmp);
			break;

		case 0x0200:
			// Lsb: 0, Len: 10, [9:0] S0 for symbol 0 [0.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_0.field.s0_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_0.field.s0_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_0.field.s1_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_0.field.s1_s0 & ~m_tmp);
			break;

		case 0x0204:
			// Lsb: 0, Len: 10, [9:0] S2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_1.field.s2_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_1.field.s2_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_1.field.s3_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_1.field.s3_s0 & ~m_tmp);
			break;

		case 0x0208:
			// Lsb: 0, Len: 10, [9:0] S4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_2.field.s4_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_2.field.s4_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_2.field.s5_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_2.field.s5_s0 & ~m_tmp);
			break;

		case 0x020C:
			// Lsb: 0, Len: 10, [9:0] S6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_3.field.s6_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_3.field.s6_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_3.field.s7_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_3.field.s7_s0 & ~m_tmp);
			break;

		case 0x0210:
			// Lsb: 0, Len: 10, [9:0] S8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_4.field.s8_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_4.field.s8_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_4.field.s9_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_4.field.s9_s0 & ~m_tmp);
			break;

		case 0x0214:
			// Lsb: 0, Len: 10, [9:0] S10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_5.field.s10_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_5.field.s10_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_5.field.s11_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_5.field.s11_s0 & ~m_tmp);
			break;

		case 0x0218:
			// Lsb: 0, Len: 10, [9:0] S12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_6.field.s12_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_6.field.s12_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_6.field.s13_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_6.field.s13_s0 & ~m_tmp);
			break;

		case 0x021C:
			// Lsb: 0, Len: 10, [9:0] S14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s0_cfg_7.field.s14_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_7.field.s14_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s0_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s0_cfg_7.field.s15_s0 = (d_tmp & m_tmp) | (reg_oecf_s0_cfg_7.field.s15_s0 & ~m_tmp);
			break;

		case 0x0220:
			// Lsb: 0, Len: 10, [9:0] S0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_0.field.s0_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_0.field.s0_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_0.field.s1_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_0.field.s1_s1 & ~m_tmp);
			break;

		case 0x0224:
			// Lsb: 0, Len: 10, [9:0] S2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_1.field.s2_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_1.field.s2_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_1.field.s3_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_1.field.s3_s1 & ~m_tmp);
			break;

		case 0x0228:
			// Lsb: 0, Len: 10, [9:0] S4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_2.field.s4_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_2.field.s4_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_2.field.s5_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_2.field.s5_s1 & ~m_tmp);
			break;

		case 0x022C:
			// Lsb: 0, Len: 10, [9:0] S6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_3.field.s6_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_3.field.s6_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_3.field.s7_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_3.field.s7_s1 & ~m_tmp);
			break;

		case 0x0230:
			// Lsb: 0, Len: 10, [9:0] S8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_4.field.s8_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_4.field.s8_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_4.field.s9_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_4.field.s9_s1 & ~m_tmp);
			break;

		case 0x0234:
			// Lsb: 0, Len: 10, [9:0] S10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_5.field.s10_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_5.field.s10_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_5.field.s11_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_5.field.s11_s1 & ~m_tmp);
			break;

		case 0x0238:
			// Lsb: 0, Len: 10, [9:0] S12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_6.field.s12_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_6.field.s12_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_6.field.s13_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_6.field.s13_s1 & ~m_tmp);
			break;

		case 0x023C:
			// Lsb: 0, Len: 10, [9:0] S14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s1_cfg_7.field.s14_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_7.field.s14_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s1_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s1_cfg_7.field.s15_s1 = (d_tmp & m_tmp) | (reg_oecf_s1_cfg_7.field.s15_s1 & ~m_tmp);
			break;

		case 0x0240:
			// Lsb: 0, Len: 10, [9:0] S0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_0.field.s0_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_0.field.s0_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_0.field.s1_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_0.field.s1_s2 & ~m_tmp);
			break;

		case 0x0244:
			// Lsb: 0, Len: 10, [9:0] S2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_1.field.s2_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_1.field.s2_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_1.field.s3_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_1.field.s3_s2 & ~m_tmp);
			break;

		case 0x0248:
			// Lsb: 0, Len: 10, [9:0] S4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_2.field.s4_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_2.field.s4_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_2.field.s5_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_2.field.s5_s2 & ~m_tmp);
			break;

		case 0x024C:
			// Lsb: 0, Len: 10, [9:0] S6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_3.field.s6_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_3.field.s6_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_3.field.s7_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_3.field.s7_s2 & ~m_tmp);
			break;

		case 0x0250:
			// Lsb: 0, Len: 10, [9:0] S8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_4.field.s8_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_4.field.s8_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_4.field.s9_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_4.field.s9_s2 & ~m_tmp);
			break;

		case 0x0254:
			// Lsb: 0, Len: 10, [9:0] S10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_5.field.s10_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_5.field.s10_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_5.field.s11_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_5.field.s11_s2 & ~m_tmp);
			break;

		case 0x0258:
			// Lsb: 0, Len: 10, [9:0] S12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_6.field.s12_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_6.field.s12_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_6.field.s13_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_6.field.s13_s2 & ~m_tmp);
			break;

		case 0x025C:
			// Lsb: 0, Len: 10, [9:0] S14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s2_cfg_7.field.s14_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_7.field.s14_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s2_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s2_cfg_7.field.s15_s2 = (d_tmp & m_tmp) | (reg_oecf_s2_cfg_7.field.s15_s2 & ~m_tmp);
			break;

		case 0x0260:
			// Lsb: 0, Len: 10, [9:0] S0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_0.field.s0_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_0.field.s0_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_0.field.s1_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_0.field.s1_s3 & ~m_tmp);
			break;

		case 0x0264:
			// Lsb: 0, Len: 10, [9:0] S2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_1.field.s2_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_1.field.s2_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_1.field.s3_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_1.field.s3_s3 & ~m_tmp);
			break;

		case 0x0268:
			// Lsb: 0, Len: 10, [9:0] S4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_2.field.s4_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_2.field.s4_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_2.field.s5_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_2.field.s5_s3 & ~m_tmp);
			break;

		case 0x026C:
			// Lsb: 0, Len: 10, [9:0] S6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_3.field.s6_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_3.field.s6_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_3.field.s7_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_3.field.s7_s3 & ~m_tmp);
			break;

		case 0x0270:
			// Lsb: 0, Len: 10, [9:0] S8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_4.field.s8_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_4.field.s8_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_4.field.s9_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_4.field.s9_s3 & ~m_tmp);
			break;

		case 0x0274:
			// Lsb: 0, Len: 10, [9:0] S10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_5.field.s10_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_5.field.s10_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_5.field.s11_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_5.field.s11_s3 & ~m_tmp);
			break;

		case 0x0278:
			// Lsb: 0, Len: 10, [9:0] S12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_6.field.s12_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_6.field.s12_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_6.field.s13_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_6.field.s13_s3 & ~m_tmp);
			break;

		case 0x027C:
			// Lsb: 0, Len: 10, [9:0] S14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_oecf_s3_cfg_7.field.s14_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_7.field.s14_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_oecf_s3_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] S15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_oecf_s3_cfg_7.field.s15_s3 = (d_tmp & m_tmp) | (reg_oecf_s3_cfg_7.field.s15_s3 & ~m_tmp);
			break;

		case 0x0280:
			// Lsb: 0, Len: 10, [9:0] symbol_0 X0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x0_cfg_0.field.x0_s0 = (d_tmp & m_tmp) | (reg_awb_x0_cfg_0.field.x0_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x0_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x0_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_0 X1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x0_cfg_0.field.x1_s0 = (d_tmp & m_tmp) | (reg_awb_x0_cfg_0.field.x1_s0 & ~m_tmp);
			break;

		case 0x0284:
			// Lsb: 0, Len: 10, [9:0] symbol_0 X2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x0_cfg_1.field.x2_s0 = (d_tmp & m_tmp) | (reg_awb_x0_cfg_1.field.x2_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x0_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x0_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_0 X3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x0_cfg_1.field.x3_s0 = (d_tmp & m_tmp) | (reg_awb_x0_cfg_1.field.x3_s0 & ~m_tmp);
			break;

		case 0x0288:
			// Lsb: 0, Len: 10, [9:0] symbol_1 X0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x1_cfg_0.field.x0_s1 = (d_tmp & m_tmp) | (reg_awb_x1_cfg_0.field.x0_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x1_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x1_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_1 X1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x1_cfg_0.field.x1_s1 = (d_tmp & m_tmp) | (reg_awb_x1_cfg_0.field.x1_s1 & ~m_tmp);
			break;

		case 0x028C:
			// Lsb: 0, Len: 10, [9:0] symbol_1 X2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x1_cfg_1.field.x2_s1 = (d_tmp & m_tmp) | (reg_awb_x1_cfg_1.field.x2_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x1_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x1_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_1 X3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x1_cfg_1.field.x3_s1 = (d_tmp & m_tmp) | (reg_awb_x1_cfg_1.field.x3_s1 & ~m_tmp);
			break;

		case 0x0290:
			// Lsb: 0, Len: 10, [9:0] symbol_2 X0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x2_cfg_0.field.x0_s2 = (d_tmp & m_tmp) | (reg_awb_x2_cfg_0.field.x0_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x2_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x2_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_2 X1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x2_cfg_0.field.x1_s2 = (d_tmp & m_tmp) | (reg_awb_x2_cfg_0.field.x1_s2 & ~m_tmp);
			break;

		case 0x0294:
			// Lsb: 0, Len: 10, [9:0] symbol_2 X2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x2_cfg_1.field.x2_s2 = (d_tmp & m_tmp) | (reg_awb_x2_cfg_1.field.x2_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x2_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x2_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_2 X3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x2_cfg_1.field.x3_s2 = (d_tmp & m_tmp) | (reg_awb_x2_cfg_1.field.x3_s2 & ~m_tmp);
			break;

		case 0x0298:
			// Lsb: 0, Len: 10, [9:0] symbol_3 X0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x3_cfg_0.field.x0_s3 = (d_tmp & m_tmp) | (reg_awb_x3_cfg_0.field.x0_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x3_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x3_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_3 X1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x3_cfg_0.field.x1_s3 = (d_tmp & m_tmp) | (reg_awb_x3_cfg_0.field.x1_s3 & ~m_tmp);
			break;

		case 0x029C:
			// Lsb: 0, Len: 10, [9:0] symbol_3 X2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_x3_cfg_1.field.x2_s3 = (d_tmp & m_tmp) | (reg_awb_x3_cfg_1.field.x2_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_x3_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_x3_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_3 X3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_x3_cfg_1.field.x3_s3 = (d_tmp & m_tmp) | (reg_awb_x3_cfg_1.field.x3_s3 & ~m_tmp);
			break;

		case 0x02A0:
			// Lsb: 0, Len: 10, [9:0] symbol_0 Y0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y0_cfg_0.field.y0_s0 = (d_tmp & m_tmp) | (reg_awb_y0_cfg_0.field.y0_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y0_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y0_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_0 Y1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y0_cfg_0.field.y1_s0 = (d_tmp & m_tmp) | (reg_awb_y0_cfg_0.field.y1_s0 & ~m_tmp);
			break;

		case 0x02A4:
			// Lsb: 0, Len: 10, [9:0] symbol_0 Y2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y0_cfg_1.field.y2_s0 = (d_tmp & m_tmp) | (reg_awb_y0_cfg_1.field.y2_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y0_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y0_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_0 Y3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y0_cfg_1.field.y3_s0 = (d_tmp & m_tmp) | (reg_awb_y0_cfg_1.field.y3_s0 & ~m_tmp);
			break;

		case 0x02A8:
			// Lsb: 0, Len: 10, [9:0] symbol_1 Y0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y1_cfg_0.field.y0_s1 = (d_tmp & m_tmp) | (reg_awb_y1_cfg_0.field.y0_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y1_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y1_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_1 Y1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y1_cfg_0.field.y1_s1 = (d_tmp & m_tmp) | (reg_awb_y1_cfg_0.field.y1_s1 & ~m_tmp);
			break;

		case 0x02AC:
			// Lsb: 0, Len: 10, [9:0] symbol_1 Y2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y1_cfg_1.field.y2_s1 = (d_tmp & m_tmp) | (reg_awb_y1_cfg_1.field.y2_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y1_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y1_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_1 Y3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y1_cfg_1.field.y3_s1 = (d_tmp & m_tmp) | (reg_awb_y1_cfg_1.field.y3_s1 & ~m_tmp);
			break;

		case 0x02B0:
			// Lsb: 0, Len: 10, [9:0] symbol_2 Y0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y2_cfg_0.field.y0_s2 = (d_tmp & m_tmp) | (reg_awb_y2_cfg_0.field.y0_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y2_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y2_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_2 Y1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y2_cfg_0.field.y1_s2 = (d_tmp & m_tmp) | (reg_awb_y2_cfg_0.field.y1_s2 & ~m_tmp);
			break;

		case 0x02B4:
			// Lsb: 0, Len: 10, [9:0] symbol_2 Y2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y2_cfg_1.field.y2_s2 = (d_tmp & m_tmp) | (reg_awb_y2_cfg_1.field.y2_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y2_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y2_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_2 Y3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y2_cfg_1.field.y3_s2 = (d_tmp & m_tmp) | (reg_awb_y2_cfg_1.field.y3_s2 & ~m_tmp);
			break;

		case 0x02B8:
			// Lsb: 0, Len: 10, [9:0] symbol_3 Y0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y3_cfg_0.field.y0_s3 = (d_tmp & m_tmp) | (reg_awb_y3_cfg_0.field.y0_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y3_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y3_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_3 Y1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y3_cfg_0.field.y1_s3 = (d_tmp & m_tmp) | (reg_awb_y3_cfg_0.field.y1_s3 & ~m_tmp);
			break;

		case 0x02BC:
			// Lsb: 0, Len: 10, [9:0] symbol_3 Y2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_y3_cfg_1.field.y2_s3 = (d_tmp & m_tmp) | (reg_awb_y3_cfg_1.field.y2_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_y3_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_y3_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_3 Y3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_y3_cfg_1.field.y3_s3 = (d_tmp & m_tmp) | (reg_awb_y3_cfg_1.field.y3_s3 & ~m_tmp);
			break;

		case 0x02C0:
			// Lsb: 0, Len: 10, [9:0] symbol_0 S0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s0_cfg_0.field.s0_s0 = (d_tmp & m_tmp) | (reg_awb_s0_cfg_0.field.s0_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s0_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s0_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_0 S1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s0_cfg_0.field.s1_s0 = (d_tmp & m_tmp) | (reg_awb_s0_cfg_0.field.s1_s0 & ~m_tmp);
			break;

		case 0x02C4:
			// Lsb: 0, Len: 10, [9:0] symbol_0 S2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s0_cfg_1.field.s2_s0 = (d_tmp & m_tmp) | (reg_awb_s0_cfg_1.field.s2_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s0_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s0_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_0 S3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s0_cfg_1.field.s3_s0 = (d_tmp & m_tmp) | (reg_awb_s0_cfg_1.field.s3_s0 & ~m_tmp);
			break;

		case 0x02C8:
			// Lsb: 0, Len: 10, [9:0] symbol_1 S0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s1_cfg_0.field.s0_s1 = (d_tmp & m_tmp) | (reg_awb_s1_cfg_0.field.s0_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s1_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s1_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_1 S1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s1_cfg_0.field.s1_s1 = (d_tmp & m_tmp) | (reg_awb_s1_cfg_0.field.s1_s1 & ~m_tmp);
			break;

		case 0x02CC:
			// Lsb: 0, Len: 10, [9:0] symbol_1 S2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s1_cfg_1.field.s2_s1 = (d_tmp & m_tmp) | (reg_awb_s1_cfg_1.field.s2_s1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s1_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s1_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_1 S3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s1_cfg_1.field.s3_s1 = (d_tmp & m_tmp) | (reg_awb_s1_cfg_1.field.s3_s1 & ~m_tmp);
			break;

		case 0x02D0:
			// Lsb: 0, Len: 10, [9:0] symbol_2 S0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s2_cfg_0.field.s0_s2 = (d_tmp & m_tmp) | (reg_awb_s2_cfg_0.field.s0_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s2_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s2_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_2 S1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s2_cfg_0.field.s1_s2 = (d_tmp & m_tmp) | (reg_awb_s2_cfg_0.field.s1_s2 & ~m_tmp);
			break;

		case 0x02D4:
			// Lsb: 0, Len: 10, [9:0] symbol_2 S2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s2_cfg_1.field.s2_s2 = (d_tmp & m_tmp) | (reg_awb_s2_cfg_1.field.s2_s2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s2_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s2_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_2 S3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s2_cfg_1.field.s3_s2 = (d_tmp & m_tmp) | (reg_awb_s2_cfg_1.field.s3_s2 & ~m_tmp);
			break;

		case 0x02D8:
			// Lsb: 0, Len: 10, [9:0] symbol_3 S0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s3_cfg_0.field.s0_s3 = (d_tmp & m_tmp) | (reg_awb_s3_cfg_0.field.s0_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s3_cfg_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s3_cfg_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_3 S1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s3_cfg_0.field.s1_s3 = (d_tmp & m_tmp) | (reg_awb_s3_cfg_0.field.s1_s3 & ~m_tmp);
			break;

		case 0x02DC:
			// Lsb: 0, Len: 10, [9:0] symbol_3 S2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_awb_s3_cfg_1.field.s2_s3 = (d_tmp & m_tmp) | (reg_awb_s3_cfg_1.field.s2_s3 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_awb_s3_cfg_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_awb_s3_cfg_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] symbol_3 S3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_awb_s3_cfg_1.field.s3_s3 = (d_tmp & m_tmp) | (reg_awb_s3_cfg_1.field.s3_s3 & ~m_tmp);
			break;

		case 0x02E0:
			// Lsb: 0, Len: 8, [7:0] [0.2.6]Gain at point A for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obcg_cfg_0.field.a_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_0.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.2.6]Gain at point B for symbol 0
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obcg_cfg_0.field.b_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_0.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.2.6]Gain at point C for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obcg_cfg_0.field.c_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_0.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.2.6]Gain at point D for symbol 0
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obcg_cfg_0.field.d_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_0.field.d_s0 & ~m_tmp);
			break;

		case 0x02E4:
			// Lsb: 0, Len: 8, [7:0] [0.2.6]Gain at point A for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obcg_cfg_1.field.a_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_1.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.2.6]Gain at point B for symbol 1
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obcg_cfg_1.field.b_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_1.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.2.6]Gain at point C for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obcg_cfg_1.field.c_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_1.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.2.6]Gain at point D for symbol 1
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obcg_cfg_1.field.d_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_1.field.d_s0 & ~m_tmp);
			break;

		case 0x02E8:
			// Lsb: 0, Len: 8, [7:0] [0.2.6]Gain at point A for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obcg_cfg_2.field.a_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_2.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.2.6]Gain at point B for symbol 2
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obcg_cfg_2.field.b_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_2.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.2.6]Gain at point C for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obcg_cfg_2.field.c_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_2.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.2.6]Gain at point D for symbol 2
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obcg_cfg_2.field.d_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_2.field.d_s0 & ~m_tmp);
			break;

		case 0x02EC:
			// Lsb: 0, Len: 8, [7:0] [0.2.6]Gain at point A for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obcg_cfg_3.field.a_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_3.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.2.6]Gain at point B for symbol 3
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obcg_cfg_3.field.b_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_3.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.2.6]Gain at point C for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obcg_cfg_3.field.c_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_3.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.2.6]Gain at point D for symbol 3
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obcg_cfg_3.field.d_s0 = (d_tmp & m_tmp) | (reg_obcg_cfg_3.field.d_s0 & ~m_tmp);
			break;

		case 0x02F0:
			// Lsb: 0, Len: 8, [7:0] [0.8.0] Offset at point A for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obco_cfg_0.field.a_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_0.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0] Offset at point B for symbol 0
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obco_cfg_0.field.b_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_0.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0] Offset at point C for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obco_cfg_0.field.c_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_0.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0] Offset at point D for symbol 0
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obco_cfg_0.field.d_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_0.field.d_s0 & ~m_tmp);
			break;

		case 0x02F4:
			// Lsb: 0, Len: 8, [7:0] [0.8.0] Offset at point A for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obco_cfg_1.field.a_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_1.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0] Offset at point B for symbol 1
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obco_cfg_1.field.b_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_1.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0] Offset at point C for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obco_cfg_1.field.c_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_1.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0] Offset at point D for symbol 1
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obco_cfg_1.field.d_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_1.field.d_s0 & ~m_tmp);
			break;

		case 0x02F8:
			// Lsb: 0, Len: 8, [7:0] [0.8.0] Offset at point A for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obco_cfg_2.field.a_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_2.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0] Offset at point B for symbol 2
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obco_cfg_2.field.b_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_2.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0] Offset at point C for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obco_cfg_2.field.c_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_2.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0] Offset at point D for symbol 2
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obco_cfg_2.field.d_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_2.field.d_s0 & ~m_tmp);
			break;

		case 0x02FC:
			// Lsb: 0, Len: 8, [7:0] [0.8.0] Offset at point A for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_obco_cfg_3.field.a_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_3.field.a_s0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0] Offset at point B for symbol 3
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_obco_cfg_3.field.b_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_3.field.b_s0 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0] Offset at point C for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_obco_cfg_3.field.c_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_3.field.c_s0 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0] Offset at point D for symbol 3
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_obco_cfg_3.field.d_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_3.field.d_s0 & ~m_tmp);
			break;

		case 0x0300:
			// Lsb: 0, Len: 9, [8:0] G0 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_0.field.g0_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_0.field.g0_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_0.field.g1_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_0.field.g1_s0 & ~m_tmp);
			break;

		case 0x0304:
			// Lsb: 0, Len: 9, [8:0] G2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_1.field.g2_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_1.field.g2_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_1.field.g3_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_1.field.g3_s0 & ~m_tmp);
			break;

		case 0x0308:
			// Lsb: 0, Len: 9, [8:0] G4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_2.field.g4_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_2.field.g4_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_2.field.g5_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_2.field.g5_s0 & ~m_tmp);
			break;

		case 0x030C:
			// Lsb: 0, Len: 9, [8:0] G6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_3.field.g6_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_3.field.g6_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_3.field.g7_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_3.field.g7_s0 & ~m_tmp);
			break;

		case 0x0310:
			// Lsb: 0, Len: 9, [8:0] G8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_4.field.g8_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_4.field.g8_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_4.field.g9_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_4.field.g9_s0 & ~m_tmp);
			break;

		case 0x0314:
			// Lsb: 0, Len: 9, [8:0] G10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_5.field.g10_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_5.field.g10_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_5.field.g11_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_5.field.g11_s0 & ~m_tmp);
			break;

		case 0x0318:
			// Lsb: 0, Len: 9, [8:0] G12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_6.field.g12_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_6.field.g12_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_6.field.g13_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_6.field.g13_s0 & ~m_tmp);
			break;

		case 0x031C:
			// Lsb: 0, Len: 9, [8:0] G14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_7.field.g14_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_7.field.g14_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_7.field.g15_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_7.field.g15_s0 & ~m_tmp);
			break;

		case 0x0320:
			// Lsb: 0, Len: 9, [8:0] G16 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_8.field.g16_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_8.field.g16_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G17 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_8.field.g17_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_8.field.g17_s0 & ~m_tmp);
			break;

		case 0x0324:
			// Lsb: 0, Len: 9, [8:0] G18 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_9.field.g18_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_9.field.g18_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G19 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_9.field.g19_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_9.field.g19_s0 & ~m_tmp);
			break;

		case 0x0328:
			// Lsb: 0, Len: 9, [8:0] G20 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_10.field.g20_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_10.field.g20_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G21 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_10.field.g21_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_10.field.g21_s0 & ~m_tmp);
			break;

		case 0x032C:
			// Lsb: 0, Len: 9, [8:0] G22 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_11.field.g22_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_11.field.g22_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain0_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G23 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain0_cfg_11.field.g23_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_11.field.g23_s0 & ~m_tmp);
			break;

		case 0x0330:
			// Lsb: 0, Len: 9, [8:0] G24 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain0_cfg_12.field.g24_s0 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_12.field.g24_s0 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_gain0_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain0_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x0334:
			// Lsb: 0, Len: 9, [8:0] G0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_0.field.g0_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_0.field.g0_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_0.field.g1_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_0.field.g1_s1 & ~m_tmp);
			break;

		case 0x0338:
			// Lsb: 0, Len: 9, [8:0] G2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_1.field.g2_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_1.field.g2_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_1.field.g3_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_1.field.g3_s1 & ~m_tmp);
			break;

		case 0x033C:
			// Lsb: 0, Len: 9, [8:0] G4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_2.field.g4_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_2.field.g4_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_2.field.g5_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_2.field.g5_s1 & ~m_tmp);
			break;

		case 0x0340:
			// Lsb: 0, Len: 9, [8:0] G6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_3.field.g6_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_3.field.g6_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_3.field.g7_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_3.field.g7_s1 & ~m_tmp);
			break;

		case 0x0344:
			// Lsb: 0, Len: 9, [8:0] G8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_4.field.g8_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_4.field.g8_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_4.field.g9_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_4.field.g9_s1 & ~m_tmp);
			break;

		case 0x0348:
			// Lsb: 0, Len: 9, [8:0] G10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_5.field.g10_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_5.field.g10_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_5.field.g11_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_5.field.g11_s1 & ~m_tmp);
			break;

		case 0x034C:
			// Lsb: 0, Len: 9, [8:0] G12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_6.field.g12_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_6.field.g12_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_6.field.g13_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_6.field.g13_s1 & ~m_tmp);
			break;

		case 0x0350:
			// Lsb: 0, Len: 9, [8:0] G14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_7.field.g14_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_7.field.g14_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_7.field.g15_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_7.field.g15_s1 & ~m_tmp);
			break;

		case 0x0354:
			// Lsb: 0, Len: 9, [8:0] G16 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_8.field.g16_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_8.field.g16_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G17 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_8.field.g17_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_8.field.g17_s1 & ~m_tmp);
			break;

		case 0x0358:
			// Lsb: 0, Len: 9, [8:0] G18 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_9.field.g18_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_9.field.g18_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G19 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_9.field.g19_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_9.field.g19_s1 & ~m_tmp);
			break;

		case 0x035C:
			// Lsb: 0, Len: 9, [8:0] G20 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_10.field.g20_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_10.field.g20_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G21 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_10.field.g21_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_10.field.g21_s1 & ~m_tmp);
			break;

		case 0x0360:
			// Lsb: 0, Len: 9, [8:0] G22 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_11.field.g22_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_11.field.g22_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain1_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G23 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain1_cfg_11.field.g23_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_11.field.g23_s1 & ~m_tmp);
			break;

		case 0x0364:
			// Lsb: 0, Len: 9, [8:0] G24 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain1_cfg_12.field.g24_s1 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_12.field.g24_s1 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_gain1_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain1_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x0368:
			// Lsb: 0, Len: 9, [8:0] G0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_0.field.g0_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_0.field.g0_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_0.field.g1_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_0.field.g1_s2 & ~m_tmp);
			break;

		case 0x036C:
			// Lsb: 0, Len: 9, [8:0] G2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_1.field.g2_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_1.field.g2_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_1.field.g3_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_1.field.g3_s2 & ~m_tmp);
			break;

		case 0x0370:
			// Lsb: 0, Len: 9, [8:0] G4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_2.field.g4_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_2.field.g4_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_2.field.g5_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_2.field.g5_s2 & ~m_tmp);
			break;

		case 0x0374:
			// Lsb: 0, Len: 9, [8:0] G6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_3.field.g6_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_3.field.g6_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_3.field.g7_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_3.field.g7_s2 & ~m_tmp);
			break;

		case 0x0378:
			// Lsb: 0, Len: 9, [8:0] G8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_4.field.g8_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_4.field.g8_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_4.field.g9_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_4.field.g9_s2 & ~m_tmp);
			break;

		case 0x037C:
			// Lsb: 0, Len: 9, [8:0] G10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_5.field.g10_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_5.field.g10_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_5.field.g11_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_5.field.g11_s2 & ~m_tmp);
			break;

		case 0x0380:
			// Lsb: 0, Len: 9, [8:0] G12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_6.field.g12_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_6.field.g12_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_6.field.g13_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_6.field.g13_s2 & ~m_tmp);
			break;

		case 0x0384:
			// Lsb: 0, Len: 9, [8:0] G14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_7.field.g14_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_7.field.g14_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_7.field.g15_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_7.field.g15_s2 & ~m_tmp);
			break;

		case 0x0388:
			// Lsb: 0, Len: 9, [8:0] G16 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_8.field.g16_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_8.field.g16_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G17 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_8.field.g17_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_8.field.g17_s2 & ~m_tmp);
			break;

		case 0x038C:
			// Lsb: 0, Len: 9, [8:0] G18 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_9.field.g18_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_9.field.g18_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G19 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_9.field.g19_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_9.field.g19_s2 & ~m_tmp);
			break;

		case 0x0390:
			// Lsb: 0, Len: 9, [8:0] G20 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_10.field.g20_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_10.field.g20_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G21 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_10.field.g21_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_10.field.g21_s2 & ~m_tmp);
			break;

		case 0x0394:
			// Lsb: 0, Len: 9, [8:0] G22 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_11.field.g22_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_11.field.g22_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain2_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G23 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain2_cfg_11.field.g23_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_11.field.g23_s2 & ~m_tmp);
			break;

		case 0x0398:
			// Lsb: 0, Len: 9, [8:0] G24 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain2_cfg_12.field.g24_s2 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_12.field.g24_s2 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_gain2_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain2_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x039C:
			// Lsb: 0, Len: 9, [8:0] G0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_0.field.g0_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_0.field.g0_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_0.field.g1_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_0.field.g1_s3 & ~m_tmp);
			break;

		case 0x03A0:
			// Lsb: 0, Len: 9, [8:0] G2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_1.field.g2_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_1.field.g2_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_1.field.g3_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_1.field.g3_s3 & ~m_tmp);
			break;

		case 0x03A4:
			// Lsb: 0, Len: 9, [8:0] G4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_2.field.g4_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_2.field.g4_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_2.field.g5_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_2.field.g5_s3 & ~m_tmp);
			break;

		case 0x03A8:
			// Lsb: 0, Len: 9, [8:0] G6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_3.field.g6_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_3.field.g6_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_3.field.g7_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_3.field.g7_s3 & ~m_tmp);
			break;

		case 0x03AC:
			// Lsb: 0, Len: 9, [8:0] G8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_4.field.g8_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_4.field.g8_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_4.field.g9_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_4.field.g9_s3 & ~m_tmp);
			break;

		case 0x03B0:
			// Lsb: 0, Len: 9, [8:0] G10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_5.field.g10_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_5.field.g10_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_5.field.g11_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_5.field.g11_s3 & ~m_tmp);
			break;

		case 0x03B4:
			// Lsb: 0, Len: 9, [8:0] G12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_6.field.g12_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_6.field.g12_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_6.field.g13_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_6.field.g13_s3 & ~m_tmp);
			break;

		case 0x03B8:
			// Lsb: 0, Len: 9, [8:0] G14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_7.field.g14_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_7.field.g14_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_7.field.g15_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_7.field.g15_s3 & ~m_tmp);
			break;

		case 0x03BC:
			// Lsb: 0, Len: 9, [8:0] G16 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_8.field.g16_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_8.field.g16_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G17 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_8.field.g17_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_8.field.g17_s3 & ~m_tmp);
			break;

		case 0x03C0:
			// Lsb: 0, Len: 9, [8:0] G18 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_9.field.g18_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_9.field.g18_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G19 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_9.field.g19_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_9.field.g19_s3 & ~m_tmp);
			break;

		case 0x03C4:
			// Lsb: 0, Len: 9, [8:0] G20 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_10.field.g20_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_10.field.g20_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G21 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_10.field.g21_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_10.field.g21_s3 & ~m_tmp);
			break;

		case 0x03C8:
			// Lsb: 0, Len: 9, [8:0] G22 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_11.field.g22_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_11.field.g22_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_gain3_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] G23 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_gain3_cfg_11.field.g23_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_11.field.g23_s3 & ~m_tmp);
			break;

		case 0x03CC:
			// Lsb: 0, Len: 9, [8:0] G24 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_gain3_cfg_12.field.g24_s3 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_12.field.g24_s3 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_gain3_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_gain3_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x03D0:
			// Lsb: 0, Len: 12, [11:0] [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_oecfhm_y_cfg_0.field.y0 = (d_tmp & m_tmp) | (reg_oecfhm_y_cfg_0.field.y0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_oecfhm_y_cfg_0.field.rsvd12 = (d_tmp & m_tmp) | (reg_oecfhm_y_cfg_0.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_oecfhm_y_cfg_0.field.y1 = (d_tmp & m_tmp) | (reg_oecfhm_y_cfg_0.field.y1 & ~m_tmp);
			break;

		case 0x03D4:
			// Lsb: 0, Len: 12, [11:0] [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_oecfhm_y_cfg_1.field.y2 = (d_tmp & m_tmp) | (reg_oecfhm_y_cfg_1.field.y2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_oecfhm_y_cfg_1.field.rsvd12 = (d_tmp & m_tmp) | (reg_oecfhm_y_cfg_1.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_oecfhm_y_cfg_1.field.y3 = (d_tmp & m_tmp) | (reg_oecfhm_y_cfg_1.field.y3 & ~m_tmp);
			break;

		case 0x03D8:
			// Lsb: 0, Len: 12, [11:0] [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_oecfhm_y_cfg_2.field.y4 = (d_tmp & m_tmp) | (reg_oecfhm_y_cfg_2.field.y4 & ~m_tmp);
			break;

		case 0x03DC:
			// Lsb: 0, Len: 16, [15:0] [1.4.11]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfhm_s_cfg_0.field.s0 = (d_tmp & m_tmp) | (reg_oecfhm_s_cfg_0.field.s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] [1.4.11]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfhm_s_cfg_0.field.s1 = (d_tmp & m_tmp) | (reg_oecfhm_s_cfg_0.field.s1 & ~m_tmp);
			break;

		case 0x03E0:
			// Lsb: 0, Len: 16, [15:0] [1.4.11]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfhm_s_cfg_1.field.s2 = (d_tmp & m_tmp) | (reg_oecfhm_s_cfg_1.field.s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] [1.4.11]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfhm_s_cfg_1.field.s3 = (d_tmp & m_tmp) | (reg_oecfhm_s_cfg_1.field.s3 & ~m_tmp);
			break;

		case 0x03E4:
			// Lsb: 0, Len: 16, [15:0] [1.4.11]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfhm_s_cfg_2.field.s4 = (d_tmp & m_tmp) | (reg_oecfhm_s_cfg_2.field.s4 & ~m_tmp);
			break;

		case 0x0400:
			// Lsb: 0, Len: 9, [8:0] S0 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_0.field.s0_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_0.field.s0_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_0.field.s1_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_0.field.s1_s0 & ~m_tmp);
			break;

		case 0x0404:
			// Lsb: 0, Len: 9, [8:0] S2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_1.field.s2_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_1.field.s2_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_1.field.s3_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_1.field.s3_s0 & ~m_tmp);
			break;

		case 0x0408:
			// Lsb: 0, Len: 9, [8:0] S4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_2.field.s4_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_2.field.s4_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_2.field.s5_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_2.field.s5_s0 & ~m_tmp);
			break;

		case 0x040C:
			// Lsb: 0, Len: 9, [8:0] S6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_3.field.s6_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_3.field.s6_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_3.field.s7_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_3.field.s7_s0 & ~m_tmp);
			break;

		case 0x0410:
			// Lsb: 0, Len: 9, [8:0] S8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_4.field.s8_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_4.field.s8_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_4.field.s9_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_4.field.s9_s0 & ~m_tmp);
			break;

		case 0x0414:
			// Lsb: 0, Len: 9, [8:0] S10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_5.field.s10_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_5.field.s10_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_5.field.s11_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_5.field.s11_s0 & ~m_tmp);
			break;

		case 0x0418:
			// Lsb: 0, Len: 9, [8:0] S12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_6.field.s12_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_6.field.s12_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_6.field.s13_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_6.field.s13_s0 & ~m_tmp);
			break;

		case 0x041C:
			// Lsb: 0, Len: 9, [8:0] S14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_7.field.s14_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_7.field.s14_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_7.field.s15_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_7.field.s15_s0 & ~m_tmp);
			break;

		case 0x0420:
			// Lsb: 0, Len: 9, [8:0] S16 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_8.field.s16_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_8.field.s16_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S17 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_8.field.s17_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_8.field.s17_s0 & ~m_tmp);
			break;

		case 0x0424:
			// Lsb: 0, Len: 9, [8:0] S18 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_9.field.s18_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_9.field.s18_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S19 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_9.field.s19_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_9.field.s19_s0 & ~m_tmp);
			break;

		case 0x0428:
			// Lsb: 0, Len: 9, [8:0] S20 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_10.field.s20_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_10.field.s20_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S21 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_10.field.s21_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_10.field.s21_s0 & ~m_tmp);
			break;

		case 0x042C:
			// Lsb: 0, Len: 9, [8:0] S22 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_11.field.s22_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_11.field.s22_s0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset0_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S23 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset0_cfg_11.field.s23_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_11.field.s23_s0 & ~m_tmp);
			break;

		case 0x0430:
			// Lsb: 0, Len: 9, [8:0] S24 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset0_cfg_12.field.s24_s0 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_12.field.s24_s0 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_offset0_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset0_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x0434:
			// Lsb: 0, Len: 9, [8:0] S0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_0.field.s0_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_0.field.s0_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_0.field.s1_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_0.field.s1_s1 & ~m_tmp);
			break;

		case 0x0438:
			// Lsb: 0, Len: 9, [8:0] S2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_1.field.s2_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_1.field.s2_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_1.field.s3_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_1.field.s3_s1 & ~m_tmp);
			break;

		case 0x043C:
			// Lsb: 0, Len: 9, [8:0] S4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_2.field.s4_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_2.field.s4_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_2.field.s5_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_2.field.s5_s1 & ~m_tmp);
			break;

		case 0x0440:
			// Lsb: 0, Len: 9, [8:0] S6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_3.field.s6_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_3.field.s6_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_3.field.s7_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_3.field.s7_s1 & ~m_tmp);
			break;

		case 0x0444:
			// Lsb: 0, Len: 9, [8:0] S8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_4.field.s8_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_4.field.s8_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_4.field.s9_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_4.field.s9_s1 & ~m_tmp);
			break;

		case 0x0448:
			// Lsb: 0, Len: 9, [8:0] S10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_5.field.s10_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_5.field.s10_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_5.field.s11_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_5.field.s11_s1 & ~m_tmp);
			break;

		case 0x044C:
			// Lsb: 0, Len: 9, [8:0] S12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_6.field.s12_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_6.field.s12_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_6.field.s13_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_6.field.s13_s1 & ~m_tmp);
			break;

		case 0x0450:
			// Lsb: 0, Len: 9, [8:0] S14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_7.field.s14_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_7.field.s14_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_7.field.s15_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_7.field.s15_s1 & ~m_tmp);
			break;

		case 0x0454:
			// Lsb: 0, Len: 9, [8:0] S16 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_8.field.s16_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_8.field.s16_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S17 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_8.field.s17_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_8.field.s17_s1 & ~m_tmp);
			break;

		case 0x0458:
			// Lsb: 0, Len: 9, [8:0] S18 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_9.field.s18_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_9.field.s18_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S19 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_9.field.s19_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_9.field.s19_s1 & ~m_tmp);
			break;

		case 0x045C:
			// Lsb: 0, Len: 9, [8:0] S20 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_10.field.s20_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_10.field.s20_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S21 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_10.field.s21_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_10.field.s21_s1 & ~m_tmp);
			break;

		case 0x0460:
			// Lsb: 0, Len: 9, [8:0] S22 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_11.field.s22_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_11.field.s22_s1 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset1_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S23 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset1_cfg_11.field.s23_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_11.field.s23_s1 & ~m_tmp);
			break;

		case 0x0464:
			// Lsb: 0, Len: 9, [8:0] S24 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset1_cfg_12.field.s24_s1 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_12.field.s24_s1 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_offset1_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset1_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x0468:
			// Lsb: 0, Len: 9, [8:0] S0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_0.field.s0_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_0.field.s0_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_0.field.s1_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_0.field.s1_s2 & ~m_tmp);
			break;

		case 0x046C:
			// Lsb: 0, Len: 9, [8:0] S2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_1.field.s2_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_1.field.s2_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_1.field.s3_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_1.field.s3_s2 & ~m_tmp);
			break;

		case 0x0470:
			// Lsb: 0, Len: 9, [8:0] S4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_2.field.s4_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_2.field.s4_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_2.field.s5_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_2.field.s5_s2 & ~m_tmp);
			break;

		case 0x0474:
			// Lsb: 0, Len: 9, [8:0] S6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_3.field.s6_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_3.field.s6_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_3.field.s7_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_3.field.s7_s2 & ~m_tmp);
			break;

		case 0x0478:
			// Lsb: 0, Len: 9, [8:0] S8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_4.field.s8_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_4.field.s8_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_4.field.s9_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_4.field.s9_s2 & ~m_tmp);
			break;

		case 0x047C:
			// Lsb: 0, Len: 9, [8:0] S10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_5.field.s10_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_5.field.s10_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_5.field.s11_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_5.field.s11_s2 & ~m_tmp);
			break;

		case 0x0480:
			// Lsb: 0, Len: 9, [8:0] S12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_6.field.s12_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_6.field.s12_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_6.field.s13_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_6.field.s13_s2 & ~m_tmp);
			break;

		case 0x0484:
			// Lsb: 0, Len: 9, [8:0] S14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_7.field.s14_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_7.field.s14_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_7.field.s15_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_7.field.s15_s2 & ~m_tmp);
			break;

		case 0x0488:
			// Lsb: 0, Len: 9, [8:0] S16 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_8.field.s16_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_8.field.s16_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S17 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_8.field.s17_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_8.field.s17_s2 & ~m_tmp);
			break;

		case 0x048C:
			// Lsb: 0, Len: 9, [8:0] S18 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_9.field.s18_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_9.field.s18_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S19 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_9.field.s19_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_9.field.s19_s2 & ~m_tmp);
			break;

		case 0x0490:
			// Lsb: 0, Len: 9, [8:0] S20 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_10.field.s20_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_10.field.s20_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S21 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_10.field.s21_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_10.field.s21_s2 & ~m_tmp);
			break;

		case 0x0494:
			// Lsb: 0, Len: 9, [8:0] S22 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_11.field.s22_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_11.field.s22_s2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset2_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S23 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset2_cfg_11.field.s23_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_11.field.s23_s2 & ~m_tmp);
			break;

		case 0x0498:
			// Lsb: 0, Len: 9, [8:0] S24 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset2_cfg_12.field.s24_s2 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_12.field.s24_s2 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_offset2_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset2_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x049C:
			// Lsb: 0, Len: 9, [8:0] S0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_0.field.s0_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_0.field.s0_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_0.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_0.field.s1_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_0.field.s1_s3 & ~m_tmp);
			break;

		case 0x04A0:
			// Lsb: 0, Len: 9, [8:0] S2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_1.field.s2_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_1.field.s2_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_1.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_1.field.s3_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_1.field.s3_s3 & ~m_tmp);
			break;

		case 0x04A4:
			// Lsb: 0, Len: 9, [8:0] S4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_2.field.s4_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_2.field.s4_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_2.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_2.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_2.field.s5_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_2.field.s5_s3 & ~m_tmp);
			break;

		case 0x04A8:
			// Lsb: 0, Len: 9, [8:0] S6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_3.field.s6_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_3.field.s6_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_3.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_3.field.s7_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_3.field.s7_s3 & ~m_tmp);
			break;

		case 0x04AC:
			// Lsb: 0, Len: 9, [8:0] S8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_4.field.s8_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_4.field.s8_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_4.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_4.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_4.field.s9_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_4.field.s9_s3 & ~m_tmp);
			break;

		case 0x04B0:
			// Lsb: 0, Len: 9, [8:0] S10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_5.field.s10_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_5.field.s10_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_5.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_5.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_5.field.s11_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_5.field.s11_s3 & ~m_tmp);
			break;

		case 0x04B4:
			// Lsb: 0, Len: 9, [8:0] S12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_6.field.s12_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_6.field.s12_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_6.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_6.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_6.field.s13_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_6.field.s13_s3 & ~m_tmp);
			break;

		case 0x04B8:
			// Lsb: 0, Len: 9, [8:0] S14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_7.field.s14_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_7.field.s14_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_7.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_7.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_7.field.s15_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_7.field.s15_s3 & ~m_tmp);
			break;

		case 0x04BC:
			// Lsb: 0, Len: 9, [8:0] S16 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_8.field.s16_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_8.field.s16_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_8.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_8.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S17 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_8.field.s17_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_8.field.s17_s3 & ~m_tmp);
			break;

		case 0x04C0:
			// Lsb: 0, Len: 9, [8:0] S18 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_9.field.s18_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_9.field.s18_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_9.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_9.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S19 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_9.field.s19_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_9.field.s19_s3 & ~m_tmp);
			break;

		case 0x04C4:
			// Lsb: 0, Len: 9, [8:0] S20 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_10.field.s20_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_10.field.s20_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_10.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_10.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S21 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_10.field.s21_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_10.field.s21_s3 & ~m_tmp);
			break;

		case 0x04C8:
			// Lsb: 0, Len: 9, [8:0] S22 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_11.field.s22_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_11.field.s22_s3 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_lcbq_offset3_cfg_11.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_11.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] S23 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_lcbq_offset3_cfg_11.field.s23_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_11.field.s23_s3 & ~m_tmp);
			break;

		case 0x04CC:
			// Lsb: 0, Len: 9, [8:0] S24 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_lcbq_offset3_cfg_12.field.s24_s3 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_12.field.s24_s3 & ~m_tmp);

			// Lsb: 9, Len: 23, [31:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x007FFFFF;
			reg_lcbq_offset3_cfg_12.field.rsvd9 = (d_tmp & m_tmp) | (reg_lcbq_offset3_cfg_12.field.rsvd9 & ~m_tmp);
			break;

		case 0x04D0:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(0,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(0,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(0,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(0,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(0,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(0,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(0,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(0,7), [c][r]
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_0.field.awb_ws_cw_w_0_7 & ~m_tmp);
			break;

		case 0x04D4:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(0,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(0,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(0,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(0,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(0,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw0_cfg_1.field.awb_ws_cw_w_0_12 & ~m_tmp);
			break;

		case 0x04D8:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(1,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(1,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(1,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(1,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(1,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(1,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(1,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(1,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_0.field.awb_ws_cw_w_1_7 & ~m_tmp);
			break;

		case 0x04DC:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(1,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(1,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(1,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(1,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(1,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw1_cfg_1.field.awb_ws_cw_w_1_12 & ~m_tmp);
			break;

		case 0x04E0:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(2,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(2,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(2,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(2,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(2,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(2,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(2,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(2,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_0.field.awb_ws_cw_w_2_7 & ~m_tmp);
			break;

		case 0x04E4:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(2,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(2,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(2,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(2,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(2,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw2_cfg_1.field.awb_ws_cw_w_2_12 & ~m_tmp);
			break;

		case 0x04E8:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(3,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(3,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(3,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(3,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(3,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(3,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(3,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(3,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_0.field.awb_ws_cw_w_3_7 & ~m_tmp);
			break;

		case 0x04EC:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(3,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(3,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(3,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(3,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(3,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw3_cfg_1.field.awb_ws_cw_w_3_12 & ~m_tmp);
			break;

		case 0x04F0:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(4,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(4,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(4,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(4,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(4,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(4,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(4,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(4,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_0.field.awb_ws_cw_w_4_7 & ~m_tmp);
			break;

		case 0x04F4:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(4,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(4,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(4,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(4,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(4,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw4_cfg_1.field.awb_ws_cw_w_4_12 & ~m_tmp);
			break;

		case 0x04F8:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(5,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(5,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(5,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(5,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(5,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(5,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(5,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(5,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_0.field.awb_ws_cw_w_5_7 & ~m_tmp);
			break;

		case 0x04FC:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(5,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(5,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(5,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(5,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(5,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw5_cfg_1.field.awb_ws_cw_w_5_12 & ~m_tmp);
			break;

		case 0x0500:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(6,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(6,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(6,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(6,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(6,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(6,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(6,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(6,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_0.field.awb_ws_cw_w_6_7 & ~m_tmp);
			break;

		case 0x0504:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(6,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(6,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(6,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(6,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(6,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw6_cfg_1.field.awb_ws_cw_w_6_12 & ~m_tmp);
			break;

		case 0x0508:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(7,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(7,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(7,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(7,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(7,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(7,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(7,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(7,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_0.field.awb_ws_cw_w_7_7 & ~m_tmp);
			break;

		case 0x050C:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(7,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(7,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(7,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(7,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(7,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw7_cfg_1.field.awb_ws_cw_w_7_12 & ~m_tmp);
			break;

		case 0x0510:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(8,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(8,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(8,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(8,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(8,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(8,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(8,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(8,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_0.field.awb_ws_cw_w_8_7 & ~m_tmp);
			break;

		case 0x0514:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(8,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(8,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(8,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(8,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(8,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw8_cfg_1.field.awb_ws_cw_w_8_12 & ~m_tmp);
			break;

		case 0x0518:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(9,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(9,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(9,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(9,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(9,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(9,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(9,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(9,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_0.field.awb_ws_cw_w_9_7 & ~m_tmp);
			break;

		case 0x051C:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(9,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(9,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(9,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(9,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(9,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw9_cfg_1.field.awb_ws_cw_w_9_12 & ~m_tmp);
			break;

		case 0x0520:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(10,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(10,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(10,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(10,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(10,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(10,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(10,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(10,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_0.field.awb_ws_cw_w_10_7 & ~m_tmp);
			break;

		case 0x0524:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(10,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(10,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(10,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(10,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(10,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw10_cfg_1.field.awb_ws_cw_w_10_12 & ~m_tmp);
			break;

		case 0x0528:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(11,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(11,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(11,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(11,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(11,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(11,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(11,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(11,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_0.field.awb_ws_cw_w_11_7 & ~m_tmp);
			break;

		case 0x052C:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(11,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(11,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(11,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(11,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(11,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw11_cfg_1.field.awb_ws_cw_w_11_12 & ~m_tmp);
			break;

		case 0x0530:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(12,0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(12,1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(12,2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(12,3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(12,4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(12,5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(12,6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(12,7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_0.field.awb_ws_cw_w_12_7 & ~m_tmp);
			break;

		case 0x0534:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(12,8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(12,9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(12,10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(12,11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(12,12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_cw12_cfg_1.field.awb_ws_cw_w_12_12 & ~m_tmp);
			break;

		case 0x0538:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(1)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(2)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(3)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(5)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(6)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(7)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_0.field.awb_ws_iw_v_7 & ~m_tmp);
			break;

		case 0x053C:
			// Lsb: 0, Len: 4, [3:0] [0.4.0]Weighting value at point(8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_8 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0]Weighting value at point(9)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_9 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0]Weighting value at point(10)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0]Weighting value at point(11)
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0]Weighting value at point(12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_12 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0]Weighting value at point(13)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_13 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_13 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0]Weighting value at point(14)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_14 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_14 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0]Weighting value at point(15)
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_15 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iwv_cfg_1.field.awb_ws_iw_v_15 & ~m_tmp);
			break;

		case 0x0540:
			// Lsb: 0, Len: 8, [7:0] [1.2.5]Slope value at point(0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_0 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [1.2.5]Slope value at point(1)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_1 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_1 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [1.2.5]Slope value at point(2)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_2 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_2 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [1.2.5]Slope value at point(3)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_3 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_0.field.awb_ws_iw_s_3 & ~m_tmp);
			break;

		case 0x0544:
			// Lsb: 0, Len: 8, [7:0] [1.2.5]Slope value at point(4)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_4 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_4 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [1.2.5]Slope value at point(5)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_5 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_5 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [1.2.5]Slope value at point(6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_6 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_6 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [1.2.5]Slope value at point(7)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_7 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_1.field.awb_ws_iw_s_7 & ~m_tmp);
			break;

		case 0x0548:
			// Lsb: 0, Len: 8, [7:0] [1.2.5]Slope value at point(8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_8 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_8 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [1.2.5]Slope value at point(9)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_9 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_9 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [1.2.5]Slope value at point(10)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_10 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_10 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [1.2.5]Slope value at point(11)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_11 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_2.field.awb_ws_iw_s_11 & ~m_tmp);
			break;

		case 0x054C:
			// Lsb: 0, Len: 8, [7:0] [1.2.5]Slope value at point(12)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_12 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_12 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [1.2.5]Slope value at point(13)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_13 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_13 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [1.2.5]Slope value at point(14)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_14 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_14 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [1.2.5]Slope value at point(15)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_15 = (d_tmp & m_tmp) | (reg_sc_awb_ws_iws_cfg_3.field.awb_ws_iw_s_15 & ~m_tmp);
			break;

		case 0x05D0:
			// Lsb: 0, Len: 8, [7:0] [0.8.0]Lower boundary of R value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ws_cfg_0.field.awb_ws_rl = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_0.field.awb_ws_rl & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0]Upper boundary of R value
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ws_cfg_0.field.awb_ws_ru = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_0.field.awb_ws_ru & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0]Lower boundary of Gr value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ws_cfg_0.field.awb_ws_grl = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_0.field.awb_ws_grl & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0]Upper boundary of Gr value
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ws_cfg_0.field.awb_ws_gru = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_0.field.awb_ws_gru & ~m_tmp);
			break;

		case 0x05D4:
			// Lsb: 0, Len: 8, [7:0] [0.8.0]Lower boundary of Gb value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_sc_awb_ws_cfg_1.field.awb_ws_gbl = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_1.field.awb_ws_gbl & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] [0.8.0]Upper boundary of Gb value
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_sc_awb_ws_cfg_1.field.awb_ws_gbu = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_1.field.awb_ws_gbu & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.8.0]Lower boundary of B value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc_awb_ws_cfg_1.field.awb_ws_bl = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_1.field.awb_ws_bl & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] [0.8.0]Upper boundary of B value
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_sc_awb_ws_cfg_1.field.awb_ws_bu = (d_tmp & m_tmp) | (reg_sc_awb_ws_cfg_1.field.awb_ws_bu & ~m_tmp);
			break;

		case 0x0600:
			// Lsb: 0, Len: 13, [12:0] Color bar frame width (xsize)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_csicbfs.field.htotal = (d_tmp & m_tmp) | (reg_csicbfs.field.htotal & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] Reserved
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_csicbfs.field.rsvd13 = (d_tmp & m_tmp) | (reg_csicbfs.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Color bar frame height (ysize)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_csicbfs.field.vtotal = (d_tmp & m_tmp) | (reg_csicbfs.field.vtotal & ~m_tmp);
			break;

		case 0x0604:
			// Lsb: 0, Len: 13, [12:0] Horizontal start point
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_csicbs.field.hstart = (d_tmp & m_tmp) | (reg_csicbs.field.hstart & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] Reserved
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_csicbs.field.rsvd13 = (d_tmp & m_tmp) | (reg_csicbs.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Vertical start point
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_csicbs.field.vstart = (d_tmp & m_tmp) | (reg_csicbs.field.vstart & ~m_tmp);
			break;

		case 0x0608:
			// Lsb: 0, Len: 13, [12:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_csicbe.field.hend = (d_tmp & m_tmp) | (reg_csicbe.field.hend & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] Reserved
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_csicbe.field.rsvd13 = (d_tmp & m_tmp) | (reg_csicbe.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_csicbe.field.vend = (d_tmp & m_tmp) | (reg_csicbe.field.vend & ~m_tmp);
			break;

		case 0x060C:
			// Lsb: 0, Len: 1, [0] Enable Timing Genrator
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_csicbmd0.field.tg_en = (d_tmp & m_tmp) | (reg_csicbmd0.field.tg_en & ~m_tmp);

			// Lsb: 1, Len: 3, [3:1] Reserved
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000007;
			reg_csicbmd0.field.rsvd1 = (d_tmp & m_tmp) | (reg_csicbmd0.field.rsvd1 & ~m_tmp);

			// Lsb: 4, Len: 1, [4] Enable DVP Mux (switch to test pattern)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_csicbmd0.field.dvp_en = (d_tmp & m_tmp) | (reg_csicbmd0.field.dvp_en & ~m_tmp);

			// Lsb: 5, Len: 1, [5] Enable MIPI Mux (switch to test pattern)
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_csicbmd0.field.mux_en = (d_tmp & m_tmp) | (reg_csicbmd0.field.mux_en & ~m_tmp);

			// Lsb: 6, Len: 2, [7:6] Reserved
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000003;
			reg_csicbmd0.field.rsvd6 = (d_tmp & m_tmp) | (reg_csicbmd0.field.rsvd6 & ~m_tmp);

			// Lsb: 8, Len: 1, [8] H Sync Polarity
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000001;
			reg_csicbmd0.field.hpolarity = (d_tmp & m_tmp) | (reg_csicbmd0.field.hpolarity & ~m_tmp);

			// Lsb: 9, Len: 1, [9] V Sync Polarity
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_csicbmd0.field.vpolarity = (d_tmp & m_tmp) | (reg_csicbmd0.field.vpolarity & ~m_tmp);

			// Lsb: 11, Len: 1, [11] Reserved
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_csicbmd0.field.rsvd10 = (d_tmp & m_tmp) | (reg_csicbmd0.field.rsvd10 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Pattern type:
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbmd0.field.pattern = (d_tmp & m_tmp) | (reg_csicbmd0.field.pattern & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] Horizontal bar width: 2^(WIDTH+1)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_csicbmd0.field.hwidth = (d_tmp & m_tmp) | (reg_csicbmd0.field.hwidth & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] Vertical bar width: 2^(WIDTH+1)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_csicbmd0.field.vwidth = (d_tmp & m_tmp) | (reg_csicbmd0.field.vwidth & ~m_tmp);
			break;

		case 0x0610:
			// Lsb: 0, Len: 32, [31:0] Mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_csicbmd1.field.md = (d_tmp & m_tmp) | (reg_csicbmd1.field.md & ~m_tmp);
			break;

		case 0x0614:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbp01.field.p0 = (d_tmp & m_tmp) | (reg_csicbp01.field.p0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbp01.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbp01.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbp01.field.p1 = (d_tmp & m_tmp) | (reg_csicbp01.field.p1 & ~m_tmp);
			break;

		case 0x0618:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbp23.field.p2 = (d_tmp & m_tmp) | (reg_csicbp23.field.p2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbp23.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbp23.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbp23.field.p3 = (d_tmp & m_tmp) | (reg_csicbp23.field.p3 & ~m_tmp);
			break;

		case 0x061C:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbp45.field.p4 = (d_tmp & m_tmp) | (reg_csicbp45.field.p4 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbp45.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbp45.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbp45.field.p5 = (d_tmp & m_tmp) | (reg_csicbp45.field.p5 & ~m_tmp);
			break;

		case 0x0620:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbp67.field.p6 = (d_tmp & m_tmp) | (reg_csicbp67.field.p6 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbp67.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbp67.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbp67.field.p7 = (d_tmp & m_tmp) | (reg_csicbp67.field.p7 & ~m_tmp);
			break;

		case 0x0624:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbp89.field.p8 = (d_tmp & m_tmp) | (reg_csicbp89.field.p8 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbp89.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbp89.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbp89.field.p9 = (d_tmp & m_tmp) | (reg_csicbp89.field.p9 & ~m_tmp);
			break;

		case 0x0628:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbpab.field.pa = (d_tmp & m_tmp) | (reg_csicbpab.field.pa & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbpab.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbpab.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbpab.field.pb = (d_tmp & m_tmp) | (reg_csicbpab.field.pb & ~m_tmp);
			break;

		case 0x062C:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbpcd.field.pc = (d_tmp & m_tmp) | (reg_csicbpcd.field.pc & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbpcd.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbpcd.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbpcd.field.pd = (d_tmp & m_tmp) | (reg_csicbpcd.field.pd & ~m_tmp);
			break;

		case 0x0630:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbpef.field.pe = (d_tmp & m_tmp) | (reg_csicbpef.field.pe & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbpef.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbpef.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbpef.field.pf = (d_tmp & m_tmp) | (reg_csicbpef.field.pf & ~m_tmp);
			break;

		case 0x0634:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1p01.field.p0 = (d_tmp & m_tmp) | (reg_csicbl1p01.field.p0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1p01.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1p01.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1p01.field.p1 = (d_tmp & m_tmp) | (reg_csicbl1p01.field.p1 & ~m_tmp);
			break;

		case 0x0638:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1p23.field.p2 = (d_tmp & m_tmp) | (reg_csicbl1p23.field.p2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1p23.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1p23.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1p23.field.p3 = (d_tmp & m_tmp) | (reg_csicbl1p23.field.p3 & ~m_tmp);
			break;

		case 0x063C:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1p45.field.p4 = (d_tmp & m_tmp) | (reg_csicbl1p45.field.p4 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1p45.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1p45.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1p45.field.p5 = (d_tmp & m_tmp) | (reg_csicbl1p45.field.p5 & ~m_tmp);
			break;

		case 0x0640:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1p67.field.p6 = (d_tmp & m_tmp) | (reg_csicbl1p67.field.p6 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1p67.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1p67.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1p67.field.p7 = (d_tmp & m_tmp) | (reg_csicbl1p67.field.p7 & ~m_tmp);
			break;

		case 0x0644:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1p89.field.p8 = (d_tmp & m_tmp) | (reg_csicbl1p89.field.p8 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1p89.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1p89.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1p89.field.p9 = (d_tmp & m_tmp) | (reg_csicbl1p89.field.p9 & ~m_tmp);
			break;

		case 0x0648:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1pab.field.pa = (d_tmp & m_tmp) | (reg_csicbl1pab.field.pa & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1pab.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1pab.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1pab.field.pb = (d_tmp & m_tmp) | (reg_csicbl1pab.field.pb & ~m_tmp);
			break;

		case 0x064C:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1pcd.field.pc = (d_tmp & m_tmp) | (reg_csicbl1pcd.field.pc & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1pcd.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1pcd.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1pcd.field.pd = (d_tmp & m_tmp) | (reg_csicbl1pcd.field.pd & ~m_tmp);
			break;

		case 0x0650:
			// Lsb: 0, Len: 12, [11:0] Pixel value
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_csicbl1pef.field.pe = (d_tmp & m_tmp) | (reg_csicbl1pef.field.pe & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] Reserved
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_csicbl1pef.field.rsvd12 = (d_tmp & m_tmp) | (reg_csicbl1pef.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Pixel value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_csicbl1pef.field.pf = (d_tmp & m_tmp) | (reg_csicbl1pef.field.pf & ~m_tmp);
			break;

		case 0x0A00:
			// Lsb: 0, Len: 1, [0] Enable ISP processor.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ispctrl0.field.en = (d_tmp & m_tmp) | (reg_ispctrl0.field.en & ~m_tmp);

			// Lsb: 1, Len: 1, [1] Reset/initialize ISP processor.
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_ispctrl0.field.rst = (d_tmp & m_tmp) | (reg_ispctrl0.field.rst & ~m_tmp);

			// Lsb: 2, Len: 1, [2] Reserved.
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_ispctrl0.field.enilc = (d_tmp & m_tmp) | (reg_ispctrl0.field.enilc & ~m_tmp);

			// Lsb: 3, Len: 1, [3] Reserved.
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_ispctrl0.field.rstilc = (d_tmp & m_tmp) | (reg_ispctrl0.field.rstilc & ~m_tmp);

			// Lsb: 4, Len: 1, [4] Reserved.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_ispctrl0.field.envs = (d_tmp & m_tmp) | (reg_ispctrl0.field.envs & ~m_tmp);

			// Lsb: 5, Len: 1, [5] Reserved.
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_ispctrl0.field.rstvs = (d_tmp & m_tmp) | (reg_ispctrl0.field.rstvs & ~m_tmp);

			// Lsb: 6, Len: 2, [7:6] Reserved.
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000003;
			reg_ispctrl0.field.rsvd6 = (d_tmp & m_tmp) | (reg_ispctrl0.field.rsvd6 & ~m_tmp);

			// Lsb: 8, Len: 1, [8] Reserved.
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000001;
			reg_ispctrl0.field.enlc = (d_tmp & m_tmp) | (reg_ispctrl0.field.enlc & ~m_tmp);

			// Lsb: 9, Len: 1, [9] Reserved.
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_ispctrl0.field.enov = (d_tmp & m_tmp) | (reg_ispctrl0.field.enov & ~m_tmp);

			// Lsb: 10, Len: 1, [10] Reserved.
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000001;
			reg_ispctrl0.field.endn = (d_tmp & m_tmp) | (reg_ispctrl0.field.endn & ~m_tmp);

			// Lsb: 11, Len: 1, [11] Enable Scaled Stream 0.
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_ispctrl0.field.enss0 = (d_tmp & m_tmp) | (reg_ispctrl0.field.enss0 & ~m_tmp);

			// Lsb: 12, Len: 1, [12] Enable Scaled Stream 1.
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000001;
			reg_ispctrl0.field.enss1 = (d_tmp & m_tmp) | (reg_ispctrl0.field.enss1 & ~m_tmp);

			// Lsb: 13, Len: 1, [13] Reserved.
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000001;
			reg_ispctrl0.field.envsrc = (d_tmp & m_tmp) | (reg_ispctrl0.field.envsrc & ~m_tmp);

			// Lsb: 14, Len: 1, [14] Reserved.
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000001;
			reg_ispctrl0.field.envsr = (d_tmp & m_tmp) | (reg_ispctrl0.field.envsr & ~m_tmp);

			// Lsb: 15, Len: 1, [15] Reserved.
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_ispctrl0.field.envencl = (d_tmp & m_tmp) | (reg_ispctrl0.field.envencl & ~m_tmp);

			// Lsb: 16, Len: 1, [16] Reserved.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000001;
			reg_ispctrl0.field.enlclb = (d_tmp & m_tmp) | (reg_ispctrl0.field.enlclb & ~m_tmp);

			// Lsb: 17, Len: 1, [17] Enable ISP multiple frame mode.
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000001;
			reg_ispctrl0.field.enls = (d_tmp & m_tmp) | (reg_ispctrl0.field.enls & ~m_tmp);

			// Lsb: 18, Len: 2, [19:18] Reserved. These bits always return zero when read.
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000003;
			reg_ispctrl0.field.rsvd18 = (d_tmp & m_tmp) | (reg_ispctrl0.field.rsvd18 & ~m_tmp);

			// Lsb: 20, Len: 1, [20] Enable Unscaled Output.
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000001;
			reg_ispctrl0.field.enuo = (d_tmp & m_tmp) | (reg_ispctrl0.field.enuo & ~m_tmp);

			// Lsb: 21, Len: 2, [22:21] Reserved.
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000003;
			reg_ispctrl0.field.rsvd21 = (d_tmp & m_tmp) | (reg_ispctrl0.field.rsvd21 & ~m_tmp);

			// Lsb: 23, Len: 1, [23] Reserved.
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x00000001;
			reg_ispctrl0.field.rstvencl = (d_tmp & m_tmp) | (reg_ispctrl0.field.rstvencl & ~m_tmp);

			// Lsb: 24, Len: 1, [24] ISP module done interrupt. No trigger if none of scalar outputs is enabled.
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x00000001;
			reg_ispctrl0.field.ints = (d_tmp & m_tmp) | (reg_ispctrl0.field.ints & ~m_tmp);

			// Lsb: 25, Len: 1, [25] CSI capture end interrupt bit.
			d_tmp = (data >> 25); m_tmp = (mask >> 25) & 0x00000001;
			reg_ispctrl0.field.vsint = (d_tmp & m_tmp) | (reg_ispctrl0.field.vsint & ~m_tmp);

			// Lsb: 26, Len: 1, [26] SC dump done interrupt bit. No trigger if SC is disabled.
			d_tmp = (data >> 26); m_tmp = (mask >> 26) & 0x00000001;
			reg_ispctrl0.field.vsfwint = (d_tmp & m_tmp) | (reg_ispctrl0.field.vsfwint & ~m_tmp);

			// Lsb: 27, Len: 1, [27] Line interrupt bit.
			d_tmp = (data >> 27); m_tmp = (mask >> 27) & 0x00000001;
			reg_ispctrl0.field.lberrint = (d_tmp & m_tmp) | (reg_ispctrl0.field.lberrint & ~m_tmp);

			// Lsb: 28, Len: 1, [28] Reserved.
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x00000001;
			reg_ispctrl0.field.rdmaint = (d_tmp & m_tmp) | (reg_ispctrl0.field.rdmaint & ~m_tmp);

			// Lsb: 29, Len: 3, [31:29] Reserved. These bits always return zero when read.
			d_tmp = (data >> 29); m_tmp = (mask >> 29) & 0x00000007;
			reg_ispctrl0.field.rsvd29 = (d_tmp & m_tmp) | (reg_ispctrl0.field.rsvd29 & ~m_tmp);
			break;

		case 0x0A04:
			// Lsb: 0, Len: 1, [0] ISP run status.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ispstat0.field.stat0 = (d_tmp & m_tmp) | (reg_ispstat0.field.stat0 & ~m_tmp);

			// Lsb: 1, Len: 1, [1] Unscaled Output run status.
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_ispstat0.field.stat_uo = (d_tmp & m_tmp) | (reg_ispstat0.field.stat_uo & ~m_tmp);

			// Lsb: 2, Len: 1, [2] Scaler 0 run status.
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_ispstat0.field.stat_ss0 = (d_tmp & m_tmp) | (reg_ispstat0.field.stat_ss0 & ~m_tmp);

			// Lsb: 3, Len: 1, [3] scaler 1 run status.
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_ispstat0.field.stat_ss1 = (d_tmp & m_tmp) | (reg_ispstat0.field.stat_ss1 & ~m_tmp);

			// Lsb: 4, Len: 1, [4] Reserved.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_ispstat0.field.stat1 = (d_tmp & m_tmp) | (reg_ispstat0.field.stat1 & ~m_tmp);

			// Lsb: 5, Len: 1, [5] Reserved.
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_ispstat0.field.stat2 = (d_tmp & m_tmp) | (reg_ispstat0.field.stat2 & ~m_tmp);

			// Lsb: 6, Len: 2, [7:6] Reserved. These bits always return zero when read.
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000003;
			reg_ispstat0.field.rsvd6 = (d_tmp & m_tmp) | (reg_ispstat0.field.rsvd6 & ~m_tmp);

			// Lsb: 8, Len: 1, [8] Reserved.
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000001;
			reg_ispstat0.field.lberr = (d_tmp & m_tmp) | (reg_ispstat0.field.lberr & ~m_tmp);

			// Lsb: 9, Len: 1, [9] CSI interface buffer located in between CSI and ISP status.
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_ispstat0.field.ciferr = (d_tmp & m_tmp) | (reg_ispstat0.field.ciferr & ~m_tmp);

			// Lsb: 10, Len: 22, [31:10] Reserved. These bits always return zero when read.
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x003FFFFF;
			reg_ispstat0.field.rsvd10 = (d_tmp & m_tmp) | (reg_ispstat0.field.rsvd10 & ~m_tmp);
			break;

		case 0x0A08:
			// Lsb: 0, Len: 1, [0] Reserved.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ispctrl1.field.rsvd0 = (d_tmp & m_tmp) | (reg_ispctrl1.field.rsvd0 & ~m_tmp);

			// Lsb: 1, Len: 1, [1] CFA filter enable.
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_ispctrl1.field.ce = (d_tmp & m_tmp) | (reg_ispctrl1.field.ce & ~m_tmp);

			// Lsb: 2, Len: 1, [2] Color Artifact removal filter enable.
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_ispctrl1.field.ae = (d_tmp & m_tmp) | (reg_ispctrl1.field.ae & ~m_tmp);

			// Lsb: 3, Len: 1, [3] Color Correction Matrix enable.
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_ispctrl1.field.cme = (d_tmp & m_tmp) | (reg_ispctrl1.field.cme & ~m_tmp);

			// Lsb: 4, Len: 1, [4] RGB Gamma enable.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_ispctrl1.field.rge = (d_tmp & m_tmp) | (reg_ispctrl1.field.rge & ~m_tmp);

			// Lsb: 5, Len: 1, [5] RGB to YUV color space conversion enable.
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_ispctrl1.field.cce = (d_tmp & m_tmp) | (reg_ispctrl1.field.cce & ~m_tmp);

			// Lsb: 6, Len: 1, [6] Reserved.
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000001;
			reg_ispctrl1.field.lne = (d_tmp & m_tmp) | (reg_ispctrl1.field.lne & ~m_tmp);

			// Lsb: 7, Len: 1, [7] Sharpening and Edge Enhancement enable.
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_ispctrl1.field.ee = (d_tmp & m_tmp) | (reg_ispctrl1.field.ee & ~m_tmp);

			// Lsb: 8, Len: 1, [8] Hue, Saturation, Brightness, Contrast enable.
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000001;
			reg_ispctrl1.field.sce = (d_tmp & m_tmp) | (reg_ispctrl1.field.sce & ~m_tmp);

			// Lsb: 9, Len: 1, [9] Reserved.
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_ispctrl1.field.cae = (d_tmp & m_tmp) | (reg_ispctrl1.field.cae & ~m_tmp);

			// Lsb: 10, Len: 1, [10] Reserved.
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000001;
			reg_ispctrl1.field.pfe = (d_tmp & m_tmp) | (reg_ispctrl1.field.pfe & ~m_tmp);

			// Lsb: 11, Len: 1, [11] Reserved.
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_ispctrl1.field.nwcl = (d_tmp & m_tmp) | (reg_ispctrl1.field.nwcl & ~m_tmp);

			// Lsb: 12, Len: 1, [12] Reserved.
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000001;
			reg_ispctrl1.field.fwbg = (d_tmp & m_tmp) | (reg_ispctrl1.field.fwbg & ~m_tmp);

			// Lsb: 13, Len: 1, [13] Reserved.
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000001;
			reg_ispctrl1.field.nl2d = (d_tmp & m_tmp) | (reg_ispctrl1.field.nl2d & ~m_tmp);

			// Lsb: 14, Len: 1, [14] Reserved.
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000001;
			reg_ispctrl1.field.rwbg = (d_tmp & m_tmp) | (reg_ispctrl1.field.rwbg & ~m_tmp);

			// Lsb: 15, Len: 1, [15] Reserved.
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_ispctrl1.field.lute = (d_tmp & m_tmp) | (reg_ispctrl1.field.lute & ~m_tmp);

			// Lsb: 16, Len: 1, [16] Reserved.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000001;
			reg_ispctrl1.field.nwed = (d_tmp & m_tmp) | (reg_ispctrl1.field.nwed & ~m_tmp);

			// Lsb: 17, Len: 1, [17] BiYUV enable
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000001;
			reg_ispctrl1.field.biyuv = (d_tmp & m_tmp) | (reg_ispctrl1.field.biyuv & ~m_tmp);

			// Lsb: 18, Len: 1, [18] Reserved.
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_ispctrl1.field.ctm = (d_tmp & m_tmp) | (reg_ispctrl1.field.ctm & ~m_tmp);

			// Lsb: 19, Len: 1, [19] Y Curve  enable
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_ispctrl1.field.ycurve = (d_tmp & m_tmp) | (reg_ispctrl1.field.ycurve & ~m_tmp);

			// Lsb: 20, Len: 1, [20] Y Histogram enable
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000001;
			reg_ispctrl1.field.yhist = (d_tmp & m_tmp) | (reg_ispctrl1.field.yhist & ~m_tmp);

			// Lsb: 21, Len: 1, [21] CTC filter enable.
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000001;
			reg_ispctrl1.field.ctc = (d_tmp & m_tmp) | (reg_ispctrl1.field.ctc & ~m_tmp);

			// Lsb: 22, Len: 1, [22] DBC filter enable.
			d_tmp = (data >> 22); m_tmp = (mask >> 22) & 0x00000001;
			reg_ispctrl1.field.dbc = (d_tmp & m_tmp) | (reg_ispctrl1.field.dbc & ~m_tmp);

			// Lsb: 23, Len: 5, [27:23] 
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x0000001F;
			reg_ispctrl1.field.rsvd23 = (d_tmp & m_tmp) | (reg_ispctrl1.field.rsvd23 & ~m_tmp);

			// Lsb: 28, Len: 2, [29:28] This register defines the first component of image sensor array.
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x00000003;
			reg_ispctrl1.field.sat = (d_tmp & m_tmp) | (reg_ispctrl1.field.sat & ~m_tmp);
			break;

		case 0x0A0C:
			// Lsb: 0, Len: 13, [12:0] Active capture area width(xsize)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ifsz.field.w = (d_tmp & m_tmp) | (reg_ifsz.field.w & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ifsz.field.rsvd13 = (d_tmp & m_tmp) | (reg_ifsz.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Active capture area height(ysize)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ifsz.field.h = (d_tmp & m_tmp) | (reg_ifsz.field.h & ~m_tmp);

			// Lsb: 29, Len: 3, [31:29] 
			d_tmp = (data >> 29); m_tmp = (mask >> 29) & 0x00000007;
			reg_ifsz.field.rsvd29 = (d_tmp & m_tmp) | (reg_ifsz.field.rsvd29 & ~m_tmp);
			break;

		case 0x0A10:
			// Lsb: 0, Len: 10, [9:0] (0.PW.0 format)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ictc.field.mingt = (d_tmp & m_tmp) | (reg_ictc.field.mingt & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_ictc.field.rsvd10 = (d_tmp & m_tmp) | (reg_ictc.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] (0.PW.0 format)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ictc.field.maxgt = (d_tmp & m_tmp) | (reg_ictc.field.maxgt & ~m_tmp);

			// Lsb: 26, Len: 4, [29:26] 
			d_tmp = (data >> 26); m_tmp = (mask >> 26) & 0x0000000F;
			reg_ictc.field.rsvd26 = (d_tmp & m_tmp) | (reg_ictc.field.rsvd26 & ~m_tmp);

			// Lsb: 30, Len: 2, [31:30] GrGb filter mode
			d_tmp = (data >> 30); m_tmp = (mask >> 30) & 0x00000003;
			reg_ictc.field.gf_mode = (d_tmp & m_tmp) | (reg_ictc.field.gf_mode & ~m_tmp);
			break;

		case 0x0A14:
			// Lsb: 0, Len: 10, [9:0] (0.PW.0 format)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_idbc.field.badxt = (d_tmp & m_tmp) | (reg_idbc.field.badxt & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_idbc.field.rsvd10 = (d_tmp & m_tmp) | (reg_idbc.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] (0.PW.0 format)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_idbc.field.badgt = (d_tmp & m_tmp) | (reg_idbc.field.badgt & ~m_tmp);
			break;

		case 0x0A1C:
			// Lsb: 0, Len: 4, [3:0] HW_WIDTH=2**HV_WIDTH(0~3)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_icfam.field.hv_width = (d_tmp & m_tmp) | (reg_icfam.field.hv_width & ~m_tmp);

			// Lsb: 4, Len: 2, [5:4] Cross covariance weighting
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000003;
			reg_icfam.field.cross_cov = (d_tmp & m_tmp) | (reg_icfam.field.cross_cov & ~m_tmp);
			break;

		case 0x0A30:
			// Lsb: 0, Len: 11, [10:0] Chroma Magnitude Amplification Base (Format: 0.3.8.)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_isat0.field.cmab = (d_tmp & m_tmp) | (reg_isat0.field.cmab & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_isat0.field.rsvd11 = (d_tmp & m_tmp) | (reg_isat0.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Chroma Magnitude Amplification Delta (Format 1.3.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_isat0.field.cmmd = (d_tmp & m_tmp) | (reg_isat0.field.cmmd & ~m_tmp);
			break;

		case 0x0A34:
			// Lsb: 0, Len: 11, [10:0] Chroma Magnitude Base, Format: 0.11.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_isat1.field.cmb = (d_tmp & m_tmp) | (reg_isat1.field.cmb & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_isat1.field.rsvd11 = (d_tmp & m_tmp) | (reg_isat1.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Chroma Magnitude Delta, Format: 1.11.0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_isat1.field.cmd = (d_tmp & m_tmp) | (reg_isat1.field.cmd & ~m_tmp);
			break;

		case 0x0A38:
			// Lsb: 0, Len: 11, [10:0] U offset, Format: 1.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_isat2.field.uoff = (d_tmp & m_tmp) | (reg_isat2.field.uoff & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_isat2.field.rsvd11 = (d_tmp & m_tmp) | (reg_isat2.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] V offset
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_isat2.field.voff = (d_tmp & m_tmp) | (reg_isat2.field.voff & ~m_tmp);
			break;

		case 0x0A3C:
			// Lsb: 0, Len: 9, [8:0] COS hue factor, Hue adjustment rotation factor. Format: 0.1.8
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_isat3.field.cos = (d_tmp & m_tmp) | (reg_isat3.field.cos & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_isat3.field.rsvd9 = (d_tmp & m_tmp) | (reg_isat3.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] SIN hue factor,Hue adjustment rotation factor. Format: 1.1.8
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_isat3.field.sin = (d_tmp & m_tmp) | (reg_isat3.field.sin & ~m_tmp);
			break;

		case 0x0A40:
			// Lsb: 0, Len: 4, [3:0] Chroma Magnitude Scaling Factor
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_isat4.field.cmsf = (d_tmp & m_tmp) | (reg_isat4.field.cmsf & ~m_tmp);
			break;

		case 0x0A50:
			// Lsb: 0, Len: 1, [0] Shadow update enable
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ieshd.field.ud = (d_tmp & m_tmp) | (reg_ieshd.field.ud & ~m_tmp);

			// Lsb: 1, Len: 1, [1] Shadow update mode
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_ieshd.field.udm = (d_tmp & m_tmp) | (reg_ieshd.field.udm & ~m_tmp);
			break;

		case 0x0A54:
			// Lsb: 0, Len: 10, [9:0] This register specifies the minimum input Y value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_iyadj0.field.yimin = (d_tmp & m_tmp) | (reg_iyadj0.field.yimin & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_iyadj0.field.rsvd10 = (d_tmp & m_tmp) | (reg_iyadj0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] This register specifies the ratio of Y output range to input range. Format: 0.4.10
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_iyadj0.field.yoir = (d_tmp & m_tmp) | (reg_iyadj0.field.yoir & ~m_tmp);
			break;

		case 0x0A58:
			// Lsb: 0, Len: 10, [9:0] This register specifies the minimum output Y value. Format 0.10.0.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_iyadj1.field.yomin = (d_tmp & m_tmp) | (reg_iyadj1.field.yomin & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_iyadj1.field.rsvd10 = (d_tmp & m_tmp) | (reg_iyadj1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] This register specifies the maximum output Y value. Format: 0.10.0.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_iyadj1.field.yomax = (d_tmp & m_tmp) | (reg_iyadj1.field.yomax & ~m_tmp);
			break;

		case 0x0A80:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_uoay.field.rsvd0 = (d_tmp & m_tmp) | (reg_uoay.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Base address in QWORD (64bit) boundary
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_uoay.field.sad = (d_tmp & m_tmp) | (reg_uoay.field.sad & ~m_tmp);
			break;

		case 0x0A84:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_uoauv.field.rsvd0 = (d_tmp & m_tmp) | (reg_uoauv.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Base address in QWORD (64bit) boundary
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_uoauv.field.sad = (d_tmp & m_tmp) | (reg_uoauv.field.sad & ~m_tmp);
			break;

		case 0x0A88:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_uos.field.rsvd0 = (d_tmp & m_tmp) | (reg_uos.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 10, [12:3] Image stride QWORD (64bit) granularity
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x000003FF;
			reg_uos.field.sd = (d_tmp & m_tmp) | (reg_uos.field.sd & ~m_tmp);
			break;

		case 0x0A8C:
			// Lsb: 0, Len: 5, [4:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_uopgm.field.rsvd0 = (d_tmp & m_tmp) | (reg_uopgm.field.rsvd0 & ~m_tmp);

			// Lsb: 5, Len: 1, [5] UO, SS0, and SS1 output UV order
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_uopgm.field.nv21 = (d_tmp & m_tmp) | (reg_uopgm.field.nv21 & ~m_tmp);
			break;

		case 0x0A90:
			// Lsb: 0, Len: 8, [7:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_uoaxi.field.rsvd0 = (d_tmp & m_tmp) | (reg_uoaxi.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] Reference image AXI write ID
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_uoaxi.field.refwid = (d_tmp & m_tmp) | (reg_uoaxi.field.refwid & ~m_tmp);
			break;

		case 0x0A94:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_ss0ay.field.rsvd0 = (d_tmp & m_tmp) | (reg_ss0ay.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Base address in QWORD (64bit) boundary
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_ss0ay.field.sad = (d_tmp & m_tmp) | (reg_ss0ay.field.sad & ~m_tmp);
			break;

		case 0x0A98:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_ss0auv.field.rsvd0 = (d_tmp & m_tmp) | (reg_ss0auv.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Base address in QWORD (64bit) boundary
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_ss0auv.field.sad = (d_tmp & m_tmp) | (reg_ss0auv.field.sad & ~m_tmp);
			break;

		case 0x0A9C:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_ss0s.field.rsvd0 = (d_tmp & m_tmp) | (reg_ss0s.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 10, [12:3] Image stride QWORD (64bit) granularity
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x000003FF;
			reg_ss0s.field.sd = (d_tmp & m_tmp) | (reg_ss0s.field.sd & ~m_tmp);
			break;

		case 0x0AA0:
			// Lsb: 0, Len: 2, [1:0] Scaling mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_ss0hf.field.sm = (d_tmp & m_tmp) | (reg_ss0hf.field.sm & ~m_tmp);

			// Lsb: 2, Len: 14, [15:2] Reserved
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00003FFF;
			reg_ss0hf.field.rsvd2 = (d_tmp & m_tmp) | (reg_ss0hf.field.rsvd2 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Scaling factor (format 0.0.12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_ss0hf.field.sf = (d_tmp & m_tmp) | (reg_ss0hf.field.sf & ~m_tmp);
			break;

		case 0x0AA4:
			// Lsb: 0, Len: 2, [1:0] Scaling mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_ss0vf.field.sm = (d_tmp & m_tmp) | (reg_ss0vf.field.sm & ~m_tmp);

			// Lsb: 2, Len: 14, [15:2] Reserved
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00003FFF;
			reg_ss0vf.field.rsvd2 = (d_tmp & m_tmp) | (reg_ss0vf.field.rsvd2 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Scaling factor (format 0.0.12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_ss0vf.field.sf = (d_tmp & m_tmp) | (reg_ss0vf.field.sf & ~m_tmp);
			break;

		case 0x0AA8:
			// Lsb: 0, Len: 13, [12:0] Output image height
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ss0iw.field.h = (d_tmp & m_tmp) | (reg_ss0iw.field.h & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] Reserved
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ss0iw.field.rsvd13 = (d_tmp & m_tmp) | (reg_ss0iw.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Output image width
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ss0iw.field.w = (d_tmp & m_tmp) | (reg_ss0iw.field.w & ~m_tmp);
			break;

		case 0x0AAC:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_ss1ay.field.rsvd0 = (d_tmp & m_tmp) | (reg_ss1ay.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Base address in QWORD (64bit) boundary
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_ss1ay.field.sad = (d_tmp & m_tmp) | (reg_ss1ay.field.sad & ~m_tmp);
			break;

		case 0x0AB0:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_ss1auv.field.rsvd0 = (d_tmp & m_tmp) | (reg_ss1auv.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Base address in QWORD (64bit) boundary
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_ss1auv.field.sad = (d_tmp & m_tmp) | (reg_ss1auv.field.sad & ~m_tmp);
			break;

		case 0x0AB4:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_ss1s.field.rsvd0 = (d_tmp & m_tmp) | (reg_ss1s.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 10, [12:3] Image stride QWORD (64bit) granularity
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x000003FF;
			reg_ss1s.field.sd = (d_tmp & m_tmp) | (reg_ss1s.field.sd & ~m_tmp);
			break;

		case 0x0AB8:
			// Lsb: 0, Len: 2, [1:0] Scaling mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_ss1hf.field.sm = (d_tmp & m_tmp) | (reg_ss1hf.field.sm & ~m_tmp);

			// Lsb: 2, Len: 14, [15:2] Reserved
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00003FFF;
			reg_ss1hf.field.rsvd2 = (d_tmp & m_tmp) | (reg_ss1hf.field.rsvd2 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Scaling factor (format 0.0.12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_ss1hf.field.sf = (d_tmp & m_tmp) | (reg_ss1hf.field.sf & ~m_tmp);
			break;

		case 0x0ABC:
			// Lsb: 0, Len: 2, [1:0] Scaling mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_ss1vf.field.sm = (d_tmp & m_tmp) | (reg_ss1vf.field.sm & ~m_tmp);

			// Lsb: 2, Len: 14, [15:2] Reserved
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00003FFF;
			reg_ss1vf.field.rsvd2 = (d_tmp & m_tmp) | (reg_ss1vf.field.rsvd2 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] Scaling factor (format 0.0.12)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_ss1vf.field.sf = (d_tmp & m_tmp) | (reg_ss1vf.field.sf & ~m_tmp);
			break;

		case 0x0AC0:
			// Lsb: 0, Len: 13, [12:0] Output image height
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ss1iw.field.h = (d_tmp & m_tmp) | (reg_ss1iw.field.h & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] Reserved
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ss1iw.field.rsvd13 = (d_tmp & m_tmp) | (reg_ss1iw.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Output image width
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ss1iw.field.w = (d_tmp & m_tmp) | (reg_ss1iw.field.w & ~m_tmp);
			break;

		case 0x0AC4:
			// Lsb: 0, Len: 8, [7:0] SS0 image AXI write ID
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ssaxi.field.ss0wid = (d_tmp & m_tmp) | (reg_ssaxi.field.ss0wid & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] SS1 image AXI write ID
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_ssaxi.field.ss1wid = (d_tmp & m_tmp) | (reg_ssaxi.field.ss1wid & ~m_tmp);
			break;

		case 0x0B20:
			// Lsb: 0, Len: 16, [15:0] The width of image window size
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_itiiwsr.field.wsize = (d_tmp & m_tmp) | (reg_itiiwsr.field.wsize & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] The height of image window size
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_itiiwsr.field.hsize = (d_tmp & m_tmp) | (reg_itiiwsr.field.hsize & ~m_tmp);
			break;

		case 0x0B24:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwlsr.field.rsvd0 = (d_tmp & m_tmp) | (reg_itidwlsr.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 20, [22:3] The line stride of the next line address in DRAM buffer (8-byte alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x000FFFFF;
			reg_itidwlsr.field.wstride = (d_tmp & m_tmp) | (reg_itidwlsr.field.wstride & ~m_tmp);
			break;

		case 0x0B28:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwysar.field.rsvd0 = (d_tmp & m_tmp) | (reg_itidwysar.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Data buffer start address for writing RAW/Y plane in DRAM buffer (8-byte alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwysar.field.wyaddr = (d_tmp & m_tmp) | (reg_itidwysar.field.wyaddr & ~m_tmp);
			break;

		case 0x0B2C:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwusar.field.rsvd0 = (d_tmp & m_tmp) | (reg_itidwusar.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Data buffer start address for writing UV plane in DRAM buffer (8-byte alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwusar.field.wuvaddr = (d_tmp & m_tmp) | (reg_itidwusar.field.wuvaddr & ~m_tmp);
			break;

		case 0x0B30:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrysar.field.rsvd0 = (d_tmp & m_tmp) | (reg_itidrysar.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Data buffer start address for reading RAW/Y plane in DRAM buffer (8-byte alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrysar.field.ryaddr = (d_tmp & m_tmp) | (reg_itidrysar.field.ryaddr & ~m_tmp);
			break;

		case 0x0B34:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrusar.field.rsvd0 = (d_tmp & m_tmp) | (reg_itidrusar.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Data buffer start address for reading UV plane in DRAM buffer (8-byte alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrusar.field.ruvaddr = (d_tmp & m_tmp) | (reg_itidrusar.field.ruvaddr & ~m_tmp);
			break;

		case 0x0B38:
			// Lsb: 0, Len: 3, [2:0] Data package format type
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itipdfr.field.wrformat = (d_tmp & m_tmp) | (reg_itipdfr.field.wrformat & ~m_tmp);

			// Lsb: 3, Len: 1, [3] RAW10bit format is changed to IMG ISP RAW 10 bit format (IMG 3 pack in a DW)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_itipdfr.field.imgispraw10 = (d_tmp & m_tmp) | (reg_itipdfr.field.imgispraw10 & ~m_tmp);

			// Lsb: 4, Len: 5, [8:4] The bit number of one RAW for data format is 3'h7 (first pixel offset)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000001F;
			reg_itipdfr.field.wrflexiblebit = (d_tmp & m_tmp) | (reg_itipdfr.field.wrflexiblebit & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] Reserved
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_itipdfr.field.rsvd9 = (d_tmp & m_tmp) | (reg_itipdfr.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 3, [18:16] Data package format type
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000007;
			reg_itipdfr.field.rdformat = (d_tmp & m_tmp) | (reg_itipdfr.field.rdformat & ~m_tmp);

			// Lsb: 19, Len: 1, [19] Disable UV line buffer function for YUV de-package flow.
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_itipdfr.field.rdlinebufoff = (d_tmp & m_tmp) | (reg_itipdfr.field.rdlinebufoff & ~m_tmp);

			// Lsb: 20, Len: 5, [24:20] The bit number of one RAW for data format is 3'h7 (first pixel offset)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000001F;
			reg_itipdfr.field.rdflexiblebit = (d_tmp & m_tmp) | (reg_itipdfr.field.rdflexiblebit & ~m_tmp);
			break;

		case 0x0B3C:
			// Lsb: 0, Len: 3, [2:0] Reserved
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrlsr.field.rsvd0 = (d_tmp & m_tmp) | (reg_itidrlsr.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 20, [22:3] The line stride of the next line address in DRAM buffer (8-byte alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x000FFFFF;
			reg_itidrlsr.field.rstride = (d_tmp & m_tmp) | (reg_itidrlsr.field.rstride & ~m_tmp);
			break;

		case 0x0B40:
			// Lsb: 0, Len: 1, [0] 1: The ISP tiling interface status is busy for writing processes
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_itibsr.field.wbusy = (d_tmp & m_tmp) | (reg_itibsr.field.wbusy & ~m_tmp);

			// Lsb: 1, Len: 1, [1] 1: The ISP tiling interface status is busy for reading processes
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_itibsr.field.rbusy = (d_tmp & m_tmp) | (reg_itibsr.field.rbusy & ~m_tmp);

			// Lsb: 2, Len: 30, [31:2] Reserved
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x3FFFFFFF;
			reg_itibsr.field.rsvd2 = (d_tmp & m_tmp) | (reg_itibsr.field.rsvd2 & ~m_tmp);
			break;

		case 0x0B44:
			// Lsb: 0, Len: 8, [7:0] The AXI ID of the Y AXI write controller
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_itiair.field.ywid = (d_tmp & m_tmp) | (reg_itiair.field.ywid & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] The AXI ID of the UV AXI write controller
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_itiair.field.uvwid = (d_tmp & m_tmp) | (reg_itiair.field.uvwid & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] The AXI ID of the Y AXI read controller
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_itiair.field.yrid = (d_tmp & m_tmp) | (reg_itiair.field.yrid & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] The AXI ID of the UV AXI read controller
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_itiair.field.uvrid = (d_tmp & m_tmp) | (reg_itiair.field.uvrid & ~m_tmp);
			break;

		case 0x0B48:
			// Lsb: 0, Len: 8, [7:0] The index of the selected module whose input will be selected from DRAM buffer
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_itidpsr.field.readindex = (d_tmp & m_tmp) | (reg_itidpsr.field.readindex & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] The index of the selected module whose output will be written into DRAM buffer
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_itidpsr.field.writeindex = (d_tmp & m_tmp) | (reg_itidpsr.field.writeindex & ~m_tmp);

			// Lsb: 16, Len: 1, [16] Enable the read function of the ITI interface from DRAM buffer
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000001;
			reg_itidpsr.field.readdram = (d_tmp & m_tmp) | (reg_itidpsr.field.readdram & ~m_tmp);

			// Lsb: 17, Len: 1, [17] Enable the write function of the ITI interface into DRAM buffer
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000001;
			reg_itidpsr.field.writedram = (d_tmp & m_tmp) | (reg_itidpsr.field.writedram & ~m_tmp);

			// Lsb: 18, Len: 1, [18] Enable the loop back self test where the write AXI controller obtains the input data from the AXI read controller
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_itidpsr.field.loopback = (d_tmp & m_tmp) | (reg_itidpsr.field.loopback & ~m_tmp);

			// Lsb: 19, Len: 1, [19] Enable the move data function from the reading address to the writing address. (move data directly from read to write, can be used for copying data)
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_itidpsr.field.movedramdata = (d_tmp & m_tmp) | (reg_itidpsr.field.movedramdata & ~m_tmp);

			// Lsb: 20, Len: 1, [20] Enable the independent  READ RVI signal function under  the normal  DRAM read mode.
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000001;
			reg_itidpsr.field.independentrdrvi = (d_tmp & m_tmp) | (reg_itidpsr.field.independentrdrvi & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] Reserved
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_itidpsr.field.rsvd21 = (d_tmp & m_tmp) | (reg_itidpsr.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 1, [24] Enable  YCrCb 420  NV21 Data format  in DRAM package for the Reading path
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x00000001;
			reg_itidpsr.field.rdnv21format = (d_tmp & m_tmp) | (reg_itidpsr.field.rdnv21format & ~m_tmp);

			// Lsb: 25, Len: 1, [25] Enable  YCrCb 420 NV21 Data format in DRAM package for the Writing path
			d_tmp = (data >> 25); m_tmp = (mask >> 25) & 0x00000001;
			reg_itidpsr.field.wrnv21format = (d_tmp & m_tmp) | (reg_itidpsr.field.wrnv21format & ~m_tmp);

			// Lsb: 26, Len: 6, [31:26] Reserved
			d_tmp = (data >> 26); m_tmp = (mask >> 26) & 0x0000003F;
			reg_itidpsr.field.rsvd26 = (d_tmp & m_tmp) | (reg_itidpsr.field.rsvd26 & ~m_tmp);
			break;

		case 0x0C00:
			// Lsb: 0, Len: 3, [2:0] [0.3.0], y channel yeWsa
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_dnyuv_yswr0.field.yswa = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.yswa & ~m_tmp);

			// Lsb: 3, Len: 1, [3] 
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_dnyuv_yswr0.field.rsvd3 = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.rsvd3 & ~m_tmp);

			// Lsb: 4, Len: 3, [6:4] [0.3.0], y channel yeWsb
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000007;
			reg_dnyuv_yswr0.field.yswb = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.yswb & ~m_tmp);

			// Lsb: 7, Len: 1, [7] 
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_dnyuv_yswr0.field.rsvd7 = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.rsvd7 & ~m_tmp);

			// Lsb: 8, Len: 3, [10:8] [0.3.0], y channel yeWsc
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000007;
			reg_dnyuv_yswr0.field.yswc = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.yswc & ~m_tmp);

			// Lsb: 11, Len: 1, [11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_dnyuv_yswr0.field.rsvd11 = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.rsvd11 & ~m_tmp);

			// Lsb: 12, Len: 3, [14:12] [0.3.0], y channel yeWsd
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000007;
			reg_dnyuv_yswr0.field.yswd = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.yswd & ~m_tmp);

			// Lsb: 15, Len: 1, [15] 
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_dnyuv_yswr0.field.rsvd15 = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.rsvd15 & ~m_tmp);

			// Lsb: 16, Len: 3, [18:16] [0.3.0], y channel yeWse
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000007;
			reg_dnyuv_yswr0.field.yswe = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.yswe & ~m_tmp);

			// Lsb: 19, Len: 1, [19] 
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_dnyuv_yswr0.field.rsvd19 = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.rsvd19 & ~m_tmp);

			// Lsb: 20, Len: 3, [22:20] [0.3.0], y channel yeWsf
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000007;
			reg_dnyuv_yswr0.field.yswf = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.yswf & ~m_tmp);

			// Lsb: 23, Len: 9, [31:23] 
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x000001FF;
			reg_dnyuv_yswr0.field.rsvd23 = (d_tmp & m_tmp) | (reg_dnyuv_yswr0.field.rsvd23 & ~m_tmp);
			break;

		case 0x0C04:
			// Lsb: 0, Len: 3, [2:0] [0.3.0], y channel yeWsg
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_dnyuv_yswr1.field.yswg = (d_tmp & m_tmp) | (reg_dnyuv_yswr1.field.yswg & ~m_tmp);

			// Lsb: 3, Len: 1, [3] 
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_dnyuv_yswr1.field.rsvd3 = (d_tmp & m_tmp) | (reg_dnyuv_yswr1.field.rsvd3 & ~m_tmp);

			// Lsb: 4, Len: 3, [6:4] [0.3.0], y channel yeWsh
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000007;
			reg_dnyuv_yswr1.field.yswh = (d_tmp & m_tmp) | (reg_dnyuv_yswr1.field.yswh & ~m_tmp);

			// Lsb: 7, Len: 1, [7] 
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_dnyuv_yswr1.field.rsvd7 = (d_tmp & m_tmp) | (reg_dnyuv_yswr1.field.rsvd7 & ~m_tmp);

			// Lsb: 8, Len: 3, [10:8] [0.3.0], y channel yeWsi
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000007;
			reg_dnyuv_yswr1.field.yswi = (d_tmp & m_tmp) | (reg_dnyuv_yswr1.field.yswi & ~m_tmp);

			// Lsb: 11, Len: 1, [11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_dnyuv_yswr1.field.rsvd11 = (d_tmp & m_tmp) | (reg_dnyuv_yswr1.field.rsvd11 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.3.0], y channel yeWsj
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_dnyuv_yswr1.field.yswj = (d_tmp & m_tmp) | (reg_dnyuv_yswr1.field.yswj & ~m_tmp);
			break;

		case 0x0C08:
			// Lsb: 0, Len: 3, [2:0] [0.3.0], uv channel ceWsa
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_dnyuv_cswr0.field.cswa = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.cswa & ~m_tmp);

			// Lsb: 3, Len: 1, [3] 
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_dnyuv_cswr0.field.rsvd3 = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.rsvd3 & ~m_tmp);

			// Lsb: 4, Len: 3, [6:4] [0.3.0], uv channel ceWsb
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000007;
			reg_dnyuv_cswr0.field.cswb = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.cswb & ~m_tmp);

			// Lsb: 7, Len: 1, [7] 
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_dnyuv_cswr0.field.rsvd7 = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.rsvd7 & ~m_tmp);

			// Lsb: 8, Len: 3, [10:8] [0.3.0], uv channel ceWsc
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000007;
			reg_dnyuv_cswr0.field.cswc = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.cswc & ~m_tmp);

			// Lsb: 11, Len: 1, [11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_dnyuv_cswr0.field.rsvd11 = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.rsvd11 & ~m_tmp);

			// Lsb: 12, Len: 3, [14:12] [0.3.0], uv channel ceWsd
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000007;
			reg_dnyuv_cswr0.field.cswd = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.cswd & ~m_tmp);

			// Lsb: 15, Len: 1, [15] 
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_dnyuv_cswr0.field.rsvd15 = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.rsvd15 & ~m_tmp);

			// Lsb: 16, Len: 3, [18:16] [0.3.0], uv channel ceWse
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000007;
			reg_dnyuv_cswr0.field.cswe = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.cswe & ~m_tmp);

			// Lsb: 19, Len: 1, [19] 
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_dnyuv_cswr0.field.rsvd19 = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.rsvd19 & ~m_tmp);

			// Lsb: 20, Len: 3, [22:20] [0.3.0], uv channel ceWsf
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000007;
			reg_dnyuv_cswr0.field.cswf = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.cswf & ~m_tmp);

			// Lsb: 23, Len: 9, [31:23] 
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x000001FF;
			reg_dnyuv_cswr0.field.rsvd23 = (d_tmp & m_tmp) | (reg_dnyuv_cswr0.field.rsvd23 & ~m_tmp);
			break;

		case 0x0C0C:
			// Lsb: 0, Len: 3, [2:0] [0.3.0], uv channel ceWsg
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_dnyuv_cswr1.field.cswg = (d_tmp & m_tmp) | (reg_dnyuv_cswr1.field.cswg & ~m_tmp);

			// Lsb: 3, Len: 1, [3] 
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_dnyuv_cswr1.field.rsvd3 = (d_tmp & m_tmp) | (reg_dnyuv_cswr1.field.rsvd3 & ~m_tmp);

			// Lsb: 4, Len: 3, [6:4] [0.3.0], uv channel ceWsh
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000007;
			reg_dnyuv_cswr1.field.cswh = (d_tmp & m_tmp) | (reg_dnyuv_cswr1.field.cswh & ~m_tmp);

			// Lsb: 7, Len: 1, [7] 
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_dnyuv_cswr1.field.rsvd7 = (d_tmp & m_tmp) | (reg_dnyuv_cswr1.field.rsvd7 & ~m_tmp);

			// Lsb: 8, Len: 3, [10:8] [0.3.0], uv channel ceWsi
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000007;
			reg_dnyuv_cswr1.field.cswi = (d_tmp & m_tmp) | (reg_dnyuv_cswr1.field.cswi & ~m_tmp);

			// Lsb: 11, Len: 1, [11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_dnyuv_cswr1.field.rsvd11 = (d_tmp & m_tmp) | (reg_dnyuv_cswr1.field.rsvd11 & ~m_tmp);

			// Lsb: 12, Len: 3, [14:12] [0.3.0], uv channel ceWsj
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000007;
			reg_dnyuv_cswr1.field.cswj = (d_tmp & m_tmp) | (reg_dnyuv_cswr1.field.cswj & ~m_tmp);
			break;

		case 0x0C10:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_dnyuv_ydr0.field.yd0 = (d_tmp & m_tmp) | (reg_dnyuv_ydr0.field.yd0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_dnyuv_ydr0.field.rsvd10 = (d_tmp & m_tmp) | (reg_dnyuv_ydr0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_dnyuv_ydr0.field.yd1 = (d_tmp & m_tmp) | (reg_dnyuv_ydr0.field.yd1 & ~m_tmp);
			break;

		case 0x0C14:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_dnyuv_ydr1.field.yd2 = (d_tmp & m_tmp) | (reg_dnyuv_ydr1.field.yd2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_dnyuv_ydr1.field.rsvd10 = (d_tmp & m_tmp) | (reg_dnyuv_ydr1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_dnyuv_ydr1.field.yd3 = (d_tmp & m_tmp) | (reg_dnyuv_ydr1.field.yd3 & ~m_tmp);
			break;

		case 0x0C18:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_dnyuv_ydr2.field.yd4 = (d_tmp & m_tmp) | (reg_dnyuv_ydr2.field.yd4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_dnyuv_ydr2.field.rsvd10 = (d_tmp & m_tmp) | (reg_dnyuv_ydr2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_dnyuv_ydr2.field.yd5 = (d_tmp & m_tmp) | (reg_dnyuv_ydr2.field.yd5 & ~m_tmp);
			break;

		case 0x0C1C:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_dnyuv_cdr0.field.cd0 = (d_tmp & m_tmp) | (reg_dnyuv_cdr0.field.cd0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_dnyuv_cdr0.field.rsvd10 = (d_tmp & m_tmp) | (reg_dnyuv_cdr0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_dnyuv_cdr0.field.cd1 = (d_tmp & m_tmp) | (reg_dnyuv_cdr0.field.cd1 & ~m_tmp);
			break;

		case 0x0C20:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_dnyuv_cdr1.field.cd2 = (d_tmp & m_tmp) | (reg_dnyuv_cdr1.field.cd2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_dnyuv_cdr1.field.rsvd10 = (d_tmp & m_tmp) | (reg_dnyuv_cdr1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_dnyuv_cdr1.field.cd3 = (d_tmp & m_tmp) | (reg_dnyuv_cdr1.field.cd3 & ~m_tmp);
			break;

		case 0x0C24:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_dnyuv_cdr2.field.cd4 = (d_tmp & m_tmp) | (reg_dnyuv_cdr2.field.cd4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_dnyuv_cdr2.field.rsvd10 = (d_tmp & m_tmp) | (reg_dnyuv_cdr2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_dnyuv_cdr2.field.cd5 = (d_tmp & m_tmp) | (reg_dnyuv_cdr2.field.cd5 & ~m_tmp);
			break;

		case 0x0C40:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter , r1g1_1/smatrix11 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_0.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_0.field.ccm_m_dat & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_icamd_0.field.rsvd11 = (d_tmp & m_tmp) | (reg_icamd_0.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] Color matrix threshold denormalization factor.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_icamd_0.field.dnrm = (d_tmp & m_tmp) | (reg_icamd_0.field.dnrm & ~m_tmp);
			break;

		case 0x0C44:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter , r1g2_1/smatrix12 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_1.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_1.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C48:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r1g3_1/smatrix13 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_2.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_2.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C4C:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r2g1_1/smatrix21  [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_3.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_3.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C50:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r2g2_1/smatrix22  [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_4.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_4.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C54:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r2g3_1/smatrix23  [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_5.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_5.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C58:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r3g1_1/smatrix31  [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_6.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_6.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C5C:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r3g2_1/smatrix32  [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_7.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_7.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C60:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r3g3_1/smatrix33  [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_8.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_8.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C64:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, k1_1/sk1 [1.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_9.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_9.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C68:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, k2_1/sk2 [1.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_10.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_10.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C6C:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, k3_1/sk3 [1.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_11.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_11.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C70:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r1g1_0 /matrix11 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_12.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_12.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C74:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r1g2_0 /matrix12 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_13.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_13.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C78:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, r1g3_0 /matrix13 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_14.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_14.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C7C:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter,  r2g1_0 /matrix21 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_15.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_15.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C80:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter,  r2g2_0 /matrix22 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_16.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_16.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C84:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter,  r2g3_0 /matrix23 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_17.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_17.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C88:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter,  r3g1_0 /matrix31 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_18.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_18.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C8C:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter,  r3g2_0 /matrix32 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_19.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_19.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C90:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter,  r3g3_0 /matrix33 [1.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_20.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_20.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C94:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, k1_0/k1 [1.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_21.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_21.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C98:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, k2_0/k2 [1.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_22.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_22.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0C9C:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, k3_0/k3 [1.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_23.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_23.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0CA0:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, mdth [1.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_24.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_24.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0CA4:
			// Lsb: 0, Len: 11, [10:0] Color correction matrix parameter, mth1 [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_icamd_25.field.ccm_m_dat = (d_tmp & m_tmp) | (reg_icamd_25.field.ccm_m_dat & ~m_tmp);
			break;

		case 0x0CC8:
			// Lsb: 0, Len: 13, [12:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_yhist_cfg_0.field.yh_hstart = (d_tmp & m_tmp) | (reg_yhist_cfg_0.field.yh_hstart & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_yhist_cfg_0.field.rsvd13 = (d_tmp & m_tmp) | (reg_yhist_cfg_0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] 
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_yhist_cfg_0.field.yh_vstart = (d_tmp & m_tmp) | (reg_yhist_cfg_0.field.yh_vstart & ~m_tmp);
			break;

		case 0x0CCC:
			// Lsb: 0, Len: 13, [12:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_yhist_cfg_1.field.yh_width = (d_tmp & m_tmp) | (reg_yhist_cfg_1.field.yh_width & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_yhist_cfg_1.field.rsvd13 = (d_tmp & m_tmp) | (reg_yhist_cfg_1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] 
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_yhist_cfg_1.field.yh_height = (d_tmp & m_tmp) | (reg_yhist_cfg_1.field.yh_height & ~m_tmp);
			break;

		case 0x0CD0:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_yhist_cfg_2.field.yh_dec_etw = (d_tmp & m_tmp) | (reg_yhist_cfg_2.field.yh_dec_etw & ~m_tmp);

			// Lsb: 3, Len: 13, [15:3] 
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00001FFF;
			reg_yhist_cfg_2.field.rsvd3 = (d_tmp & m_tmp) | (reg_yhist_cfg_2.field.rsvd3 & ~m_tmp);

			// Lsb: 16, Len: 3, [18:16] 
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000007;
			reg_yhist_cfg_2.field.yh_dec_eth = (d_tmp & m_tmp) | (reg_yhist_cfg_2.field.yh_dec_eth & ~m_tmp);
			break;

		case 0x0CD4:
			// Lsb: 0, Len: 32, [31:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_yhist_cfg_3.field.rsvd0 = (d_tmp & m_tmp) | (reg_yhist_cfg_3.field.rsvd0 & ~m_tmp);
			break;

		case 0x0CD8:
			// Lsb: 0, Len: 7, [6:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000007F;
			reg_yhist_cfg_4.field.rsvd0 = (d_tmp & m_tmp) | (reg_yhist_cfg_4.field.rsvd0 & ~m_tmp);

			// Lsb: 7, Len: 25, [31:7] Y histogram dumping base address(8x16byte align), need use Yhistogram frame_start generate interrupt & sync address
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x01FFFFFF;
			reg_yhist_cfg_4.field.base_adr = (d_tmp & m_tmp) | (reg_yhist_cfg_4.field.base_adr & ~m_tmp);
			break;

		case 0x0D00:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_0.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_0.field.acc & ~m_tmp);
			break;

		case 0x0D04:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_1.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_1.field.acc & ~m_tmp);
			break;

		case 0x0D08:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_2.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_2.field.acc & ~m_tmp);
			break;

		case 0x0D0C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_3.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_3.field.acc & ~m_tmp);
			break;

		case 0x0D10:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_4.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_4.field.acc & ~m_tmp);
			break;

		case 0x0D14:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_5.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_5.field.acc & ~m_tmp);
			break;

		case 0x0D18:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_6.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_6.field.acc & ~m_tmp);
			break;

		case 0x0D1C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_7.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_7.field.acc & ~m_tmp);
			break;

		case 0x0D20:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_8.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_8.field.acc & ~m_tmp);
			break;

		case 0x0D24:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_9.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_9.field.acc & ~m_tmp);
			break;

		case 0x0D28:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_10.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_10.field.acc & ~m_tmp);
			break;

		case 0x0D2C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_11.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_11.field.acc & ~m_tmp);
			break;

		case 0x0D30:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_12.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_12.field.acc & ~m_tmp);
			break;

		case 0x0D34:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_13.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_13.field.acc & ~m_tmp);
			break;

		case 0x0D38:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_14.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_14.field.acc & ~m_tmp);
			break;

		case 0x0D3C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_15.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_15.field.acc & ~m_tmp);
			break;

		case 0x0D40:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_16.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_16.field.acc & ~m_tmp);
			break;

		case 0x0D44:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_17.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_17.field.acc & ~m_tmp);
			break;

		case 0x0D48:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_18.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_18.field.acc & ~m_tmp);
			break;

		case 0x0D4C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_19.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_19.field.acc & ~m_tmp);
			break;

		case 0x0D50:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_20.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_20.field.acc & ~m_tmp);
			break;

		case 0x0D54:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_21.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_21.field.acc & ~m_tmp);
			break;

		case 0x0D58:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_22.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_22.field.acc & ~m_tmp);
			break;

		case 0x0D5C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_23.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_23.field.acc & ~m_tmp);
			break;

		case 0x0D60:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_24.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_24.field.acc & ~m_tmp);
			break;

		case 0x0D64:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_25.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_25.field.acc & ~m_tmp);
			break;

		case 0x0D68:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_26.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_26.field.acc & ~m_tmp);
			break;

		case 0x0D6C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_27.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_27.field.acc & ~m_tmp);
			break;

		case 0x0D70:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_28.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_28.field.acc & ~m_tmp);
			break;

		case 0x0D74:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_29.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_29.field.acc & ~m_tmp);
			break;

		case 0x0D78:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_30.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_30.field.acc & ~m_tmp);
			break;

		case 0x0D7C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_31.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_31.field.acc & ~m_tmp);
			break;

		case 0x0D80:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_32.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_32.field.acc & ~m_tmp);
			break;

		case 0x0D84:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_33.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_33.field.acc & ~m_tmp);
			break;

		case 0x0D88:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_34.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_34.field.acc & ~m_tmp);
			break;

		case 0x0D8C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_35.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_35.field.acc & ~m_tmp);
			break;

		case 0x0D90:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_36.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_36.field.acc & ~m_tmp);
			break;

		case 0x0D94:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_37.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_37.field.acc & ~m_tmp);
			break;

		case 0x0D98:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_38.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_38.field.acc & ~m_tmp);
			break;

		case 0x0D9C:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_39.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_39.field.acc & ~m_tmp);
			break;

		case 0x0DA0:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_40.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_40.field.acc & ~m_tmp);
			break;

		case 0x0DA4:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_41.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_41.field.acc & ~m_tmp);
			break;

		case 0x0DA8:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_42.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_42.field.acc & ~m_tmp);
			break;

		case 0x0DAC:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_43.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_43.field.acc & ~m_tmp);
			break;

		case 0x0DB0:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_44.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_44.field.acc & ~m_tmp);
			break;

		case 0x0DB4:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_45.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_45.field.acc & ~m_tmp);
			break;

		case 0x0DB8:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_46.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_46.field.acc & ~m_tmp);
			break;

		case 0x0DBC:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_47.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_47.field.acc & ~m_tmp);
			break;

		case 0x0DC0:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_48.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_48.field.acc & ~m_tmp);
			break;

		case 0x0DC4:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_49.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_49.field.acc & ~m_tmp);
			break;

		case 0x0DC8:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_50.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_50.field.acc & ~m_tmp);
			break;

		case 0x0DCC:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_51.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_51.field.acc & ~m_tmp);
			break;

		case 0x0DD0:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_52.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_52.field.acc & ~m_tmp);
			break;

		case 0x0DD4:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_53.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_53.field.acc & ~m_tmp);
			break;

		case 0x0DD8:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_54.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_54.field.acc & ~m_tmp);
			break;

		case 0x0DDC:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_55.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_55.field.acc & ~m_tmp);
			break;

		case 0x0DE0:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_56.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_56.field.acc & ~m_tmp);
			break;

		case 0x0DE4:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_57.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_57.field.acc & ~m_tmp);
			break;

		case 0x0DE8:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_58.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_58.field.acc & ~m_tmp);
			break;

		case 0x0DEC:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_59.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_59.field.acc & ~m_tmp);
			break;

		case 0x0DF0:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_60.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_60.field.acc & ~m_tmp);
			break;

		case 0x0DF4:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_61.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_61.field.acc & ~m_tmp);
			break;

		case 0x0DF8:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_62.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_62.field.acc & ~m_tmp);
			break;

		case 0x0DFC:
			// Lsb: 0, Len: 18, [17:0] Y histogram return data
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_yhist_acc_63.field.acc = (d_tmp & m_tmp) | (reg_yhist_acc_63.field.acc & ~m_tmp);
			break;

		case 0x0E00:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_0.field.gval = (d_tmp & m_tmp) | (reg_igrval_0.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_0.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.[1.4.11]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_0.field.sgval = (d_tmp & m_tmp) | (reg_igrval_0.field.sgval & ~m_tmp);
			break;

		case 0x0E04:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_1.field.gval = (d_tmp & m_tmp) | (reg_igrval_1.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_1.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.[1.4.11]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_1.field.sgval = (d_tmp & m_tmp) | (reg_igrval_1.field.sgval & ~m_tmp);
			break;

		case 0x0E08:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_2.field.gval = (d_tmp & m_tmp) | (reg_igrval_2.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_2.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.[1.4.11]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_2.field.sgval = (d_tmp & m_tmp) | (reg_igrval_2.field.sgval & ~m_tmp);
			break;

		case 0x0E0C:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_3.field.gval = (d_tmp & m_tmp) | (reg_igrval_3.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_3.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_3.field.sgval = (d_tmp & m_tmp) | (reg_igrval_3.field.sgval & ~m_tmp);
			break;

		case 0x0E10:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_4.field.gval = (d_tmp & m_tmp) | (reg_igrval_4.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_4.field.sgval = (d_tmp & m_tmp) | (reg_igrval_4.field.sgval & ~m_tmp);
			break;

		case 0x0E14:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_5.field.gval = (d_tmp & m_tmp) | (reg_igrval_5.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_5.field.sgval = (d_tmp & m_tmp) | (reg_igrval_5.field.sgval & ~m_tmp);
			break;

		case 0x0E18:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_6.field.gval = (d_tmp & m_tmp) | (reg_igrval_6.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_6.field.sgval = (d_tmp & m_tmp) | (reg_igrval_6.field.sgval & ~m_tmp);
			break;

		case 0x0E1C:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_7.field.gval = (d_tmp & m_tmp) | (reg_igrval_7.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_7.field.sgval = (d_tmp & m_tmp) | (reg_igrval_7.field.sgval & ~m_tmp);
			break;

		case 0x0E20:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_8.field.gval = (d_tmp & m_tmp) | (reg_igrval_8.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_8.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_8.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_8.field.sgval = (d_tmp & m_tmp) | (reg_igrval_8.field.sgval & ~m_tmp);
			break;

		case 0x0E24:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_9.field.gval = (d_tmp & m_tmp) | (reg_igrval_9.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_9.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_9.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_9.field.sgval = (d_tmp & m_tmp) | (reg_igrval_9.field.sgval & ~m_tmp);
			break;

		case 0x0E28:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_10.field.gval = (d_tmp & m_tmp) | (reg_igrval_10.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_10.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_10.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_10.field.sgval = (d_tmp & m_tmp) | (reg_igrval_10.field.sgval & ~m_tmp);
			break;

		case 0x0E2C:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_11.field.gval = (d_tmp & m_tmp) | (reg_igrval_11.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_11.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_11.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_11.field.sgval = (d_tmp & m_tmp) | (reg_igrval_11.field.sgval & ~m_tmp);
			break;

		case 0x0E30:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_12.field.gval = (d_tmp & m_tmp) | (reg_igrval_12.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_12.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_12.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_12.field.sgval = (d_tmp & m_tmp) | (reg_igrval_12.field.sgval & ~m_tmp);
			break;

		case 0x0E34:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_13.field.gval = (d_tmp & m_tmp) | (reg_igrval_13.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_13.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_13.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_13.field.sgval = (d_tmp & m_tmp) | (reg_igrval_13.field.sgval & ~m_tmp);
			break;

		case 0x0E38:
			// Lsb: 0, Len: 10, [9:0] RGB gamma value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_igrval_14.field.gval = (d_tmp & m_tmp) | (reg_igrval_14.field.gval & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_igrval_14.field.rsvd10 = (d_tmp & m_tmp) | (reg_igrval_14.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] RGB gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_14.field.sgval = (d_tmp & m_tmp) | (reg_igrval_14.field.sgval & ~m_tmp);
			break;

		case 0x0E40:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_0.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_0.field.csc_m & ~m_tmp);
			break;

		case 0x0E44:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_1.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_1.field.csc_m & ~m_tmp);
			break;

		case 0x0E48:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_2.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_2.field.csc_m & ~m_tmp);
			break;

		case 0x0E4C:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_3.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_3.field.csc_m & ~m_tmp);
			break;

		case 0x0E50:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_4.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_4.field.csc_m & ~m_tmp);
			break;

		case 0x0E54:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_5.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_5.field.csc_m & ~m_tmp);
			break;

		case 0x0E58:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_6.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_6.field.csc_m & ~m_tmp);
			break;

		case 0x0E5C:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_7.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_7.field.csc_m & ~m_tmp);
			break;

		case 0x0E60:
			// Lsb: 0, Len: 9, [8:0] The 3x3 color conversion matrix coefficient M(x, y) register. [1.0.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_icconv_8.field.csc_m = (d_tmp & m_tmp) | (reg_icconv_8.field.csc_m & ~m_tmp);
			break;

		case 0x0E80:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_0.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_0.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight, Format: 0.4.0.
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_0.field.w = (d_tmp & m_tmp) | (reg_ishrp1_0.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_0.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_0.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level, Format: 0.10.0.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_0.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_0.field.diff & ~m_tmp);
			break;

		case 0x0E84:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_1.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_1.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_1.field.w = (d_tmp & m_tmp) | (reg_ishrp1_1.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_1.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_1.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_1.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_1.field.diff & ~m_tmp);
			break;

		case 0x0E88:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_2.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_2.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_2.field.w = (d_tmp & m_tmp) | (reg_ishrp1_2.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_2.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_2.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_2.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_2.field.diff & ~m_tmp);
			break;

		case 0x0E8C:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_3.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_3.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_3.field.w = (d_tmp & m_tmp) | (reg_ishrp1_3.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_3.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_3.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_3.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_3.field.diff & ~m_tmp);
			break;

		case 0x0E90:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_4.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_4.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_4.field.w = (d_tmp & m_tmp) | (reg_ishrp1_4.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_4.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_4.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_4.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_4.field.diff & ~m_tmp);
			break;

		case 0x0E94:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_5.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_5.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_5.field.w = (d_tmp & m_tmp) | (reg_ishrp1_5.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_5.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_5.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_5.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_5.field.diff & ~m_tmp);
			break;

		case 0x0E98:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_6.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_6.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_6.field.w = (d_tmp & m_tmp) | (reg_ishrp1_6.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_6.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_6.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_6.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_6.field.diff & ~m_tmp);
			break;

		case 0x0E9C:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_7.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_7.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_7.field.w = (d_tmp & m_tmp) | (reg_ishrp1_7.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_7.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_7.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Edge amplification delta level
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_ishrp1_7.field.diff = (d_tmp & m_tmp) | (reg_ishrp1_7.field.diff & ~m_tmp);
			break;

		case 0x0EA0:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_8.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_8.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_8.field.w = (d_tmp & m_tmp) | (reg_ishrp1_8.field.w & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_ishrp1_8.field.rsvd12 = (d_tmp & m_tmp) | (reg_ishrp1_8.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] LPFF, [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ishrp1_8.field.lpff = (d_tmp & m_tmp) | (reg_ishrp1_8.field.lpff & ~m_tmp);
			break;

		case 0x0EA4:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_9.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_9.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_9.field.w = (d_tmp & m_tmp) | (reg_ishrp1_9.field.w & ~m_tmp);
			break;

		case 0x0EA8:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_10.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_10.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_10.field.w = (d_tmp & m_tmp) | (reg_ishrp1_10.field.w & ~m_tmp);
			break;

		case 0x0EAC:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_11.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_11.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_11.field.w = (d_tmp & m_tmp) | (reg_ishrp1_11.field.w & ~m_tmp);
			break;

		case 0x0EB0:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_12.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_12.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_12.field.w = (d_tmp & m_tmp) | (reg_ishrp1_12.field.w & ~m_tmp);
			break;

		case 0x0EB4:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_13.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_13.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_13.field.w = (d_tmp & m_tmp) | (reg_ishrp1_13.field.w & ~m_tmp);
			break;

		case 0x0EB8:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_ishrp1_14.field.rsvd0 = (d_tmp & m_tmp) | (reg_ishrp1_14.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] Sharpening filter weight
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_ishrp1_14.field.w = (d_tmp & m_tmp) | (reg_ishrp1_14.field.w & ~m_tmp);
			break;

		case 0x0EBC:
			// Lsb: 0, Len: 21, [20:0] Amplification factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x001FFFFF;
			reg_ishrp2_0.field.s = (d_tmp & m_tmp) | (reg_ishrp2_0.field.s & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_ishrp2_0.field.rsvd21 = (d_tmp & m_tmp) | (reg_ishrp2_0.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 7, [30:24] Amplification factor
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000007F;
			reg_ishrp2_0.field.f = (d_tmp & m_tmp) | (reg_ishrp2_0.field.f & ~m_tmp);
			break;

		case 0x0EC0:
			// Lsb: 0, Len: 21, [20:0] Amplification factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x001FFFFF;
			reg_ishrp2_1.field.s = (d_tmp & m_tmp) | (reg_ishrp2_1.field.s & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_ishrp2_1.field.rsvd21 = (d_tmp & m_tmp) | (reg_ishrp2_1.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 7, [30:24] Amplification factor
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000007F;
			reg_ishrp2_1.field.f = (d_tmp & m_tmp) | (reg_ishrp2_1.field.f & ~m_tmp);
			break;

		case 0x0EC4:
			// Lsb: 0, Len: 21, [20:0] Amplification factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x001FFFFF;
			reg_ishrp2_2.field.s = (d_tmp & m_tmp) | (reg_ishrp2_2.field.s & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_ishrp2_2.field.rsvd21 = (d_tmp & m_tmp) | (reg_ishrp2_2.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 7, [30:24] Amplification factor
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000007F;
			reg_ishrp2_2.field.f = (d_tmp & m_tmp) | (reg_ishrp2_2.field.f & ~m_tmp);
			break;

		case 0x0EC8:
			// Lsb: 0, Len: 21, [20:0] Amplification factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x001FFFFF;
			reg_ishrp2_3.field.s = (d_tmp & m_tmp) | (reg_ishrp2_3.field.s & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_ishrp2_3.field.rsvd21 = (d_tmp & m_tmp) | (reg_ishrp2_3.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 7, [30:24] Amplification factor
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000007F;
			reg_ishrp2_3.field.f = (d_tmp & m_tmp) | (reg_ishrp2_3.field.f & ~m_tmp);
			break;

		case 0x0ECC:
			// Lsb: 0, Len: 21, [20:0] Amplification factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x001FFFFF;
			reg_ishrp2_4.field.s = (d_tmp & m_tmp) | (reg_ishrp2_4.field.s & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_ishrp2_4.field.rsvd21 = (d_tmp & m_tmp) | (reg_ishrp2_4.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 7, [30:24] Amplification factor
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000007F;
			reg_ishrp2_4.field.f = (d_tmp & m_tmp) | (reg_ishrp2_4.field.f & ~m_tmp);
			break;

		case 0x0ED0:
			// Lsb: 0, Len: 21, [20:0] Amplification factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x001FFFFF;
			reg_ishrp2_5.field.s = (d_tmp & m_tmp) | (reg_ishrp2_5.field.s & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_ishrp2_5.field.rsvd21 = (d_tmp & m_tmp) | (reg_ishrp2_5.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 7, [30:24] Amplification factor
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000007F;
			reg_ishrp2_5.field.f = (d_tmp & m_tmp) | (reg_ishrp2_5.field.f & ~m_tmp);
			break;

		case 0x0ED4:
			// Lsb: 0, Len: 22, [21:0] Amplification filter weight normalization factor
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_ishrp3.field.wsum = (d_tmp & m_tmp) | (reg_ishrp3.field.wsum & ~m_tmp);

			// Lsb: 22, Len: 2, [23:22] 
			d_tmp = (data >> 22); m_tmp = (mask >> 22) & 0x00000003;
			reg_ishrp3.field.rsvd22 = (d_tmp & m_tmp) | (reg_ishrp3.field.rsvd22 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] Negative Factor Multiplier
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_ishrp3.field.ndirf = (d_tmp & m_tmp) | (reg_ishrp3.field.ndirf & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] Positive Factor Multiplier
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_ishrp3.field.pdirf = (d_tmp & m_tmp) | (reg_ishrp3.field.pdirf & ~m_tmp);
			break;

		case 0x0ED8:
			// Lsb: 0, Len: 10, [9:0] UV smoothing factor delta 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_iuvs1.field.uvdiff1 = (d_tmp & m_tmp) | (reg_iuvs1.field.uvdiff1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_iuvs1.field.rsvd10 = (d_tmp & m_tmp) | (reg_iuvs1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV smoothing factor delta 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_iuvs1.field.uvdiff2 = (d_tmp & m_tmp) | (reg_iuvs1.field.uvdiff2 & ~m_tmp);
			break;

		case 0x0EDC:
			// Lsb: 0, Len: 18, [17:0] UV smoothing factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_iuvs2.field.uvslope = (d_tmp & m_tmp) | (reg_iuvs2.field.uvslope & ~m_tmp);

			// Lsb: 18, Len: 6, [23:18] 
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x0000003F;
			reg_iuvs2.field.rsvd18 = (d_tmp & m_tmp) | (reg_iuvs2.field.rsvd18 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] UV smoothing factor level
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_iuvs2.field.uvf = (d_tmp & m_tmp) | (reg_iuvs2.field.uvf & ~m_tmp);
			break;

		case 0x0EE0:
			// Lsb: 0, Len: 10, [9:0] UV Color kill factor delta 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_iuvcks1.field.uvckdiff1 = (d_tmp & m_tmp) | (reg_iuvcks1.field.uvckdiff1 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_iuvcks1.field.rsvd10 = (d_tmp & m_tmp) | (reg_iuvcks1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV Color kill factor delta 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_iuvcks1.field.uvckdiff2 = (d_tmp & m_tmp) | (reg_iuvcks1.field.uvckdiff2 & ~m_tmp);
			break;

		case 0x0EE4:
			// Lsb: 0, Len: 18, [17:0] UV Color kill factor slope
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0003FFFF;
			reg_iuvcks2.field.uvckslope = (d_tmp & m_tmp) | (reg_iuvcks2.field.uvckslope & ~m_tmp);
			break;

		case 0x0EE8:
			// Lsb: 0, Len: 1, [0] Edge Threshold enable
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ishrpet.field.en = (d_tmp & m_tmp) | (reg_ishrpet.field.en & ~m_tmp);

			// Lsb: 1, Len: 7, [7:1] 
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x0000007F;
			reg_ishrpet.field.rsvd1 = (d_tmp & m_tmp) | (reg_ishrpet.field.rsvd1 & ~m_tmp);

			// Lsb: 8, Len: 16, [23:8] Threshold (for edge smooth)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000FFFF;
			reg_ishrpet.field.th = (d_tmp & m_tmp) | (reg_ishrpet.field.th & ~m_tmp);
			break;

		case 0x0F00:
			// Lsb: 0, Len: 10, [9:0] Y curve L parammeters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_0.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_0.field.l_param & ~m_tmp);
			break;

		case 0x0F04:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_1.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_1.field.l_param & ~m_tmp);
			break;

		case 0x0F08:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_2.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_2.field.l_param & ~m_tmp);
			break;

		case 0x0F0C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_3.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_3.field.l_param & ~m_tmp);
			break;

		case 0x0F10:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_4.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_4.field.l_param & ~m_tmp);
			break;

		case 0x0F14:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_5.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_5.field.l_param & ~m_tmp);
			break;

		case 0x0F18:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_6.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_6.field.l_param & ~m_tmp);
			break;

		case 0x0F1C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_7.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_7.field.l_param & ~m_tmp);
			break;

		case 0x0F20:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_8.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_8.field.l_param & ~m_tmp);
			break;

		case 0x0F24:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_9.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_9.field.l_param & ~m_tmp);
			break;

		case 0x0F28:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_10.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_10.field.l_param & ~m_tmp);
			break;

		case 0x0F2C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_11.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_11.field.l_param & ~m_tmp);
			break;

		case 0x0F30:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_12.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_12.field.l_param & ~m_tmp);
			break;

		case 0x0F34:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_13.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_13.field.l_param & ~m_tmp);
			break;

		case 0x0F38:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_14.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_14.field.l_param & ~m_tmp);
			break;

		case 0x0F3C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_15.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_15.field.l_param & ~m_tmp);
			break;

		case 0x0F40:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_16.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_16.field.l_param & ~m_tmp);
			break;

		case 0x0F44:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_17.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_17.field.l_param & ~m_tmp);
			break;

		case 0x0F48:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_18.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_18.field.l_param & ~m_tmp);
			break;

		case 0x0F4C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_19.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_19.field.l_param & ~m_tmp);
			break;

		case 0x0F50:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_20.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_20.field.l_param & ~m_tmp);
			break;

		case 0x0F54:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_21.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_21.field.l_param & ~m_tmp);
			break;

		case 0x0F58:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_22.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_22.field.l_param & ~m_tmp);
			break;

		case 0x0F5C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_23.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_23.field.l_param & ~m_tmp);
			break;

		case 0x0F60:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_24.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_24.field.l_param & ~m_tmp);
			break;

		case 0x0F64:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_25.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_25.field.l_param & ~m_tmp);
			break;

		case 0x0F68:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_26.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_26.field.l_param & ~m_tmp);
			break;

		case 0x0F6C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_27.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_27.field.l_param & ~m_tmp);
			break;

		case 0x0F70:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_28.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_28.field.l_param & ~m_tmp);
			break;

		case 0x0F74:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_29.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_29.field.l_param & ~m_tmp);
			break;

		case 0x0F78:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_30.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_30.field.l_param & ~m_tmp);
			break;

		case 0x0F7C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_31.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_31.field.l_param & ~m_tmp);
			break;

		case 0x0F80:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_32.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_32.field.l_param & ~m_tmp);
			break;

		case 0x0F84:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_33.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_33.field.l_param & ~m_tmp);
			break;

		case 0x0F88:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_34.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_34.field.l_param & ~m_tmp);
			break;

		case 0x0F8C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_35.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_35.field.l_param & ~m_tmp);
			break;

		case 0x0F90:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_36.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_36.field.l_param & ~m_tmp);
			break;

		case 0x0F94:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_37.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_37.field.l_param & ~m_tmp);
			break;

		case 0x0F98:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_38.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_38.field.l_param & ~m_tmp);
			break;

		case 0x0F9C:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_39.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_39.field.l_param & ~m_tmp);
			break;

		case 0x0FA0:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_40.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_40.field.l_param & ~m_tmp);
			break;

		case 0x0FA4:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_41.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_41.field.l_param & ~m_tmp);
			break;

		case 0x0FA8:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_42.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_42.field.l_param & ~m_tmp);
			break;

		case 0x0FAC:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_43.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_43.field.l_param & ~m_tmp);
			break;

		case 0x0FB0:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_44.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_44.field.l_param & ~m_tmp);
			break;

		case 0x0FB4:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_45.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_45.field.l_param & ~m_tmp);
			break;

		case 0x0FB8:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_46.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_46.field.l_param & ~m_tmp);
			break;

		case 0x0FBC:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_47.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_47.field.l_param & ~m_tmp);
			break;

		case 0x0FC0:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_48.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_48.field.l_param & ~m_tmp);
			break;

		case 0x0FC4:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_49.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_49.field.l_param & ~m_tmp);
			break;

		case 0x0FC8:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_50.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_50.field.l_param & ~m_tmp);
			break;

		case 0x0FCC:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_51.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_51.field.l_param & ~m_tmp);
			break;

		case 0x0FD0:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_52.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_52.field.l_param & ~m_tmp);
			break;

		case 0x0FD4:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_53.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_53.field.l_param & ~m_tmp);
			break;

		case 0x0FD8:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_54.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_54.field.l_param & ~m_tmp);
			break;

		case 0x0FDC:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_55.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_55.field.l_param & ~m_tmp);
			break;

		case 0x0FE0:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_56.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_56.field.l_param & ~m_tmp);
			break;

		case 0x0FE4:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_57.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_57.field.l_param & ~m_tmp);
			break;

		case 0x0FE8:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_58.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_58.field.l_param & ~m_tmp);
			break;

		case 0x0FEC:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_59.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_59.field.l_param & ~m_tmp);
			break;

		case 0x0FF0:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_60.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_60.field.l_param & ~m_tmp);
			break;

		case 0x0FF4:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_61.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_61.field.l_param & ~m_tmp);
			break;

		case 0x0FF8:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_62.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_62.field.l_param & ~m_tmp);
			break;

		case 0x0FFC:
			// Lsb: 0, Len: 10, [9:0] Y curve L parameters value. Format: 0.10.0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ycurve_63.field.l_param = (d_tmp & m_tmp) | (reg_ycurve_63.field.l_param & ~m_tmp);
			break;

		case 0x1020:
			// Lsb: 0, Len: 10, [9:0] G Sigma X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax0.field.gsx0 = (d_tmp & m_tmp) | (reg_nl3dgsigmax0.field.gsx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax0.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax0.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax0.field.gsx1 = (d_tmp & m_tmp) | (reg_nl3dgsigmax0.field.gsx1 & ~m_tmp);
			break;

		case 0x1024:
			// Lsb: 0, Len: 10, [9:0] G Sigma X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax1.field.gsx2 = (d_tmp & m_tmp) | (reg_nl3dgsigmax1.field.gsx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax1.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax1.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax1.field.gsx3 = (d_tmp & m_tmp) | (reg_nl3dgsigmax1.field.gsx3 & ~m_tmp);
			break;

		case 0x1028:
			// Lsb: 0, Len: 10, [9:0] G Sigma X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax2.field.gsx4 = (d_tmp & m_tmp) | (reg_nl3dgsigmax2.field.gsx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax2.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax2.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax2.field.gsx5 = (d_tmp & m_tmp) | (reg_nl3dgsigmax2.field.gsx5 & ~m_tmp);
			break;

		case 0x102C:
			// Lsb: 0, Len: 10, [9:0] G Sigma X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax3.field.gsx6 = (d_tmp & m_tmp) | (reg_nl3dgsigmax3.field.gsx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax3.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax3.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax3.field.gsx7 = (d_tmp & m_tmp) | (reg_nl3dgsigmax3.field.gsx7 & ~m_tmp);
			break;

		case 0x1030:
			// Lsb: 0, Len: 10, [9:0] G Sigma X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax4.field.gsx8 = (d_tmp & m_tmp) | (reg_nl3dgsigmax4.field.gsx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax4.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax4.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax4.field.gsx9 = (d_tmp & m_tmp) | (reg_nl3dgsigmax4.field.gsx9 & ~m_tmp);
			break;

		case 0x1034:
			// Lsb: 0, Len: 10, [9:0] G Sigma X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax5.field.gsx10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax5.field.gsx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax5.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax5.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax5.field.gsx11 = (d_tmp & m_tmp) | (reg_nl3dgsigmax5.field.gsx11 & ~m_tmp);
			break;

		case 0x1038:
			// Lsb: 0, Len: 10, [9:0] G Sigma X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax6.field.gsx12 = (d_tmp & m_tmp) | (reg_nl3dgsigmax6.field.gsx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax6.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax6.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax6.field.gsx13 = (d_tmp & m_tmp) | (reg_nl3dgsigmax6.field.gsx13 & ~m_tmp);
			break;

		case 0x103C:
			// Lsb: 0, Len: 10, [9:0] G Sigma X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgsigmax7.field.gsx14 = (d_tmp & m_tmp) | (reg_nl3dgsigmax7.field.gsx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgsigmax7.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgsigmax7.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgsigmax7.field.gsx15 = (d_tmp & m_tmp) | (reg_nl3dgsigmax7.field.gsx15 & ~m_tmp);
			break;

		case 0x10A0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y0(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay0.field.gsy0 = (d_tmp & m_tmp) | (reg_nl3dgsigmay0.field.gsy0 & ~m_tmp);
			break;

		case 0x10A4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y1(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay1.field.gsy1 = (d_tmp & m_tmp) | (reg_nl3dgsigmay1.field.gsy1 & ~m_tmp);
			break;

		case 0x10A8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y2(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay2.field.gsy2 = (d_tmp & m_tmp) | (reg_nl3dgsigmay2.field.gsy2 & ~m_tmp);
			break;

		case 0x10AC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y3(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay3.field.gsy3 = (d_tmp & m_tmp) | (reg_nl3dgsigmay3.field.gsy3 & ~m_tmp);
			break;

		case 0x10B0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y4(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay4.field.gsy4 = (d_tmp & m_tmp) | (reg_nl3dgsigmay4.field.gsy4 & ~m_tmp);
			break;

		case 0x10B4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y5(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay5.field.gsy5 = (d_tmp & m_tmp) | (reg_nl3dgsigmay5.field.gsy5 & ~m_tmp);
			break;

		case 0x10B8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y6(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay6.field.gsy6 = (d_tmp & m_tmp) | (reg_nl3dgsigmay6.field.gsy6 & ~m_tmp);
			break;

		case 0x10BC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y7(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay7.field.gsy7 = (d_tmp & m_tmp) | (reg_nl3dgsigmay7.field.gsy7 & ~m_tmp);
			break;

		case 0x10C0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y8(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay8.field.gsy8 = (d_tmp & m_tmp) | (reg_nl3dgsigmay8.field.gsy8 & ~m_tmp);
			break;

		case 0x10C4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y9(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay9.field.gsy9 = (d_tmp & m_tmp) | (reg_nl3dgsigmay9.field.gsy9 & ~m_tmp);
			break;

		case 0x10C8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y10(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay10.field.gsy10 = (d_tmp & m_tmp) | (reg_nl3dgsigmay10.field.gsy10 & ~m_tmp);
			break;

		case 0x10CC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y11(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay11.field.gsy11 = (d_tmp & m_tmp) | (reg_nl3dgsigmay11.field.gsy11 & ~m_tmp);
			break;

		case 0x10D0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y12(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay12.field.gsy12 = (d_tmp & m_tmp) | (reg_nl3dgsigmay12.field.gsy12 & ~m_tmp);
			break;

		case 0x10D4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y13(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay13.field.gsy13 = (d_tmp & m_tmp) | (reg_nl3dgsigmay13.field.gsy13 & ~m_tmp);
			break;

		case 0x10D8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y14(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay14.field.gsy14 = (d_tmp & m_tmp) | (reg_nl3dgsigmay14.field.gsy14 & ~m_tmp);
			break;

		case 0x10DC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y15(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl3dgsigmay15.field.gsy15 = (d_tmp & m_tmp) | (reg_nl3dgsigmay15.field.gsy15 & ~m_tmp);
			break;

		case 0x1140:
			// Lsb: 0, Len: 16, [15:0] G Sigma S0(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas0.field.gss0 = (d_tmp & m_tmp) | (reg_nl3dgsigmas0.field.gss0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S1(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas0.field.gss1 = (d_tmp & m_tmp) | (reg_nl3dgsigmas0.field.gss1 & ~m_tmp);
			break;

		case 0x1144:
			// Lsb: 0, Len: 16, [15:0] G Sigma S2(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas1.field.gss2 = (d_tmp & m_tmp) | (reg_nl3dgsigmas1.field.gss2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S3(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas1.field.gss3 = (d_tmp & m_tmp) | (reg_nl3dgsigmas1.field.gss3 & ~m_tmp);
			break;

		case 0x1148:
			// Lsb: 0, Len: 16, [15:0] G Sigma S4(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas2.field.gss4 = (d_tmp & m_tmp) | (reg_nl3dgsigmas2.field.gss4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S5(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas2.field.gss5 = (d_tmp & m_tmp) | (reg_nl3dgsigmas2.field.gss5 & ~m_tmp);
			break;

		case 0x114C:
			// Lsb: 0, Len: 16, [15:0] G Sigma S6(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas3.field.gss6 = (d_tmp & m_tmp) | (reg_nl3dgsigmas3.field.gss6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S7(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas3.field.gss7 = (d_tmp & m_tmp) | (reg_nl3dgsigmas3.field.gss7 & ~m_tmp);
			break;

		case 0x1150:
			// Lsb: 0, Len: 16, [15:0] G Sigma S8(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas4.field.gss8 = (d_tmp & m_tmp) | (reg_nl3dgsigmas4.field.gss8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S9(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas4.field.gss9 = (d_tmp & m_tmp) | (reg_nl3dgsigmas4.field.gss9 & ~m_tmp);
			break;

		case 0x1154:
			// Lsb: 0, Len: 16, [15:0] G Sigma S10(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas5.field.gss10 = (d_tmp & m_tmp) | (reg_nl3dgsigmas5.field.gss10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S11(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas5.field.gss11 = (d_tmp & m_tmp) | (reg_nl3dgsigmas5.field.gss11 & ~m_tmp);
			break;

		case 0x1158:
			// Lsb: 0, Len: 16, [15:0] G Sigma S12(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas6.field.gss12 = (d_tmp & m_tmp) | (reg_nl3dgsigmas6.field.gss12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S13(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas6.field.gss13 = (d_tmp & m_tmp) | (reg_nl3dgsigmas6.field.gss13 & ~m_tmp);
			break;

		case 0x115C:
			// Lsb: 0, Len: 16, [15:0] G Sigma S14(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgsigmas7.field.gss14 = (d_tmp & m_tmp) | (reg_nl3dgsigmas7.field.gss14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S15(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgsigmas7.field.gss15 = (d_tmp & m_tmp) | (reg_nl3dgsigmas7.field.gss15 & ~m_tmp);
			break;

		case 0x11A0:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx0.field.gfx0 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx0.field.gfx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx0.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx0.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx0.field.gfx1 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx0.field.gfx1 & ~m_tmp);
			break;

		case 0x11A4:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx1.field.gfx2 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx1.field.gfx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx1.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx1.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx1.field.gfx3 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx1.field.gfx3 & ~m_tmp);
			break;

		case 0x11A8:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx2.field.gfx4 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx2.field.gfx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx2.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx2.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx2.field.gfx5 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx2.field.gfx5 & ~m_tmp);
			break;

		case 0x11AC:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx3.field.gfx6 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx3.field.gfx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx3.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx3.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx3.field.gfx7 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx3.field.gfx7 & ~m_tmp);
			break;

		case 0x11B0:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx4.field.gfx8 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx4.field.gfx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx4.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx4.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx4.field.gfx9 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx4.field.gfx9 & ~m_tmp);
			break;

		case 0x11B4:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx5.field.gfx10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx5.field.gfx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx5.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx5.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx5.field.gfx11 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx5.field.gfx11 & ~m_tmp);
			break;

		case 0x11B8:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx6.field.gfx12 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx6.field.gfx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx6.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx6.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx6.field.gfx13 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx6.field.gfx13 & ~m_tmp);
			break;

		case 0x11BC:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl3dgfiltparx7.field.gfx14 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx7.field.gfx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl3dgfiltparx7.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx7.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl3dgfiltparx7.field.gfx15 = (d_tmp & m_tmp) | (reg_nl3dgfiltparx7.field.gfx15 & ~m_tmp);
			break;

		case 0x1220:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y0(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary0.field.gfy0 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary0.field.gfy0 & ~m_tmp);
			break;

		case 0x1224:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y1(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary1.field.gfy1 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary1.field.gfy1 & ~m_tmp);
			break;

		case 0x1228:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y2(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary2.field.gfy2 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary2.field.gfy2 & ~m_tmp);
			break;

		case 0x122C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y3(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary3.field.gfy3 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary3.field.gfy3 & ~m_tmp);
			break;

		case 0x1230:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y4(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary4.field.gfy4 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary4.field.gfy4 & ~m_tmp);
			break;

		case 0x1234:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y5(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary5.field.gfy5 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary5.field.gfy5 & ~m_tmp);
			break;

		case 0x1238:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y6(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary6.field.gfy6 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary6.field.gfy6 & ~m_tmp);
			break;

		case 0x123C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y7(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary7.field.gfy7 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary7.field.gfy7 & ~m_tmp);
			break;

		case 0x1240:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y8(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary8.field.gfy8 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary8.field.gfy8 & ~m_tmp);
			break;

		case 0x1244:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y9(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary9.field.gfy9 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary9.field.gfy9 & ~m_tmp);
			break;

		case 0x1248:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y10(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary10.field.gfy10 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary10.field.gfy10 & ~m_tmp);
			break;

		case 0x124C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y11(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary11.field.gfy11 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary11.field.gfy11 & ~m_tmp);
			break;

		case 0x1250:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y12(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary12.field.gfy12 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary12.field.gfy12 & ~m_tmp);
			break;

		case 0x1254:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y13(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary13.field.gfy13 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary13.field.gfy13 & ~m_tmp);
			break;

		case 0x1258:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y14(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary14.field.gfy14 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary14.field.gfy14 & ~m_tmp);
			break;

		case 0x125C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y15(0.6.16)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl3dgfiltpary15.field.gfy15 = (d_tmp & m_tmp) | (reg_nl3dgfiltpary15.field.gfy15 & ~m_tmp);
			break;

		case 0x12C0:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S0(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars0.field.gfs0 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars0.field.gfs0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S1(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars0.field.gfs1 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars0.field.gfs1 & ~m_tmp);
			break;

		case 0x12C4:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S2(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars1.field.gfs2 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars1.field.gfs2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S3(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars1.field.gfs3 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars1.field.gfs3 & ~m_tmp);
			break;

		case 0x12C8:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S4(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars2.field.gfs4 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars2.field.gfs4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S5(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars2.field.gfs5 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars2.field.gfs5 & ~m_tmp);
			break;

		case 0x12CC:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S6(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars3.field.gfs6 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars3.field.gfs6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S7(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars3.field.gfs7 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars3.field.gfs7 & ~m_tmp);
			break;

		case 0x12D0:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S8(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars4.field.gfs8 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars4.field.gfs8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S9(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars4.field.gfs9 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars4.field.gfs9 & ~m_tmp);
			break;

		case 0x12D4:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S10(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars5.field.gfs10 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars5.field.gfs10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S11(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars5.field.gfs11 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars5.field.gfs11 & ~m_tmp);
			break;

		case 0x12D8:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S12(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars6.field.gfs12 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars6.field.gfs12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S13(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars6.field.gfs13 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars6.field.gfs13 & ~m_tmp);
			break;

		case 0x12DC:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S14(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl3dgfiltpars7.field.gfs14 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars7.field.gfs14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S15(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl3dgfiltpars7.field.gfs15 = (d_tmp & m_tmp) | (reg_nl3dgfiltpars7.field.gfs15 & ~m_tmp);
			break;

		case 0x1300:
			// Lsb: 0, Len: 2, [1:0] TL - Top Left(read only)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_nl3dcfg.field.rsvd0 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd0 & ~m_tmp);

			// Lsb: 2, Len: 2, [3:2] TR - Top Right(read only)
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000003;
			reg_nl3dcfg.field.rsvd2 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd2 & ~m_tmp);

			// Lsb: 4, Len: 2, [5:4] BL - Bottom Left(read only)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000003;
			reg_nl3dcfg.field.rsvd4 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd4 & ~m_tmp);

			// Lsb: 6, Len: 2, [7:6] BR - Bottom Right(read only)
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000003;
			reg_nl3dcfg.field.rsvd6 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd6 & ~m_tmp);

			// Lsb: 8, Len: 9, [16:8] 
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000001FF;
			reg_nl3dcfg.field.rsvd8 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd8 & ~m_tmp);

			// Lsb: 17, Len: 3, [19:17] shift (sigma/filtpar scale parameter), bit[2] high indicate left shift for filtpar and right shift for sigma
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000007;
			reg_nl3dcfg.field.shift = (d_tmp & m_tmp) | (reg_nl3dcfg.field.shift & ~m_tmp);

			// Lsb: 20, Len: 3, [22:20] SHOTNOR - Reject shot noise number for R channel
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000007;
			reg_nl3dcfg.field.rsvd20 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd20 & ~m_tmp);

			// Lsb: 23, Len: 1, [23] 
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x00000001;
			reg_nl3dcfg.field.rsvd23 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd23 & ~m_tmp);

			// Lsb: 24, Len: 3, [26:24] Reject shot noise number for G channel
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x00000007;
			reg_nl3dcfg.field.shotnog = (d_tmp & m_tmp) | (reg_nl3dcfg.field.shotnog & ~m_tmp);

			// Lsb: 27, Len: 1, [27] 
			d_tmp = (data >> 27); m_tmp = (mask >> 27) & 0x00000001;
			reg_nl3dcfg.field.rsvd27 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd27 & ~m_tmp);

			// Lsb: 28, Len: 3, [30:28] SHOTNOB - Reject shot noise number for B channel
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x00000007;
			reg_nl3dcfg.field.rsvd28 = (d_tmp & m_tmp) | (reg_nl3dcfg.field.rsvd28 & ~m_tmp);
			break;

		case 0x1304:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_dnriay.field.rsvd0 = (d_tmp & m_tmp) | (reg_dnriay.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] decompress start address, 128byte align
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_dnriay.field.sad = (d_tmp & m_tmp) | (reg_dnriay.field.sad & ~m_tmp);
			break;

		case 0x1308:
			// Lsb: 0, Len: 4, [3:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_dnrfbdcar.field.rsvd = (d_tmp & m_tmp) | (reg_dnrfbdcar.field.rsvd & ~m_tmp);

			// Lsb: 4, Len: 28, [31:4] axi read address bit[31:4], read only
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0FFFFFFF;
			reg_dnrfbdcar.field.araddr = (d_tmp & m_tmp) | (reg_dnrfbdcar.field.araddr & ~m_tmp);
			break;

		case 0x130C:
			// Lsb: 0, Len: 32, [31:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_dnris.field.rsvd = (d_tmp & m_tmp) | (reg_dnris.field.rsvd & ~m_tmp);
			break;

		case 0x1310:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_dnroay.field.rsvd0 = (d_tmp & m_tmp) | (reg_dnroay.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] compress start address, 128byte align
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_dnroay.field.sad = (d_tmp & m_tmp) | (reg_dnroay.field.sad & ~m_tmp);
			break;

		case 0x1314:
			// Lsb: 0, Len: 16, [15:0] Quantization parameter
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_dnrcc2.field.qt1 = (d_tmp & m_tmp) | (reg_dnrcc2.field.qt1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Quantization parameter
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_dnrcc2.field.qt2 = (d_tmp & m_tmp) | (reg_dnrcc2.field.qt2 & ~m_tmp);
			break;

		case 0x1318:
			// Lsb: 0, Len: 16, [15:0] Quantization parameter
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_dnrcc3.field.qt3 = (d_tmp & m_tmp) | (reg_dnrcc3.field.qt3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] 
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_dnrcc3.field.rsvd16 = (d_tmp & m_tmp) | (reg_dnrcc3.field.rsvd16 & ~m_tmp);
			break;

		case 0x131C:
			// Lsb: 0, Len: 32, [31:0] Reference frame buffer size in bytes., no use
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_dnrisz.field.sz = (d_tmp & m_tmp) | (reg_dnrisz.field.sz & ~m_tmp);
			break;

		case 0x1320:
			// Lsb: 0, Len: 32, [31:0] Reference frame buffer size in bytes.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_dnrosz.field.sz = (d_tmp & m_tmp) | (reg_dnrosz.field.sz & ~m_tmp);
			break;

		case 0x1324:
			// Lsb: 0, Len: 2, [1:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_dnrcc.field.rsvd0 = (d_tmp & m_tmp) | (reg_dnrcc.field.rsvd0 & ~m_tmp);

			// Lsb: 2, Len: 2, [3:2] Color transform.
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000003;
			reg_dnrcc.field.ct = (d_tmp & m_tmp) | (reg_dnrcc.field.ct & ~m_tmp);

			// Lsb: 4, Len: 3, [6:4] Sample width.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000007;
			reg_dnrcc.field.sw = (d_tmp & m_tmp) | (reg_dnrcc.field.sw & ~m_tmp);
			break;

		case 0x1328:
			// Lsb: 0, Len: 1, [0] Frame Buffer Compression Enable
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_dnrcc1.field.fbe = (d_tmp & m_tmp) | (reg_dnrcc1.field.fbe & ~m_tmp);

			// Lsb: 1, Len: 1, [1] Frame Buffer Decompression Enable
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_dnrcc1.field.tb = (d_tmp & m_tmp) | (reg_dnrcc1.field.tb & ~m_tmp);

			// Lsb: 2, Len: 1, [2] enable read/write data with axi bus. (RSVD, set zero)
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_dnrcc1.field.axie = (d_tmp & m_tmp) | (reg_dnrcc1.field.axie & ~m_tmp);

			// Lsb: 3, Len: 1, [3] It is valid when FBE=0 and TB=0. This bit selects data format in DDR. 0:packed without gap  1: per pixel used 16bits
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_dnrcc1.field.format = (d_tmp & m_tmp) | (reg_dnrcc1.field.format & ~m_tmp);

			// Lsb: 4, Len: 1, [4] only enable compression model when FBE=1and TB=1. (RSVD, set zero)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_dnrcc1.field.onecmp = (d_tmp & m_tmp) | (reg_dnrcc1.field.onecmp & ~m_tmp);

			// Lsb: 5, Len: 1, [5] Only once compressed or decompressed. (RSVD, set zero)
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_dnrcc1.field.cdconce = (d_tmp & m_tmp) | (reg_dnrcc1.field.cdconce & ~m_tmp);

			// Lsb: 6, Len: 1, [6] Control Frame Buffer Decompression to start read data .  1:used register FBCLN to control   0: used input frame end signal
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000001;
			reg_dnrcc1.field.fbdcsm = (d_tmp & m_tmp) | (reg_dnrcc1.field.fbdcsm & ~m_tmp);

			// Lsb: 7, Len: 1, [7] 
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_dnrcc1.field.rsvd7 = (d_tmp & m_tmp) | (reg_dnrcc1.field.rsvd7 & ~m_tmp);

			// Lsb: 8, Len: 2, [9:8] fbdc read axi outstanding mode, 0 : 4*1*8*64, 1: 2*2*8*64, 2: 1*4*8*64
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000003;
			reg_dnrcc1.field.rbstm = (d_tmp & m_tmp) | (reg_dnrcc1.field.rbstm & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_dnrcc1.field.rsvd10 = (d_tmp & m_tmp) | (reg_dnrcc1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Frame Buffer Compression had compressed image lines number.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_dnrcc1.field.fbcln = (d_tmp & m_tmp) | (reg_dnrcc1.field.fbcln & ~m_tmp);

			// Lsb: 29, Len: 2, [30:29] 
			d_tmp = (data >> 29); m_tmp = (mask >> 29) & 0x00000003;
			reg_dnrcc1.field.rsvd29 = (d_tmp & m_tmp) | (reg_dnrcc1.field.rsvd29 & ~m_tmp);

			// Lsb: 31, Len: 1, [31] trigger nl3d control FSM to work(this bit must be configured after nl3d_enable, FBE, TB or AXIE). 1: start work 0: back idle
			d_tmp = (data >> 31); m_tmp = (mask >> 31) & 0x00000001;
			reg_dnrcc1.field.trg = (d_tmp & m_tmp) | (reg_dnrcc1.field.trg & ~m_tmp);
			break;

		case 0x132C:
			// Lsb: 0, Len: 1, [0] Frame Buffer Decompression busy.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_dnrcs.field.fbcb = (d_tmp & m_tmp) | (reg_dnrcs.field.fbcb & ~m_tmp);

			// Lsb: 1, Len: 1, [1] Frame Buffer Decompression busy.
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_dnrcs.field.fbdcb = (d_tmp & m_tmp) | (reg_dnrcs.field.fbdcb & ~m_tmp);

			// Lsb: 2, Len: 2, [3:2] 
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000003;
			reg_dnrcs.field.rsvd2 = (d_tmp & m_tmp) | (reg_dnrcs.field.rsvd2 & ~m_tmp);

			// Lsb: 4, Len: 2, [5:4] FSM(controlnl3d+compress) value.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000003;
			reg_dnrcs.field.ctrls = (d_tmp & m_tmp) | (reg_dnrcs.field.ctrls & ~m_tmp);
			break;

		case 0x1330:
			// Lsb: 0, Len: 25, [24:0] Frame Buffer Decompression buffer length value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x01FFFFFF;
			reg_dnrcl.field.fbcbl = (d_tmp & m_tmp) | (reg_dnrcl.field.fbcbl & ~m_tmp);
			break;

		case 0x1334:
			// Lsb: 0, Len: 4, [3:0] 1st 2D filter weight [0.4.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_nl3d_w2d1r.field.w2d1_0 = (d_tmp & m_tmp) | (reg_nl3d_w2d1r.field.w2d1_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] 1st 2D filter weight [0.4.0]
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_nl3d_w2d1r.field.w2d1_1 = (d_tmp & m_tmp) | (reg_nl3d_w2d1r.field.w2d1_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] 1st 2D filter weight [0.4.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_nl3d_w2d1r.field.w2d1_2 = (d_tmp & m_tmp) | (reg_nl3d_w2d1r.field.w2d1_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 1st 2D filter weight [0.4.0]
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_w2d1r.field.w2d1_3 = (d_tmp & m_tmp) | (reg_nl3d_w2d1r.field.w2d1_3 & ~m_tmp);
			break;

		case 0x1338:
			// Lsb: 0, Len: 12, [11:0] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d1r0.field.d2d1_0 = (d_tmp & m_tmp) | (reg_nl3d_d2d1r0.field.d2d1_0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_d2d1r0.field.rsvd12 = (d_tmp & m_tmp) | (reg_nl3d_d2d1r0.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_nl3d_d2d1r0.field.d2d1_1 = (d_tmp & m_tmp) | (reg_nl3d_d2d1r0.field.d2d1_1 & ~m_tmp);
			break;

		case 0x133C:
			// Lsb: 0, Len: 12, [11:0] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d1r1.field.d2d1_2 = (d_tmp & m_tmp) | (reg_nl3d_d2d1r1.field.d2d1_2 & ~m_tmp);
			break;

		case 0x1340:
			// Lsb: 0, Len: 12, [11:0] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d1g0.field.d2d1_0 = (d_tmp & m_tmp) | (reg_nl3d_d2d1g0.field.d2d1_0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_d2d1g0.field.rsvd12 = (d_tmp & m_tmp) | (reg_nl3d_d2d1g0.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_nl3d_d2d1g0.field.d2d1_1 = (d_tmp & m_tmp) | (reg_nl3d_d2d1g0.field.d2d1_1 & ~m_tmp);
			break;

		case 0x1344:
			// Lsb: 0, Len: 12, [11:0] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d1g1.field.d2d1_2 = (d_tmp & m_tmp) | (reg_nl3d_d2d1g1.field.d2d1_2 & ~m_tmp);
			break;

		case 0x1348:
			// Lsb: 0, Len: 12, [11:0] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d1b0.field.d2d1_0 = (d_tmp & m_tmp) | (reg_nl3d_d2d1b0.field.d2d1_0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_d2d1b0.field.rsvd12 = (d_tmp & m_tmp) | (reg_nl3d_d2d1b0.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_nl3d_d2d1b0.field.d2d1_1 = (d_tmp & m_tmp) | (reg_nl3d_d2d1b0.field.d2d1_1 & ~m_tmp);
			break;

		case 0x134C:
			// Lsb: 0, Len: 12, [11:0] 1st 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d1b1.field.d2d1_2 = (d_tmp & m_tmp) | (reg_nl3d_d2d1b1.field.d2d1_2 & ~m_tmp);
			break;

		case 0x1350:
			// Lsb: 0, Len: 4, [3:0] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_nl3d_s2d1r0.field.s2d1_0 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r0.field.s2d1_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_nl3d_s2d1r0.field.s2d1_1 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r0.field.s2d1_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_nl3d_s2d1r0.field.s2d1_2 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r0.field.s2d1_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_s2d1r0.field.s2d1_3 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r0.field.s2d1_3 & ~m_tmp);
			break;

		case 0x1354:
			// Lsb: 0, Len: 4, [3:0] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_nl3d_s2d1r1.field.s2d1_4 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r1.field.s2d1_4 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_nl3d_s2d1r1.field.s2d1_5 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r1.field.s2d1_5 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_nl3d_s2d1r1.field.s2d1_6 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r1.field.s2d1_6 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_s2d1r1.field.s2d1_7 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r1.field.s2d1_7 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] 1st 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_nl3d_s2d1r1.field.s2d1_8 = (d_tmp & m_tmp) | (reg_nl3d_s2d1r1.field.s2d1_8 & ~m_tmp);
			break;

		case 0x1358:
			// Lsb: 0, Len: 4, [3:0] 2nd 2D filter weight [0.4.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_nl3d_w2d2r.field.w2d2_0 = (d_tmp & m_tmp) | (reg_nl3d_w2d2r.field.w2d2_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] 2nd 2D filter weight [0.4.0]
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_nl3d_w2d2r.field.w2d2_1 = (d_tmp & m_tmp) | (reg_nl3d_w2d2r.field.w2d2_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] 2nd 2D filter weight [0.4.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_nl3d_w2d2r.field.w2d2_2 = (d_tmp & m_tmp) | (reg_nl3d_w2d2r.field.w2d2_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 2nd 2D filter weight [0.4.0]
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_w2d2r.field.w2d2_3 = (d_tmp & m_tmp) | (reg_nl3d_w2d2r.field.w2d2_3 & ~m_tmp);
			break;

		case 0x135C:
			// Lsb: 0, Len: 12, [11:0] 2nd 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d2r0.field.d2d2_0 = (d_tmp & m_tmp) | (reg_nl3d_d2d2r0.field.d2d2_0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_d2d2r0.field.rsvd12 = (d_tmp & m_tmp) | (reg_nl3d_d2d2r0.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] 2nd 2D filter difference weight [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_nl3d_d2d2r0.field.d2d2_1 = (d_tmp & m_tmp) | (reg_nl3d_d2d2r0.field.d2d2_1 & ~m_tmp);
			break;

		case 0x1360:
			// Lsb: 0, Len: 12, [11:0] 2nd 2D filter difference weight [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_d2d2r1.field.d2d2_2 = (d_tmp & m_tmp) | (reg_nl3d_d2d2r1.field.d2d2_2 & ~m_tmp);
			break;

		case 0x1364:
			// Lsb: 0, Len: 4, [3:0] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_nl3d_s2d2r0.field.s2d2_0 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r0.field.s2d2_0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_nl3d_s2d2r0.field.s2d2_1 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r0.field.s2d2_1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_nl3d_s2d2r0.field.s2d2_2 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r0.field.s2d2_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_s2d2r0.field.s2d2_3 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r0.field.s2d2_3 & ~m_tmp);
			break;

		case 0x1368:
			// Lsb: 0, Len: 4, [3:0] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_nl3d_s2d2r1.field.s2d2_4 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r1.field.s2d2_4 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_nl3d_s2d2r1.field.s2d2_5 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r1.field.s2d2_5 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_nl3d_s2d2r1.field.s2d2_6 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r1.field.s2d2_6 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_s2d2r1.field.s2d2_7 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r1.field.s2d2_7 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] 2nd 2D filter spatial weight [0.4.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_nl3d_s2d2r1.field.s2d2_8 = (d_tmp & m_tmp) | (reg_nl3d_s2d2r1.field.s2d2_8 & ~m_tmp);
			break;

		case 0x136C:
			// Lsb: 0, Len: 9, [8:0] refw curve x [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_refwcx0.field.refwcx_0 = (d_tmp & m_tmp) | (reg_nl3d_refwcx0.field.refwcx_0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_refwcx0.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_refwcx0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] refw curve x [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_refwcx0.field.refwcx_1 = (d_tmp & m_tmp) | (reg_nl3d_refwcx0.field.refwcx_1 & ~m_tmp);
			break;

		case 0x1370:
			// Lsb: 0, Len: 9, [8:0] refw curve x [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_refwcx1.field.refwcx_2 = (d_tmp & m_tmp) | (reg_nl3d_refwcx1.field.refwcx_2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_refwcx1.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_refwcx1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] refw curve x [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_refwcx1.field.refwcx_3 = (d_tmp & m_tmp) | (reg_nl3d_refwcx1.field.refwcx_3 & ~m_tmp);
			break;

		case 0x1374:
			// Lsb: 0, Len: 9, [8:0] refw curve y [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_refwcy0.field.refwcy_0 = (d_tmp & m_tmp) | (reg_nl3d_refwcy0.field.refwcy_0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_refwcy0.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_refwcy0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] refw curve y [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_refwcy0.field.refwcy_1 = (d_tmp & m_tmp) | (reg_nl3d_refwcy0.field.refwcy_1 & ~m_tmp);
			break;

		case 0x1378:
			// Lsb: 0, Len: 9, [8:0] refw curve y [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_refwcy1.field.refwcy_2 = (d_tmp & m_tmp) | (reg_nl3d_refwcy1.field.refwcy_2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_refwcy1.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_refwcy1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] refw curve y [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_refwcy1.field.refwcy_3 = (d_tmp & m_tmp) | (reg_nl3d_refwcy1.field.refwcy_3 & ~m_tmp);
			break;

		case 0x137C:
			// Lsb: 0, Len: 9, [8:0] movw curve x [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_movwcx0.field.movwcx_0 = (d_tmp & m_tmp) | (reg_nl3d_movwcx0.field.movwcx_0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_movwcx0.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_movwcx0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] movw curve x [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_movwcx0.field.movwcx_1 = (d_tmp & m_tmp) | (reg_nl3d_movwcx0.field.movwcx_1 & ~m_tmp);
			break;

		case 0x1380:
			// Lsb: 0, Len: 9, [8:0] movw curve x [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_movwcx1.field.movwcx_2 = (d_tmp & m_tmp) | (reg_nl3d_movwcx1.field.movwcx_2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_movwcx1.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_movwcx1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] movw curve x [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_movwcx1.field.movwcx_3 = (d_tmp & m_tmp) | (reg_nl3d_movwcx1.field.movwcx_3 & ~m_tmp);
			break;

		case 0x1384:
			// Lsb: 0, Len: 9, [8:0] movw curve y [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_movwcy0.field.movwcy_0 = (d_tmp & m_tmp) | (reg_nl3d_movwcy0.field.movwcy_0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_movwcy0.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_movwcy0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] movw curve y [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_movwcy0.field.movwcy_1 = (d_tmp & m_tmp) | (reg_nl3d_movwcy0.field.movwcy_1 & ~m_tmp);
			break;

		case 0x1388:
			// Lsb: 0, Len: 9, [8:0] movw curve y [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_movwcy1.field.movwcy_2 = (d_tmp & m_tmp) | (reg_nl3d_movwcy1.field.movwcy_2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_movwcy1.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_movwcy1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] movw curve y [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_movwcy1.field.movwcy_3 = (d_tmp & m_tmp) | (reg_nl3d_movwcy1.field.movwcy_3 & ~m_tmp);
			break;

		case 0x138C:
			// Lsb: 0, Len: 9, [8:0] snt curve x [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_sntcx0.field.sntcx_0 = (d_tmp & m_tmp) | (reg_nl3d_sntcx0.field.sntcx_0 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_sntcx0.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_sntcx0.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] snt curve x [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_sntcx0.field.sntcx_1 = (d_tmp & m_tmp) | (reg_nl3d_sntcx0.field.sntcx_1 & ~m_tmp);
			break;

		case 0x1390:
			// Lsb: 0, Len: 9, [8:0] snt curve x [0.9.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000001FF;
			reg_nl3d_sntcx1.field.sntcx_2 = (d_tmp & m_tmp) | (reg_nl3d_sntcx1.field.sntcx_2 & ~m_tmp);

			// Lsb: 9, Len: 7, [15:9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x0000007F;
			reg_nl3d_sntcx1.field.rsvd9 = (d_tmp & m_tmp) | (reg_nl3d_sntcx1.field.rsvd9 & ~m_tmp);

			// Lsb: 16, Len: 9, [24:16] snt curve x [0.9.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000001FF;
			reg_nl3d_sntcx1.field.sntcx_3 = (d_tmp & m_tmp) | (reg_nl3d_sntcx1.field.sntcx_3 & ~m_tmp);
			break;

		case 0x1394:
			// Lsb: 0, Len: 12, [11:0] snt curve y [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_sntcy0.field.sntcy_0 = (d_tmp & m_tmp) | (reg_nl3d_sntcy0.field.sntcy_0 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_sntcy0.field.rsvd12 = (d_tmp & m_tmp) | (reg_nl3d_sntcy0.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] snt curve y [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_nl3d_sntcy0.field.sntcy_1 = (d_tmp & m_tmp) | (reg_nl3d_sntcy0.field.sntcy_1 & ~m_tmp);
			break;

		case 0x1398:
			// Lsb: 0, Len: 12, [11:0] snt curve y [0.12.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_nl3d_sntcy1.field.sntcy_2 = (d_tmp & m_tmp) | (reg_nl3d_sntcy1.field.sntcy_2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_nl3d_sntcy1.field.rsvd12 = (d_tmp & m_tmp) | (reg_nl3d_sntcy1.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] snt curve y [0.12.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_nl3d_sntcy1.field.sntcy_3 = (d_tmp & m_tmp) | (reg_nl3d_sntcy1.field.sntcy_3 & ~m_tmp);
			break;

		case 0x2000:
			// Lsb: 0, Len: 10, [9:0] R Sigma X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax0.field.rsx0 = (d_tmp & m_tmp) | (reg_nl2drsigmax0.field.rsx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax0.field.rsx1 = (d_tmp & m_tmp) | (reg_nl2drsigmax0.field.rsx1 & ~m_tmp);
			break;

		case 0x2004:
			// Lsb: 0, Len: 10, [9:0] R Sigma X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax1.field.rsx2 = (d_tmp & m_tmp) | (reg_nl2drsigmax1.field.rsx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax1.field.rsx3 = (d_tmp & m_tmp) | (reg_nl2drsigmax1.field.rsx3 & ~m_tmp);
			break;

		case 0x2008:
			// Lsb: 0, Len: 10, [9:0] R Sigma X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax2.field.rsx4 = (d_tmp & m_tmp) | (reg_nl2drsigmax2.field.rsx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax2.field.rsx5 = (d_tmp & m_tmp) | (reg_nl2drsigmax2.field.rsx5 & ~m_tmp);
			break;

		case 0x200C:
			// Lsb: 0, Len: 10, [9:0] R Sigma X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax3.field.rsx6 = (d_tmp & m_tmp) | (reg_nl2drsigmax3.field.rsx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax3.field.rsx7 = (d_tmp & m_tmp) | (reg_nl2drsigmax3.field.rsx7 & ~m_tmp);
			break;

		case 0x2010:
			// Lsb: 0, Len: 10, [9:0] R Sigma X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax4.field.rsx8 = (d_tmp & m_tmp) | (reg_nl2drsigmax4.field.rsx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax4.field.rsx9 = (d_tmp & m_tmp) | (reg_nl2drsigmax4.field.rsx9 & ~m_tmp);
			break;

		case 0x2014:
			// Lsb: 0, Len: 10, [9:0] R Sigma X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax5.field.rsx10 = (d_tmp & m_tmp) | (reg_nl2drsigmax5.field.rsx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax5.field.rsx11 = (d_tmp & m_tmp) | (reg_nl2drsigmax5.field.rsx11 & ~m_tmp);
			break;

		case 0x2018:
			// Lsb: 0, Len: 10, [9:0] R Sigma X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax6.field.rsx12 = (d_tmp & m_tmp) | (reg_nl2drsigmax6.field.rsx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax6.field.rsx13 = (d_tmp & m_tmp) | (reg_nl2drsigmax6.field.rsx13 & ~m_tmp);
			break;

		case 0x201C:
			// Lsb: 0, Len: 10, [9:0] R Sigma X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drsigmax7.field.rsx14 = (d_tmp & m_tmp) | (reg_nl2drsigmax7.field.rsx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drsigmax7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drsigmax7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Sigma X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drsigmax7.field.rsx15 = (d_tmp & m_tmp) | (reg_nl2drsigmax7.field.rsx15 & ~m_tmp);
			break;

		case 0x2020:
			// Lsb: 0, Len: 10, [9:0] G Sigma X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax0.field.gsx0 = (d_tmp & m_tmp) | (reg_nl2dgsigmax0.field.gsx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax0.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax0.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax0.field.gsx1 = (d_tmp & m_tmp) | (reg_nl2dgsigmax0.field.gsx1 & ~m_tmp);
			break;

		case 0x2024:
			// Lsb: 0, Len: 10, [9:0] G Sigma X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax1.field.gsx2 = (d_tmp & m_tmp) | (reg_nl2dgsigmax1.field.gsx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax1.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax1.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax1.field.gsx3 = (d_tmp & m_tmp) | (reg_nl2dgsigmax1.field.gsx3 & ~m_tmp);
			break;

		case 0x2028:
			// Lsb: 0, Len: 10, [9:0] G Sigma X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax2.field.gsx4 = (d_tmp & m_tmp) | (reg_nl2dgsigmax2.field.gsx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax2.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax2.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax2.field.gsx5 = (d_tmp & m_tmp) | (reg_nl2dgsigmax2.field.gsx5 & ~m_tmp);
			break;

		case 0x202C:
			// Lsb: 0, Len: 10, [9:0] G Sigma X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax3.field.gsx6 = (d_tmp & m_tmp) | (reg_nl2dgsigmax3.field.gsx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax3.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax3.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax3.field.gsx7 = (d_tmp & m_tmp) | (reg_nl2dgsigmax3.field.gsx7 & ~m_tmp);
			break;

		case 0x2030:
			// Lsb: 0, Len: 10, [9:0] G Sigma X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax4.field.gsx8 = (d_tmp & m_tmp) | (reg_nl2dgsigmax4.field.gsx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax4.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax4.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax4.field.gsx9 = (d_tmp & m_tmp) | (reg_nl2dgsigmax4.field.gsx9 & ~m_tmp);
			break;

		case 0x2034:
			// Lsb: 0, Len: 10, [9:0] G Sigma X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax5.field.gsx10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax5.field.gsx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax5.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax5.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax5.field.gsx11 = (d_tmp & m_tmp) | (reg_nl2dgsigmax5.field.gsx11 & ~m_tmp);
			break;

		case 0x2038:
			// Lsb: 0, Len: 10, [9:0] G Sigma X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax6.field.gsx12 = (d_tmp & m_tmp) | (reg_nl2dgsigmax6.field.gsx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax6.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax6.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax6.field.gsx13 = (d_tmp & m_tmp) | (reg_nl2dgsigmax6.field.gsx13 & ~m_tmp);
			break;

		case 0x203C:
			// Lsb: 0, Len: 10, [9:0] G Sigma X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgsigmax7.field.gsx14 = (d_tmp & m_tmp) | (reg_nl2dgsigmax7.field.gsx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgsigmax7.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgsigmax7.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Sigma X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgsigmax7.field.gsx15 = (d_tmp & m_tmp) | (reg_nl2dgsigmax7.field.gsx15 & ~m_tmp);
			break;

		case 0x2040:
			// Lsb: 0, Len: 10, [9:0] B Sigma X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax0.field.bsx0 = (d_tmp & m_tmp) | (reg_nl2dbsigmax0.field.bsx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax0.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax0.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax0.field.bsx1 = (d_tmp & m_tmp) | (reg_nl2dbsigmax0.field.bsx1 & ~m_tmp);
			break;

		case 0x2044:
			// Lsb: 0, Len: 10, [9:0] B Sigma X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax1.field.bsx2 = (d_tmp & m_tmp) | (reg_nl2dbsigmax1.field.bsx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax1.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax1.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax1.field.bsx3 = (d_tmp & m_tmp) | (reg_nl2dbsigmax1.field.bsx3 & ~m_tmp);
			break;

		case 0x2048:
			// Lsb: 0, Len: 10, [9:0] B Sigma X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax2.field.bsx4 = (d_tmp & m_tmp) | (reg_nl2dbsigmax2.field.bsx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax2.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax2.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax2.field.bsx5 = (d_tmp & m_tmp) | (reg_nl2dbsigmax2.field.bsx5 & ~m_tmp);
			break;

		case 0x204C:
			// Lsb: 0, Len: 10, [9:0] B Sigma X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax3.field.bsx6 = (d_tmp & m_tmp) | (reg_nl2dbsigmax3.field.bsx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax3.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax3.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax3.field.bsx7 = (d_tmp & m_tmp) | (reg_nl2dbsigmax3.field.bsx7 & ~m_tmp);
			break;

		case 0x2050:
			// Lsb: 0, Len: 10, [9:0] B Sigma X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax4.field.bsx8 = (d_tmp & m_tmp) | (reg_nl2dbsigmax4.field.bsx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax4.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax4.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax4.field.bsx9 = (d_tmp & m_tmp) | (reg_nl2dbsigmax4.field.bsx9 & ~m_tmp);
			break;

		case 0x2054:
			// Lsb: 0, Len: 10, [9:0] B Sigma X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax5.field.bsx10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax5.field.bsx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax5.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax5.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax5.field.bsx11 = (d_tmp & m_tmp) | (reg_nl2dbsigmax5.field.bsx11 & ~m_tmp);
			break;

		case 0x2058:
			// Lsb: 0, Len: 10, [9:0] B Sigma X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax6.field.bsx12 = (d_tmp & m_tmp) | (reg_nl2dbsigmax6.field.bsx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax6.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax6.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax6.field.bsx13 = (d_tmp & m_tmp) | (reg_nl2dbsigmax6.field.bsx13 & ~m_tmp);
			break;

		case 0x205C:
			// Lsb: 0, Len: 10, [9:0] B Sigma X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbsigmax7.field.bsx14 = (d_tmp & m_tmp) | (reg_nl2dbsigmax7.field.bsx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbsigmax7.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbsigmax7.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Sigma X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbsigmax7.field.bsx15 = (d_tmp & m_tmp) | (reg_nl2dbsigmax7.field.bsx15 & ~m_tmp);
			break;

		case 0x2060:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y0(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay0.field.rsy0 = (d_tmp & m_tmp) | (reg_nl2drsigmay0.field.rsy0 & ~m_tmp);
			break;

		case 0x2064:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y1(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay1.field.rsy1 = (d_tmp & m_tmp) | (reg_nl2drsigmay1.field.rsy1 & ~m_tmp);
			break;

		case 0x2068:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y2(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay2.field.rsy2 = (d_tmp & m_tmp) | (reg_nl2drsigmay2.field.rsy2 & ~m_tmp);
			break;

		case 0x206C:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y3(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay3.field.rsy3 = (d_tmp & m_tmp) | (reg_nl2drsigmay3.field.rsy3 & ~m_tmp);
			break;

		case 0x2070:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y4(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay4.field.rsy4 = (d_tmp & m_tmp) | (reg_nl2drsigmay4.field.rsy4 & ~m_tmp);
			break;

		case 0x2074:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y5(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay5.field.rsy5 = (d_tmp & m_tmp) | (reg_nl2drsigmay5.field.rsy5 & ~m_tmp);
			break;

		case 0x2078:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y6(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay6.field.rsy6 = (d_tmp & m_tmp) | (reg_nl2drsigmay6.field.rsy6 & ~m_tmp);
			break;

		case 0x207C:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y7(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay7.field.rsy7 = (d_tmp & m_tmp) | (reg_nl2drsigmay7.field.rsy7 & ~m_tmp);
			break;

		case 0x2080:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y8(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay8.field.rsy8 = (d_tmp & m_tmp) | (reg_nl2drsigmay8.field.rsy8 & ~m_tmp);
			break;

		case 0x2084:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y9(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay9.field.rsy9 = (d_tmp & m_tmp) | (reg_nl2drsigmay9.field.rsy9 & ~m_tmp);
			break;

		case 0x2088:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y10(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay10.field.rsy10 = (d_tmp & m_tmp) | (reg_nl2drsigmay10.field.rsy10 & ~m_tmp);
			break;

		case 0x208C:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y11(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay11.field.rsy11 = (d_tmp & m_tmp) | (reg_nl2drsigmay11.field.rsy11 & ~m_tmp);
			break;

		case 0x2090:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y12(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay12.field.rsy12 = (d_tmp & m_tmp) | (reg_nl2drsigmay12.field.rsy12 & ~m_tmp);
			break;

		case 0x2094:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y13(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay13.field.rsy13 = (d_tmp & m_tmp) | (reg_nl2drsigmay13.field.rsy13 & ~m_tmp);
			break;

		case 0x2098:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y14(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay14.field.rsy14 = (d_tmp & m_tmp) | (reg_nl2drsigmay14.field.rsy14 & ~m_tmp);
			break;

		case 0x209C:
			// Lsb: 0, Len: 14, [13:0] R Sigma Y15(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2drsigmay15.field.rsy15 = (d_tmp & m_tmp) | (reg_nl2drsigmay15.field.rsy15 & ~m_tmp);
			break;

		case 0x20A0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y0(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay0.field.gsy0 = (d_tmp & m_tmp) | (reg_nl2dgsigmay0.field.gsy0 & ~m_tmp);
			break;

		case 0x20A4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y1(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay1.field.gsy1 = (d_tmp & m_tmp) | (reg_nl2dgsigmay1.field.gsy1 & ~m_tmp);
			break;

		case 0x20A8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y2(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay2.field.gsy2 = (d_tmp & m_tmp) | (reg_nl2dgsigmay2.field.gsy2 & ~m_tmp);
			break;

		case 0x20AC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y3(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay3.field.gsy3 = (d_tmp & m_tmp) | (reg_nl2dgsigmay3.field.gsy3 & ~m_tmp);
			break;

		case 0x20B0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y4(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay4.field.gsy4 = (d_tmp & m_tmp) | (reg_nl2dgsigmay4.field.gsy4 & ~m_tmp);
			break;

		case 0x20B4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y5(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay5.field.gsy5 = (d_tmp & m_tmp) | (reg_nl2dgsigmay5.field.gsy5 & ~m_tmp);
			break;

		case 0x20B8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y6(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay6.field.gsy6 = (d_tmp & m_tmp) | (reg_nl2dgsigmay6.field.gsy6 & ~m_tmp);
			break;

		case 0x20BC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y7(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay7.field.gsy7 = (d_tmp & m_tmp) | (reg_nl2dgsigmay7.field.gsy7 & ~m_tmp);
			break;

		case 0x20C0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y8(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay8.field.gsy8 = (d_tmp & m_tmp) | (reg_nl2dgsigmay8.field.gsy8 & ~m_tmp);
			break;

		case 0x20C4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y9(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay9.field.gsy9 = (d_tmp & m_tmp) | (reg_nl2dgsigmay9.field.gsy9 & ~m_tmp);
			break;

		case 0x20C8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y10(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay10.field.gsy10 = (d_tmp & m_tmp) | (reg_nl2dgsigmay10.field.gsy10 & ~m_tmp);
			break;

		case 0x20CC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y11(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay11.field.gsy11 = (d_tmp & m_tmp) | (reg_nl2dgsigmay11.field.gsy11 & ~m_tmp);
			break;

		case 0x20D0:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y12(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay12.field.gsy12 = (d_tmp & m_tmp) | (reg_nl2dgsigmay12.field.gsy12 & ~m_tmp);
			break;

		case 0x20D4:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y13(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay13.field.gsy13 = (d_tmp & m_tmp) | (reg_nl2dgsigmay13.field.gsy13 & ~m_tmp);
			break;

		case 0x20D8:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y14(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay14.field.gsy14 = (d_tmp & m_tmp) | (reg_nl2dgsigmay14.field.gsy14 & ~m_tmp);
			break;

		case 0x20DC:
			// Lsb: 0, Len: 14, [13:0] G Sigma Y15(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dgsigmay15.field.gsy15 = (d_tmp & m_tmp) | (reg_nl2dgsigmay15.field.gsy15 & ~m_tmp);
			break;

		case 0x20E0:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y0(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay0.field.bsy0 = (d_tmp & m_tmp) | (reg_nl2dbsigmay0.field.bsy0 & ~m_tmp);
			break;

		case 0x20E4:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y1(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay1.field.bsy1 = (d_tmp & m_tmp) | (reg_nl2dbsigmay1.field.bsy1 & ~m_tmp);
			break;

		case 0x20E8:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y2(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay2.field.bsy2 = (d_tmp & m_tmp) | (reg_nl2dbsigmay2.field.bsy2 & ~m_tmp);
			break;

		case 0x20EC:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y3(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay3.field.bsy3 = (d_tmp & m_tmp) | (reg_nl2dbsigmay3.field.bsy3 & ~m_tmp);
			break;

		case 0x20F0:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y4(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay4.field.bsy4 = (d_tmp & m_tmp) | (reg_nl2dbsigmay4.field.bsy4 & ~m_tmp);
			break;

		case 0x20F4:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y5(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay5.field.bsy5 = (d_tmp & m_tmp) | (reg_nl2dbsigmay5.field.bsy5 & ~m_tmp);
			break;

		case 0x20F8:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y6(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay6.field.bsy6 = (d_tmp & m_tmp) | (reg_nl2dbsigmay6.field.bsy6 & ~m_tmp);
			break;

		case 0x20FC:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y7(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay7.field.bsy7 = (d_tmp & m_tmp) | (reg_nl2dbsigmay7.field.bsy7 & ~m_tmp);
			break;

		case 0x2100:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y8(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay8.field.bsy8 = (d_tmp & m_tmp) | (reg_nl2dbsigmay8.field.bsy8 & ~m_tmp);
			break;

		case 0x2104:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y9(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay9.field.bsy9 = (d_tmp & m_tmp) | (reg_nl2dbsigmay9.field.bsy9 & ~m_tmp);
			break;

		case 0x2108:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y10(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay10.field.bsy10 = (d_tmp & m_tmp) | (reg_nl2dbsigmay10.field.bsy10 & ~m_tmp);
			break;

		case 0x210C:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y11(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay11.field.bsy11 = (d_tmp & m_tmp) | (reg_nl2dbsigmay11.field.bsy11 & ~m_tmp);
			break;

		case 0x2110:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y12(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay12.field.bsy12 = (d_tmp & m_tmp) | (reg_nl2dbsigmay12.field.bsy12 & ~m_tmp);
			break;

		case 0x2114:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y13(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay13.field.bsy13 = (d_tmp & m_tmp) | (reg_nl2dbsigmay13.field.bsy13 & ~m_tmp);
			break;

		case 0x2118:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y14(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay14.field.bsy14 = (d_tmp & m_tmp) | (reg_nl2dbsigmay14.field.bsy14 & ~m_tmp);
			break;

		case 0x211C:
			// Lsb: 0, Len: 14, [13:0] B Sigma Y15(0.14.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_nl2dbsigmay15.field.bsy15 = (d_tmp & m_tmp) | (reg_nl2dbsigmay15.field.bsy15 & ~m_tmp);
			break;

		case 0x2120:
			// Lsb: 0, Len: 16, [15:0] R Sigma S0(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas0.field.rss0 = (d_tmp & m_tmp) | (reg_nl2drsigmas0.field.rss0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S1(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas0.field.rss1 = (d_tmp & m_tmp) | (reg_nl2drsigmas0.field.rss1 & ~m_tmp);
			break;

		case 0x2124:
			// Lsb: 0, Len: 16, [15:0] R Sigma S2(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas1.field.rss2 = (d_tmp & m_tmp) | (reg_nl2drsigmas1.field.rss2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S3(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas1.field.rss3 = (d_tmp & m_tmp) | (reg_nl2drsigmas1.field.rss3 & ~m_tmp);
			break;

		case 0x2128:
			// Lsb: 0, Len: 16, [15:0] R Sigma S4(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas2.field.rss4 = (d_tmp & m_tmp) | (reg_nl2drsigmas2.field.rss4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S5(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas2.field.rss5 = (d_tmp & m_tmp) | (reg_nl2drsigmas2.field.rss5 & ~m_tmp);
			break;

		case 0x212C:
			// Lsb: 0, Len: 16, [15:0] R Sigma S6(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas3.field.rss6 = (d_tmp & m_tmp) | (reg_nl2drsigmas3.field.rss6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S7(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas3.field.rss7 = (d_tmp & m_tmp) | (reg_nl2drsigmas3.field.rss7 & ~m_tmp);
			break;

		case 0x2130:
			// Lsb: 0, Len: 16, [15:0] R Sigma S8(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas4.field.rss8 = (d_tmp & m_tmp) | (reg_nl2drsigmas4.field.rss8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S9(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas4.field.rss9 = (d_tmp & m_tmp) | (reg_nl2drsigmas4.field.rss9 & ~m_tmp);
			break;

		case 0x2134:
			// Lsb: 0, Len: 16, [15:0] R Sigma S10(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas5.field.rss10 = (d_tmp & m_tmp) | (reg_nl2drsigmas5.field.rss10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S11(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas5.field.rss11 = (d_tmp & m_tmp) | (reg_nl2drsigmas5.field.rss11 & ~m_tmp);
			break;

		case 0x2138:
			// Lsb: 0, Len: 16, [15:0] R Sigma S12(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas6.field.rss12 = (d_tmp & m_tmp) | (reg_nl2drsigmas6.field.rss12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S13(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas6.field.rss13 = (d_tmp & m_tmp) | (reg_nl2drsigmas6.field.rss13 & ~m_tmp);
			break;

		case 0x213C:
			// Lsb: 0, Len: 16, [15:0] R Sigma S14(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drsigmas7.field.rss14 = (d_tmp & m_tmp) | (reg_nl2drsigmas7.field.rss14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Sigma S15(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drsigmas7.field.rss15 = (d_tmp & m_tmp) | (reg_nl2drsigmas7.field.rss15 & ~m_tmp);
			break;

		case 0x2140:
			// Lsb: 0, Len: 16, [15:0] G Sigma S0(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas0.field.gss0 = (d_tmp & m_tmp) | (reg_nl2dgsigmas0.field.gss0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S1(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas0.field.gss1 = (d_tmp & m_tmp) | (reg_nl2dgsigmas0.field.gss1 & ~m_tmp);
			break;

		case 0x2144:
			// Lsb: 0, Len: 16, [15:0] G Sigma S2(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas1.field.gss2 = (d_tmp & m_tmp) | (reg_nl2dgsigmas1.field.gss2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S3(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas1.field.gss3 = (d_tmp & m_tmp) | (reg_nl2dgsigmas1.field.gss3 & ~m_tmp);
			break;

		case 0x2148:
			// Lsb: 0, Len: 16, [15:0] G Sigma S4(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas2.field.gss4 = (d_tmp & m_tmp) | (reg_nl2dgsigmas2.field.gss4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S5(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas2.field.gss5 = (d_tmp & m_tmp) | (reg_nl2dgsigmas2.field.gss5 & ~m_tmp);
			break;

		case 0x214C:
			// Lsb: 0, Len: 16, [15:0] G Sigma S6(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas3.field.gss6 = (d_tmp & m_tmp) | (reg_nl2dgsigmas3.field.gss6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S7(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas3.field.gss7 = (d_tmp & m_tmp) | (reg_nl2dgsigmas3.field.gss7 & ~m_tmp);
			break;

		case 0x2150:
			// Lsb: 0, Len: 16, [15:0] G Sigma S8(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas4.field.gss8 = (d_tmp & m_tmp) | (reg_nl2dgsigmas4.field.gss8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S9(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas4.field.gss9 = (d_tmp & m_tmp) | (reg_nl2dgsigmas4.field.gss9 & ~m_tmp);
			break;

		case 0x2154:
			// Lsb: 0, Len: 16, [15:0] G Sigma S10(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas5.field.gss10 = (d_tmp & m_tmp) | (reg_nl2dgsigmas5.field.gss10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S11(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas5.field.gss11 = (d_tmp & m_tmp) | (reg_nl2dgsigmas5.field.gss11 & ~m_tmp);
			break;

		case 0x2158:
			// Lsb: 0, Len: 16, [15:0] G Sigma S12(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas6.field.gss12 = (d_tmp & m_tmp) | (reg_nl2dgsigmas6.field.gss12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S13(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas6.field.gss13 = (d_tmp & m_tmp) | (reg_nl2dgsigmas6.field.gss13 & ~m_tmp);
			break;

		case 0x215C:
			// Lsb: 0, Len: 16, [15:0] G Sigma S14(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgsigmas7.field.gss14 = (d_tmp & m_tmp) | (reg_nl2dgsigmas7.field.gss14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Sigma S15(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgsigmas7.field.gss15 = (d_tmp & m_tmp) | (reg_nl2dgsigmas7.field.gss15 & ~m_tmp);
			break;

		case 0x2160:
			// Lsb: 0, Len: 16, [15:0] B Sigma S0(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas0.field.bss0 = (d_tmp & m_tmp) | (reg_nl2dbsigmas0.field.bss0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S1(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas0.field.bss1 = (d_tmp & m_tmp) | (reg_nl2dbsigmas0.field.bss1 & ~m_tmp);
			break;

		case 0x2164:
			// Lsb: 0, Len: 16, [15:0] B Sigma S2(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas1.field.bss2 = (d_tmp & m_tmp) | (reg_nl2dbsigmas1.field.bss2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S3(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas1.field.bss3 = (d_tmp & m_tmp) | (reg_nl2dbsigmas1.field.bss3 & ~m_tmp);
			break;

		case 0x2168:
			// Lsb: 0, Len: 16, [15:0] B Sigma S4(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas2.field.bss4 = (d_tmp & m_tmp) | (reg_nl2dbsigmas2.field.bss4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S5(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas2.field.bss5 = (d_tmp & m_tmp) | (reg_nl2dbsigmas2.field.bss5 & ~m_tmp);
			break;

		case 0x216C:
			// Lsb: 0, Len: 16, [15:0] B Sigma S6(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas3.field.bss6 = (d_tmp & m_tmp) | (reg_nl2dbsigmas3.field.bss6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S7(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas3.field.bss7 = (d_tmp & m_tmp) | (reg_nl2dbsigmas3.field.bss7 & ~m_tmp);
			break;

		case 0x2170:
			// Lsb: 0, Len: 16, [15:0] B Sigma S8(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas4.field.bss8 = (d_tmp & m_tmp) | (reg_nl2dbsigmas4.field.bss8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S9(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas4.field.bss9 = (d_tmp & m_tmp) | (reg_nl2dbsigmas4.field.bss9 & ~m_tmp);
			break;

		case 0x2174:
			// Lsb: 0, Len: 16, [15:0] B Sigma S10(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas5.field.bss10 = (d_tmp & m_tmp) | (reg_nl2dbsigmas5.field.bss10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S11(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas5.field.bss11 = (d_tmp & m_tmp) | (reg_nl2dbsigmas5.field.bss11 & ~m_tmp);
			break;

		case 0x2178:
			// Lsb: 0, Len: 16, [15:0] B Sigma S12(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas6.field.bss12 = (d_tmp & m_tmp) | (reg_nl2dbsigmas6.field.bss12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S13(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas6.field.bss13 = (d_tmp & m_tmp) | (reg_nl2dbsigmas6.field.bss13 & ~m_tmp);
			break;

		case 0x217C:
			// Lsb: 0, Len: 16, [15:0] B Sigma S14(1.8.7)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbsigmas7.field.bss14 = (d_tmp & m_tmp) | (reg_nl2dbsigmas7.field.bss14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Sigma S15(1.8.7)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbsigmas7.field.bss15 = (d_tmp & m_tmp) | (reg_nl2dbsigmas7.field.bss15 & ~m_tmp);
			break;

		case 0x2180:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx0.field.rfx0 = (d_tmp & m_tmp) | (reg_nl2drfiltparx0.field.rfx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx0.field.rfx1 = (d_tmp & m_tmp) | (reg_nl2drfiltparx0.field.rfx1 & ~m_tmp);
			break;

		case 0x2184:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx1.field.rfx2 = (d_tmp & m_tmp) | (reg_nl2drfiltparx1.field.rfx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx1.field.rfx3 = (d_tmp & m_tmp) | (reg_nl2drfiltparx1.field.rfx3 & ~m_tmp);
			break;

		case 0x2188:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx2.field.rfx4 = (d_tmp & m_tmp) | (reg_nl2drfiltparx2.field.rfx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx2.field.rfx5 = (d_tmp & m_tmp) | (reg_nl2drfiltparx2.field.rfx5 & ~m_tmp);
			break;

		case 0x218C:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx3.field.rfx6 = (d_tmp & m_tmp) | (reg_nl2drfiltparx3.field.rfx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx3.field.rfx7 = (d_tmp & m_tmp) | (reg_nl2drfiltparx3.field.rfx7 & ~m_tmp);
			break;

		case 0x2190:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx4.field.rfx8 = (d_tmp & m_tmp) | (reg_nl2drfiltparx4.field.rfx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx4.field.rfx9 = (d_tmp & m_tmp) | (reg_nl2drfiltparx4.field.rfx9 & ~m_tmp);
			break;

		case 0x2194:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx5.field.rfx10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx5.field.rfx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx5.field.rfx11 = (d_tmp & m_tmp) | (reg_nl2drfiltparx5.field.rfx11 & ~m_tmp);
			break;

		case 0x2198:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx6.field.rfx12 = (d_tmp & m_tmp) | (reg_nl2drfiltparx6.field.rfx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx6.field.rfx13 = (d_tmp & m_tmp) | (reg_nl2drfiltparx6.field.rfx13 & ~m_tmp);
			break;

		case 0x219C:
			// Lsb: 0, Len: 10, [9:0] R Filtpar X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2drfiltparx7.field.rfx14 = (d_tmp & m_tmp) | (reg_nl2drfiltparx7.field.rfx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2drfiltparx7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nl2drfiltparx7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] R Filtpar X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2drfiltparx7.field.rfx15 = (d_tmp & m_tmp) | (reg_nl2drfiltparx7.field.rfx15 & ~m_tmp);
			break;

		case 0x21A0:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx0.field.gfx0 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx0.field.gfx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx0.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx0.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx0.field.gfx1 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx0.field.gfx1 & ~m_tmp);
			break;

		case 0x21A4:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx1.field.gfx2 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx1.field.gfx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx1.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx1.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx1.field.gfx3 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx1.field.gfx3 & ~m_tmp);
			break;

		case 0x21A8:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx2.field.gfx4 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx2.field.gfx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx2.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx2.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx2.field.gfx5 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx2.field.gfx5 & ~m_tmp);
			break;

		case 0x21AC:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx3.field.gfx6 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx3.field.gfx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx3.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx3.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx3.field.gfx7 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx3.field.gfx7 & ~m_tmp);
			break;

		case 0x21B0:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx4.field.gfx8 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx4.field.gfx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx4.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx4.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx4.field.gfx9 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx4.field.gfx9 & ~m_tmp);
			break;

		case 0x21B4:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx5.field.gfx10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx5.field.gfx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx5.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx5.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx5.field.gfx11 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx5.field.gfx11 & ~m_tmp);
			break;

		case 0x21B8:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx6.field.gfx12 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx6.field.gfx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx6.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx6.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx6.field.gfx13 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx6.field.gfx13 & ~m_tmp);
			break;

		case 0x21BC:
			// Lsb: 0, Len: 10, [9:0] G Filtpar X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dgfiltparx7.field.gfx14 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx7.field.gfx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dgfiltparx7.field.gsvd10 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx7.field.gsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] G Filtpar X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dgfiltparx7.field.gfx15 = (d_tmp & m_tmp) | (reg_nl2dgfiltparx7.field.gfx15 & ~m_tmp);
			break;

		case 0x21C0:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx0.field.bfx0 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx0.field.bfx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx0.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx0.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx0.field.bfx1 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx0.field.bfx1 & ~m_tmp);
			break;

		case 0x21C4:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx1.field.bfx2 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx1.field.bfx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx1.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx1.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx1.field.bfx3 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx1.field.bfx3 & ~m_tmp);
			break;

		case 0x21C8:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx2.field.bfx4 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx2.field.bfx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx2.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx2.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx2.field.bfx5 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx2.field.bfx5 & ~m_tmp);
			break;

		case 0x21CC:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx3.field.bfx6 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx3.field.bfx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx3.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx3.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx3.field.bfx7 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx3.field.bfx7 & ~m_tmp);
			break;

		case 0x21D0:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx4.field.bfx8 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx4.field.bfx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx4.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx4.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx4.field.bfx9 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx4.field.bfx9 & ~m_tmp);
			break;

		case 0x21D4:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx5.field.bfx10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx5.field.bfx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx5.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx5.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx5.field.bfx11 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx5.field.bfx11 & ~m_tmp);
			break;

		case 0x21D8:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx6.field.bfx12 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx6.field.bfx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx6.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx6.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx6.field.bfx13 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx6.field.bfx13 & ~m_tmp);
			break;

		case 0x21DC:
			// Lsb: 0, Len: 10, [9:0] B Filtpar X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nl2dbfiltparx7.field.bfx14 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx7.field.bfx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nl2dbfiltparx7.field.bsvd10 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx7.field.bsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] B Filtpar X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nl2dbfiltparx7.field.bfx15 = (d_tmp & m_tmp) | (reg_nl2dbfiltparx7.field.bfx15 & ~m_tmp);
			break;

		case 0x21E0:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y0(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary0.field.rfy0 = (d_tmp & m_tmp) | (reg_nl2drfiltpary0.field.rfy0 & ~m_tmp);
			break;

		case 0x21E4:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y1(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary1.field.rfy1 = (d_tmp & m_tmp) | (reg_nl2drfiltpary1.field.rfy1 & ~m_tmp);
			break;

		case 0x21E8:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y2(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary2.field.rfy2 = (d_tmp & m_tmp) | (reg_nl2drfiltpary2.field.rfy2 & ~m_tmp);
			break;

		case 0x21EC:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y3(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary3.field.rfy3 = (d_tmp & m_tmp) | (reg_nl2drfiltpary3.field.rfy3 & ~m_tmp);
			break;

		case 0x21F0:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y4(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary4.field.rfy4 = (d_tmp & m_tmp) | (reg_nl2drfiltpary4.field.rfy4 & ~m_tmp);
			break;

		case 0x21F4:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y5(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary5.field.rfy5 = (d_tmp & m_tmp) | (reg_nl2drfiltpary5.field.rfy5 & ~m_tmp);
			break;

		case 0x21F8:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y6(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary6.field.rfy6 = (d_tmp & m_tmp) | (reg_nl2drfiltpary6.field.rfy6 & ~m_tmp);
			break;

		case 0x21FC:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y7(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary7.field.rfy7 = (d_tmp & m_tmp) | (reg_nl2drfiltpary7.field.rfy7 & ~m_tmp);
			break;

		case 0x2200:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y8(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary8.field.rfy8 = (d_tmp & m_tmp) | (reg_nl2drfiltpary8.field.rfy8 & ~m_tmp);
			break;

		case 0x2204:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y9(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary9.field.rfy9 = (d_tmp & m_tmp) | (reg_nl2drfiltpary9.field.rfy9 & ~m_tmp);
			break;

		case 0x2208:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y10(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary10.field.rfy10 = (d_tmp & m_tmp) | (reg_nl2drfiltpary10.field.rfy10 & ~m_tmp);
			break;

		case 0x220C:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y11(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary11.field.rfy11 = (d_tmp & m_tmp) | (reg_nl2drfiltpary11.field.rfy11 & ~m_tmp);
			break;

		case 0x2210:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y12(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary12.field.rfy12 = (d_tmp & m_tmp) | (reg_nl2drfiltpary12.field.rfy12 & ~m_tmp);
			break;

		case 0x2214:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y13(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary13.field.rfy13 = (d_tmp & m_tmp) | (reg_nl2drfiltpary13.field.rfy13 & ~m_tmp);
			break;

		case 0x2218:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y14(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary14.field.rfy14 = (d_tmp & m_tmp) | (reg_nl2drfiltpary14.field.rfy14 & ~m_tmp);
			break;

		case 0x221C:
			// Lsb: 0, Len: 22, [21:0] R Filtpar Y15(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2drfiltpary15.field.rfy15 = (d_tmp & m_tmp) | (reg_nl2drfiltpary15.field.rfy15 & ~m_tmp);
			break;

		case 0x2220:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y0(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary0.field.gfy0 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary0.field.gfy0 & ~m_tmp);
			break;

		case 0x2224:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y1(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary1.field.gfy1 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary1.field.gfy1 & ~m_tmp);
			break;

		case 0x2228:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y2(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary2.field.gfy2 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary2.field.gfy2 & ~m_tmp);
			break;

		case 0x222C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y3(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary3.field.gfy3 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary3.field.gfy3 & ~m_tmp);
			break;

		case 0x2230:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y4(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary4.field.gfy4 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary4.field.gfy4 & ~m_tmp);
			break;

		case 0x2234:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y5(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary5.field.gfy5 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary5.field.gfy5 & ~m_tmp);
			break;

		case 0x2238:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y6(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary6.field.gfy6 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary6.field.gfy6 & ~m_tmp);
			break;

		case 0x223C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y7(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary7.field.gfy7 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary7.field.gfy7 & ~m_tmp);
			break;

		case 0x2240:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y8(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary8.field.gfy8 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary8.field.gfy8 & ~m_tmp);
			break;

		case 0x2244:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y9(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary9.field.gfy9 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary9.field.gfy9 & ~m_tmp);
			break;

		case 0x2248:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y10(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary10.field.gfy10 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary10.field.gfy10 & ~m_tmp);
			break;

		case 0x224C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y11(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary11.field.gfy11 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary11.field.gfy11 & ~m_tmp);
			break;

		case 0x2250:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y12(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary12.field.gfy12 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary12.field.gfy12 & ~m_tmp);
			break;

		case 0x2254:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y13(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary13.field.gfy13 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary13.field.gfy13 & ~m_tmp);
			break;

		case 0x2258:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y14(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary14.field.gfy14 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary14.field.gfy14 & ~m_tmp);
			break;

		case 0x225C:
			// Lsb: 0, Len: 22, [21:0] G Filtpar Y15(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dgfiltpary15.field.gfy15 = (d_tmp & m_tmp) | (reg_nl2dgfiltpary15.field.gfy15 & ~m_tmp);
			break;

		case 0x2260:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y0(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary0.field.bfy0 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary0.field.bfy0 & ~m_tmp);
			break;

		case 0x2264:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y1(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary1.field.bfy1 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary1.field.bfy1 & ~m_tmp);
			break;

		case 0x2268:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y2(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary2.field.bfy2 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary2.field.bfy2 & ~m_tmp);
			break;

		case 0x226C:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y3(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary3.field.bfy3 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary3.field.bfy3 & ~m_tmp);
			break;

		case 0x2270:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y4(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary4.field.bfy4 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary4.field.bfy4 & ~m_tmp);
			break;

		case 0x2274:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y5(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary5.field.bfy5 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary5.field.bfy5 & ~m_tmp);
			break;

		case 0x2278:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y6(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary6.field.bfy6 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary6.field.bfy6 & ~m_tmp);
			break;

		case 0x227C:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y7(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary7.field.bfy7 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary7.field.bfy7 & ~m_tmp);
			break;

		case 0x2280:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y8(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary8.field.bfy8 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary8.field.bfy8 & ~m_tmp);
			break;

		case 0x2284:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y9(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary9.field.bfy9 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary9.field.bfy9 & ~m_tmp);
			break;

		case 0x2288:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y10(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary10.field.bfy10 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary10.field.bfy10 & ~m_tmp);
			break;

		case 0x228C:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y11(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary11.field.bfy11 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary11.field.bfy11 & ~m_tmp);
			break;

		case 0x2290:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y12(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary12.field.bfy12 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary12.field.bfy12 & ~m_tmp);
			break;

		case 0x2294:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y13(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary13.field.bfy13 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary13.field.bfy13 & ~m_tmp);
			break;

		case 0x2298:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y14(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary14.field.bfy14 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary14.field.bfy14 & ~m_tmp);
			break;

		case 0x229C:
			// Lsb: 0, Len: 22, [21:0] B Filtpar Y15(0.14.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_nl2dbfiltpary15.field.bfy15 = (d_tmp & m_tmp) | (reg_nl2dbfiltpary15.field.bfy15 & ~m_tmp);
			break;

		case 0x22A0:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S0(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars0.field.rfs0 = (d_tmp & m_tmp) | (reg_nl2drfiltpars0.field.rfs0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S1(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars0.field.rfs1 = (d_tmp & m_tmp) | (reg_nl2drfiltpars0.field.rfs1 & ~m_tmp);
			break;

		case 0x22A4:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S2(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars1.field.rfs2 = (d_tmp & m_tmp) | (reg_nl2drfiltpars1.field.rfs2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S3(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars1.field.rfs3 = (d_tmp & m_tmp) | (reg_nl2drfiltpars1.field.rfs3 & ~m_tmp);
			break;

		case 0x22A8:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S4(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars2.field.rfs4 = (d_tmp & m_tmp) | (reg_nl2drfiltpars2.field.rfs4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S5(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars2.field.rfs5 = (d_tmp & m_tmp) | (reg_nl2drfiltpars2.field.rfs5 & ~m_tmp);
			break;

		case 0x22AC:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S6(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars3.field.rfs6 = (d_tmp & m_tmp) | (reg_nl2drfiltpars3.field.rfs6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S7(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars3.field.rfs7 = (d_tmp & m_tmp) | (reg_nl2drfiltpars3.field.rfs7 & ~m_tmp);
			break;

		case 0x22B0:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S8(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars4.field.rfs8 = (d_tmp & m_tmp) | (reg_nl2drfiltpars4.field.rfs8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S9(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars4.field.rfs9 = (d_tmp & m_tmp) | (reg_nl2drfiltpars4.field.rfs9 & ~m_tmp);
			break;

		case 0x22B4:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S10(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars5.field.rfs10 = (d_tmp & m_tmp) | (reg_nl2drfiltpars5.field.rfs10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S11(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars5.field.rfs11 = (d_tmp & m_tmp) | (reg_nl2drfiltpars5.field.rfs11 & ~m_tmp);
			break;

		case 0x22B8:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S12(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars6.field.rfs12 = (d_tmp & m_tmp) | (reg_nl2drfiltpars6.field.rfs12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S13(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars6.field.rfs13 = (d_tmp & m_tmp) | (reg_nl2drfiltpars6.field.rfs13 & ~m_tmp);
			break;

		case 0x22BC:
			// Lsb: 0, Len: 16, [15:0] R Filtpar S14(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2drfiltpars7.field.rfs14 = (d_tmp & m_tmp) | (reg_nl2drfiltpars7.field.rfs14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] R Filtpar S15(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2drfiltpars7.field.rfs15 = (d_tmp & m_tmp) | (reg_nl2drfiltpars7.field.rfs15 & ~m_tmp);
			break;

		case 0x22C0:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S0(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars0.field.gfs0 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars0.field.gfs0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S1(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars0.field.gfs1 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars0.field.gfs1 & ~m_tmp);
			break;

		case 0x22C4:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S2(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars1.field.gfs2 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars1.field.gfs2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S3(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars1.field.gfs3 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars1.field.gfs3 & ~m_tmp);
			break;

		case 0x22C8:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S4(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars2.field.gfs4 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars2.field.gfs4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S5(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars2.field.gfs5 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars2.field.gfs5 & ~m_tmp);
			break;

		case 0x22CC:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S6(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars3.field.gfs6 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars3.field.gfs6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S7(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars3.field.gfs7 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars3.field.gfs7 & ~m_tmp);
			break;

		case 0x22D0:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S8(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars4.field.gfs8 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars4.field.gfs8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S9(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars4.field.gfs9 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars4.field.gfs9 & ~m_tmp);
			break;

		case 0x22D4:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S10(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars5.field.gfs10 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars5.field.gfs10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S11(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars5.field.gfs11 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars5.field.gfs11 & ~m_tmp);
			break;

		case 0x22D8:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S12(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars6.field.gfs12 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars6.field.gfs12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S13(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars6.field.gfs13 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars6.field.gfs13 & ~m_tmp);
			break;

		case 0x22DC:
			// Lsb: 0, Len: 16, [15:0] G Filtpar S14(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dgfiltpars7.field.gfs14 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars7.field.gfs14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] G Filtpar S15(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dgfiltpars7.field.gfs15 = (d_tmp & m_tmp) | (reg_nl2dgfiltpars7.field.gfs15 & ~m_tmp);
			break;

		case 0x22E0:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S0(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars0.field.bfs0 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars0.field.bfs0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S1(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars0.field.bfs1 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars0.field.bfs1 & ~m_tmp);
			break;

		case 0x22E4:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S2(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars1.field.bfs2 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars1.field.bfs2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S3(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars1.field.bfs3 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars1.field.bfs3 & ~m_tmp);
			break;

		case 0x22E8:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S4(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars2.field.bfs4 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars2.field.bfs4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S5(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars2.field.bfs5 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars2.field.bfs5 & ~m_tmp);
			break;

		case 0x22EC:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S6(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars3.field.bfs6 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars3.field.bfs6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S7(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars3.field.bfs7 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars3.field.bfs7 & ~m_tmp);
			break;

		case 0x22F0:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S8(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars4.field.bfs8 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars4.field.bfs8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S9(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars4.field.bfs9 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars4.field.bfs9 & ~m_tmp);
			break;

		case 0x22F4:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S10(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars5.field.bfs10 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars5.field.bfs10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S11(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars5.field.bfs11 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars5.field.bfs11 & ~m_tmp);
			break;

		case 0x22F8:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S12(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars6.field.bfs12 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars6.field.bfs12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S13(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars6.field.bfs13 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars6.field.bfs13 & ~m_tmp);
			break;

		case 0x22FC:
			// Lsb: 0, Len: 16, [15:0] B Filtpar S14(1.9.6)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_nl2dbfiltpars7.field.bfs14 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars7.field.bfs14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] B Filtpar S15(1.9.6)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_nl2dbfiltpars7.field.bfs15 = (d_tmp & m_tmp) | (reg_nl2dbfiltpars7.field.bfs15 & ~m_tmp);
			break;

		case 0x2300:
			// Lsb: 0, Len: 2, [1:0] TL - Top Left(read-only)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_nl2dcfg.field.rsvd0 = (d_tmp & m_tmp) | (reg_nl2dcfg.field.rsvd0 & ~m_tmp);

			// Lsb: 2, Len: 2, [3:2] TR - Top Right(read-only)
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000003;
			reg_nl2dcfg.field.rsvd2 = (d_tmp & m_tmp) | (reg_nl2dcfg.field.rsvd2 & ~m_tmp);

			// Lsb: 4, Len: 2, [5:4] BL - Bottom Left(read-only)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000003;
			reg_nl2dcfg.field.rsvd4 = (d_tmp & m_tmp) | (reg_nl2dcfg.field.rsvd4 & ~m_tmp);

			// Lsb: 6, Len: 2, [7:6] BR - Bottom Right(read-only)
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000003;
			reg_nl2dcfg.field.rsvd6 = (d_tmp & m_tmp) | (reg_nl2dcfg.field.rsvd6 & ~m_tmp);

			// Lsb: 8, Len: 9, [16:8] min W
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000001FF;
			reg_nl2dcfg.field.minw = (d_tmp & m_tmp) | (reg_nl2dcfg.field.minw & ~m_tmp);

			// Lsb: 17, Len: 3, [19:17] shift
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000007;
			reg_nl2dcfg.field.shift = (d_tmp & m_tmp) | (reg_nl2dcfg.field.shift & ~m_tmp);
			break;

		case 0x2400:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx0.field.ytx0 = (d_tmp & m_tmp) | (reg_nwedys1thx0.field.ytx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx0.field.ytx1 = (d_tmp & m_tmp) | (reg_nwedys1thx0.field.ytx1 & ~m_tmp);
			break;

		case 0x2404:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx1.field.ytx2 = (d_tmp & m_tmp) | (reg_nwedys1thx1.field.ytx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx1.field.ytx3 = (d_tmp & m_tmp) | (reg_nwedys1thx1.field.ytx3 & ~m_tmp);
			break;

		case 0x2408:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx2.field.ytx4 = (d_tmp & m_tmp) | (reg_nwedys1thx2.field.ytx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx2.field.ytx5 = (d_tmp & m_tmp) | (reg_nwedys1thx2.field.ytx5 & ~m_tmp);
			break;

		case 0x240C:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx3.field.ytx6 = (d_tmp & m_tmp) | (reg_nwedys1thx3.field.ytx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx3.field.ytx7 = (d_tmp & m_tmp) | (reg_nwedys1thx3.field.ytx7 & ~m_tmp);
			break;

		case 0x2410:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx4.field.ytx8 = (d_tmp & m_tmp) | (reg_nwedys1thx4.field.ytx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx4.field.ytx9 = (d_tmp & m_tmp) | (reg_nwedys1thx4.field.ytx9 & ~m_tmp);
			break;

		case 0x2414:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx5.field.ytx10 = (d_tmp & m_tmp) | (reg_nwedys1thx5.field.ytx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx5.field.ytx11 = (d_tmp & m_tmp) | (reg_nwedys1thx5.field.ytx11 & ~m_tmp);
			break;

		case 0x2418:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx6.field.ytx12 = (d_tmp & m_tmp) | (reg_nwedys1thx6.field.ytx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx6.field.ytx13 = (d_tmp & m_tmp) | (reg_nwedys1thx6.field.ytx13 & ~m_tmp);
			break;

		case 0x241C:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thx7.field.ytx14 = (d_tmp & m_tmp) | (reg_nwedys1thx7.field.ytx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thx7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thx7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thx7.field.ytx15 = (d_tmp & m_tmp) | (reg_nwedys1thx7.field.ytx15 & ~m_tmp);
			break;

		case 0x2420:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx0.field.ytx0 = (d_tmp & m_tmp) | (reg_nwedys6thx0.field.ytx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx0.field.ytx1 = (d_tmp & m_tmp) | (reg_nwedys6thx0.field.ytx1 & ~m_tmp);
			break;

		case 0x2424:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx1.field.ytx2 = (d_tmp & m_tmp) | (reg_nwedys6thx1.field.ytx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx1.field.ytx3 = (d_tmp & m_tmp) | (reg_nwedys6thx1.field.ytx3 & ~m_tmp);
			break;

		case 0x2428:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx2.field.ytx4 = (d_tmp & m_tmp) | (reg_nwedys6thx2.field.ytx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx2.field.ytx5 = (d_tmp & m_tmp) | (reg_nwedys6thx2.field.ytx5 & ~m_tmp);
			break;

		case 0x242C:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx3.field.ytx6 = (d_tmp & m_tmp) | (reg_nwedys6thx3.field.ytx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx3.field.ytx7 = (d_tmp & m_tmp) | (reg_nwedys6thx3.field.ytx7 & ~m_tmp);
			break;

		case 0x2430:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx4.field.ytx8 = (d_tmp & m_tmp) | (reg_nwedys6thx4.field.ytx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx4.field.ytx9 = (d_tmp & m_tmp) | (reg_nwedys6thx4.field.ytx9 & ~m_tmp);
			break;

		case 0x2434:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx5.field.ytx10 = (d_tmp & m_tmp) | (reg_nwedys6thx5.field.ytx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx5.field.ytx11 = (d_tmp & m_tmp) | (reg_nwedys6thx5.field.ytx11 & ~m_tmp);
			break;

		case 0x2438:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx6.field.ytx12 = (d_tmp & m_tmp) | (reg_nwedys6thx6.field.ytx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx6.field.ytx13 = (d_tmp & m_tmp) | (reg_nwedys6thx6.field.ytx13 & ~m_tmp);
			break;

		case 0x243C:
			// Lsb: 0, Len: 10, [9:0] Y Threshold X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thx7.field.ytx14 = (d_tmp & m_tmp) | (reg_nwedys6thx7.field.ytx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thx7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thx7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thx7.field.ytx15 = (d_tmp & m_tmp) | (reg_nwedys6thx7.field.ytx15 & ~m_tmp);
			break;

		case 0x2440:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx0.field.uvtx0 = (d_tmp & m_tmp) | (reg_nweduvs1thx0.field.uvtx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx0.field.uvtx1 = (d_tmp & m_tmp) | (reg_nweduvs1thx0.field.uvtx1 & ~m_tmp);
			break;

		case 0x2444:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx1.field.uvtx2 = (d_tmp & m_tmp) | (reg_nweduvs1thx1.field.uvtx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx1.field.uvtx3 = (d_tmp & m_tmp) | (reg_nweduvs1thx1.field.uvtx3 & ~m_tmp);
			break;

		case 0x2448:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx2.field.uvtx4 = (d_tmp & m_tmp) | (reg_nweduvs1thx2.field.uvtx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx2.field.uvtx5 = (d_tmp & m_tmp) | (reg_nweduvs1thx2.field.uvtx5 & ~m_tmp);
			break;

		case 0x244C:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx3.field.uvtx6 = (d_tmp & m_tmp) | (reg_nweduvs1thx3.field.uvtx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx3.field.uvtx7 = (d_tmp & m_tmp) | (reg_nweduvs1thx3.field.uvtx7 & ~m_tmp);
			break;

		case 0x2450:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx4.field.uvtx8 = (d_tmp & m_tmp) | (reg_nweduvs1thx4.field.uvtx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx4.field.uvtx9 = (d_tmp & m_tmp) | (reg_nweduvs1thx4.field.uvtx9 & ~m_tmp);
			break;

		case 0x2454:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx5.field.uvtx10 = (d_tmp & m_tmp) | (reg_nweduvs1thx5.field.uvtx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx5.field.uvtx11 = (d_tmp & m_tmp) | (reg_nweduvs1thx5.field.uvtx11 & ~m_tmp);
			break;

		case 0x2458:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx6.field.uvtx12 = (d_tmp & m_tmp) | (reg_nweduvs1thx6.field.uvtx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx6.field.uvtx13 = (d_tmp & m_tmp) | (reg_nweduvs1thx6.field.uvtx13 & ~m_tmp);
			break;

		case 0x245C:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thx7.field.uvtx14 = (d_tmp & m_tmp) | (reg_nweduvs1thx7.field.uvtx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thx7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thx7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thx7.field.uvtx15 = (d_tmp & m_tmp) | (reg_nweduvs1thx7.field.uvtx15 & ~m_tmp);
			break;

		case 0x2460:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx0.field.uvtx0 = (d_tmp & m_tmp) | (reg_nweduvs6thx0.field.uvtx0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx0.field.uvtx1 = (d_tmp & m_tmp) | (reg_nweduvs6thx0.field.uvtx1 & ~m_tmp);
			break;

		case 0x2464:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx1.field.uvtx2 = (d_tmp & m_tmp) | (reg_nweduvs6thx1.field.uvtx2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx1.field.uvtx3 = (d_tmp & m_tmp) | (reg_nweduvs6thx1.field.uvtx3 & ~m_tmp);
			break;

		case 0x2468:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx2.field.uvtx4 = (d_tmp & m_tmp) | (reg_nweduvs6thx2.field.uvtx4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx2.field.uvtx5 = (d_tmp & m_tmp) | (reg_nweduvs6thx2.field.uvtx5 & ~m_tmp);
			break;

		case 0x246C:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx3.field.uvtx6 = (d_tmp & m_tmp) | (reg_nweduvs6thx3.field.uvtx6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx3.field.uvtx7 = (d_tmp & m_tmp) | (reg_nweduvs6thx3.field.uvtx7 & ~m_tmp);
			break;

		case 0x2470:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx4.field.uvtx8 = (d_tmp & m_tmp) | (reg_nweduvs6thx4.field.uvtx8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx4.field.uvtx9 = (d_tmp & m_tmp) | (reg_nweduvs6thx4.field.uvtx9 & ~m_tmp);
			break;

		case 0x2474:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx5.field.uvtx10 = (d_tmp & m_tmp) | (reg_nweduvs6thx5.field.uvtx10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx5.field.uvtx11 = (d_tmp & m_tmp) | (reg_nweduvs6thx5.field.uvtx11 & ~m_tmp);
			break;

		case 0x2478:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx6.field.uvtx12 = (d_tmp & m_tmp) | (reg_nweduvs6thx6.field.uvtx12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx6.field.uvtx13 = (d_tmp & m_tmp) | (reg_nweduvs6thx6.field.uvtx13 & ~m_tmp);
			break;

		case 0x247C:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold X14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thx7.field.uvtx14 = (d_tmp & m_tmp) | (reg_nweduvs6thx7.field.uvtx14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thx7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thx7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold X15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thx7.field.uvtx15 = (d_tmp & m_tmp) | (reg_nweduvs6thx7.field.uvtx15 & ~m_tmp);
			break;

		case 0x2480:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy0.field.yty0 = (d_tmp & m_tmp) | (reg_nwedys1thy0.field.yty0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy0.field.yty1 = (d_tmp & m_tmp) | (reg_nwedys1thy0.field.yty1 & ~m_tmp);
			break;

		case 0x2484:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy1.field.yty2 = (d_tmp & m_tmp) | (reg_nwedys1thy1.field.yty2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy1.field.yty3 = (d_tmp & m_tmp) | (reg_nwedys1thy1.field.yty3 & ~m_tmp);
			break;

		case 0x2488:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy2.field.yty4 = (d_tmp & m_tmp) | (reg_nwedys1thy2.field.yty4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy2.field.yty5 = (d_tmp & m_tmp) | (reg_nwedys1thy2.field.yty5 & ~m_tmp);
			break;

		case 0x248C:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy3.field.yty6 = (d_tmp & m_tmp) | (reg_nwedys1thy3.field.yty6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy3.field.yty7 = (d_tmp & m_tmp) | (reg_nwedys1thy3.field.yty7 & ~m_tmp);
			break;

		case 0x2490:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy4.field.yty8 = (d_tmp & m_tmp) | (reg_nwedys1thy4.field.yty8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy4.field.yty9 = (d_tmp & m_tmp) | (reg_nwedys1thy4.field.yty9 & ~m_tmp);
			break;

		case 0x2494:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy5.field.yty10 = (d_tmp & m_tmp) | (reg_nwedys1thy5.field.yty10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy5.field.yty11 = (d_tmp & m_tmp) | (reg_nwedys1thy5.field.yty11 & ~m_tmp);
			break;

		case 0x2498:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy6.field.yty12 = (d_tmp & m_tmp) | (reg_nwedys1thy6.field.yty12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy6.field.yty13 = (d_tmp & m_tmp) | (reg_nwedys1thy6.field.yty13 & ~m_tmp);
			break;

		case 0x249C:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys1thy7.field.yty14 = (d_tmp & m_tmp) | (reg_nwedys1thy7.field.yty14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys1thy7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys1thy7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys1thy7.field.yty15 = (d_tmp & m_tmp) | (reg_nwedys1thy7.field.yty15 & ~m_tmp);
			break;

		case 0x24A0:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy0.field.yty0 = (d_tmp & m_tmp) | (reg_nwedys6thy0.field.yty0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy0.field.yty1 = (d_tmp & m_tmp) | (reg_nwedys6thy0.field.yty1 & ~m_tmp);
			break;

		case 0x24A4:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy1.field.yty2 = (d_tmp & m_tmp) | (reg_nwedys6thy1.field.yty2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy1.field.yty3 = (d_tmp & m_tmp) | (reg_nwedys6thy1.field.yty3 & ~m_tmp);
			break;

		case 0x24A8:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy2.field.yty4 = (d_tmp & m_tmp) | (reg_nwedys6thy2.field.yty4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy2.field.yty5 = (d_tmp & m_tmp) | (reg_nwedys6thy2.field.yty5 & ~m_tmp);
			break;

		case 0x24AC:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy3.field.yty6 = (d_tmp & m_tmp) | (reg_nwedys6thy3.field.yty6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy3.field.yty7 = (d_tmp & m_tmp) | (reg_nwedys6thy3.field.yty7 & ~m_tmp);
			break;

		case 0x24B0:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy4.field.yty8 = (d_tmp & m_tmp) | (reg_nwedys6thy4.field.yty8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy4.field.yty9 = (d_tmp & m_tmp) | (reg_nwedys6thy4.field.yty9 & ~m_tmp);
			break;

		case 0x24B4:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy5.field.yty10 = (d_tmp & m_tmp) | (reg_nwedys6thy5.field.yty10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy5.field.yty11 = (d_tmp & m_tmp) | (reg_nwedys6thy5.field.yty11 & ~m_tmp);
			break;

		case 0x24B8:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy6.field.yty12 = (d_tmp & m_tmp) | (reg_nwedys6thy6.field.yty12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy6.field.yty13 = (d_tmp & m_tmp) | (reg_nwedys6thy6.field.yty13 & ~m_tmp);
			break;

		case 0x24BC:
			// Lsb: 0, Len: 10, [9:0] Y Threshold Y14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nwedys6thy7.field.yty14 = (d_tmp & m_tmp) | (reg_nwedys6thy7.field.yty14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nwedys6thy7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nwedys6thy7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Y Threshold Y15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nwedys6thy7.field.yty15 = (d_tmp & m_tmp) | (reg_nwedys6thy7.field.yty15 & ~m_tmp);
			break;

		case 0x24C0:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy0.field.uvty0 = (d_tmp & m_tmp) | (reg_nweduvs1thy0.field.uvty0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy0.field.uvty1 = (d_tmp & m_tmp) | (reg_nweduvs1thy0.field.uvty1 & ~m_tmp);
			break;

		case 0x24C4:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy1.field.uvty2 = (d_tmp & m_tmp) | (reg_nweduvs1thy1.field.uvty2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy1.field.uvty3 = (d_tmp & m_tmp) | (reg_nweduvs1thy1.field.uvty3 & ~m_tmp);
			break;

		case 0x24C8:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy2.field.uvty4 = (d_tmp & m_tmp) | (reg_nweduvs1thy2.field.uvty4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy2.field.uvty5 = (d_tmp & m_tmp) | (reg_nweduvs1thy2.field.uvty5 & ~m_tmp);
			break;

		case 0x24CC:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy3.field.uvty6 = (d_tmp & m_tmp) | (reg_nweduvs1thy3.field.uvty6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy3.field.uvty7 = (d_tmp & m_tmp) | (reg_nweduvs1thy3.field.uvty7 & ~m_tmp);
			break;

		case 0x24D0:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy4.field.uvty8 = (d_tmp & m_tmp) | (reg_nweduvs1thy4.field.uvty8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy4.field.uvty9 = (d_tmp & m_tmp) | (reg_nweduvs1thy4.field.uvty9 & ~m_tmp);
			break;

		case 0x24D4:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy5.field.uvty10 = (d_tmp & m_tmp) | (reg_nweduvs1thy5.field.uvty10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy5.field.uvty11 = (d_tmp & m_tmp) | (reg_nweduvs1thy5.field.uvty11 & ~m_tmp);
			break;

		case 0x24D8:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy6.field.uvty12 = (d_tmp & m_tmp) | (reg_nweduvs1thy6.field.uvty12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy6.field.uvty13 = (d_tmp & m_tmp) | (reg_nweduvs1thy6.field.uvty13 & ~m_tmp);
			break;

		case 0x24DC:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs1thy7.field.uvty14 = (d_tmp & m_tmp) | (reg_nweduvs1thy7.field.uvty14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs1thy7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs1thy7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs1thy7.field.uvty15 = (d_tmp & m_tmp) | (reg_nweduvs1thy7.field.uvty15 & ~m_tmp);
			break;

		case 0x24E0:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y0(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy0.field.uvty0 = (d_tmp & m_tmp) | (reg_nweduvs6thy0.field.uvty0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy0.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y1(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy0.field.uvty1 = (d_tmp & m_tmp) | (reg_nweduvs6thy0.field.uvty1 & ~m_tmp);
			break;

		case 0x24E4:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y2(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy1.field.uvty2 = (d_tmp & m_tmp) | (reg_nweduvs6thy1.field.uvty2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy1.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y3(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy1.field.uvty3 = (d_tmp & m_tmp) | (reg_nweduvs6thy1.field.uvty3 & ~m_tmp);
			break;

		case 0x24E8:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y4(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy2.field.uvty4 = (d_tmp & m_tmp) | (reg_nweduvs6thy2.field.uvty4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy2.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y5(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy2.field.uvty5 = (d_tmp & m_tmp) | (reg_nweduvs6thy2.field.uvty5 & ~m_tmp);
			break;

		case 0x24EC:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y6(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy3.field.uvty6 = (d_tmp & m_tmp) | (reg_nweduvs6thy3.field.uvty6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy3.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y7(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy3.field.uvty7 = (d_tmp & m_tmp) | (reg_nweduvs6thy3.field.uvty7 & ~m_tmp);
			break;

		case 0x24F0:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y8(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy4.field.uvty8 = (d_tmp & m_tmp) | (reg_nweduvs6thy4.field.uvty8 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy4.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y9(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy4.field.uvty9 = (d_tmp & m_tmp) | (reg_nweduvs6thy4.field.uvty9 & ~m_tmp);
			break;

		case 0x24F4:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y10(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy5.field.uvty10 = (d_tmp & m_tmp) | (reg_nweduvs6thy5.field.uvty10 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy5.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y11(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy5.field.uvty11 = (d_tmp & m_tmp) | (reg_nweduvs6thy5.field.uvty11 & ~m_tmp);
			break;

		case 0x24F8:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y12(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy6.field.uvty12 = (d_tmp & m_tmp) | (reg_nweduvs6thy6.field.uvty12 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy6.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y13(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy6.field.uvty13 = (d_tmp & m_tmp) | (reg_nweduvs6thy6.field.uvty13 & ~m_tmp);
			break;

		case 0x24FC:
			// Lsb: 0, Len: 10, [9:0] UV  Threshold Y14(0.10.0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_nweduvs6thy7.field.uvty14 = (d_tmp & m_tmp) | (reg_nweduvs6thy7.field.uvty14 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_nweduvs6thy7.field.rsvd10 = (d_tmp & m_tmp) | (reg_nweduvs6thy7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] UV  Threshold Y15(0.10.0)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_nweduvs6thy7.field.uvty15 = (d_tmp & m_tmp) | (reg_nweduvs6thy7.field.uvty15 & ~m_tmp);
			break;

		case 0x2500:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S0(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths0.field.yts0 = (d_tmp & m_tmp) | (reg_nwedys1ths0.field.yts0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths0.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S1(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths0.field.yts1 = (d_tmp & m_tmp) | (reg_nwedys1ths0.field.yts1 & ~m_tmp);
			break;

		case 0x2504:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S2(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths1.field.yts2 = (d_tmp & m_tmp) | (reg_nwedys1ths1.field.yts2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths1.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S3(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths1.field.yts3 = (d_tmp & m_tmp) | (reg_nwedys1ths1.field.yts3 & ~m_tmp);
			break;

		case 0x2508:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S4(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths2.field.yts4 = (d_tmp & m_tmp) | (reg_nwedys1ths2.field.yts4 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths2.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S5(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths2.field.yts5 = (d_tmp & m_tmp) | (reg_nwedys1ths2.field.yts5 & ~m_tmp);
			break;

		case 0x250C:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S6(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths3.field.yts6 = (d_tmp & m_tmp) | (reg_nwedys1ths3.field.yts6 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths3.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S7(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths3.field.yts7 = (d_tmp & m_tmp) | (reg_nwedys1ths3.field.yts7 & ~m_tmp);
			break;

		case 0x2510:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S8(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths4.field.yts8 = (d_tmp & m_tmp) | (reg_nwedys1ths4.field.yts8 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths4.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths4.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S9(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths4.field.yts9 = (d_tmp & m_tmp) | (reg_nwedys1ths4.field.yts9 & ~m_tmp);
			break;

		case 0x2514:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S10(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths5.field.yts10 = (d_tmp & m_tmp) | (reg_nwedys1ths5.field.yts10 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths5.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths5.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S11(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths5.field.yts11 = (d_tmp & m_tmp) | (reg_nwedys1ths5.field.yts11 & ~m_tmp);
			break;

		case 0x2518:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S12(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths6.field.yts12 = (d_tmp & m_tmp) | (reg_nwedys1ths6.field.yts12 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths6.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths6.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S13(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths6.field.yts13 = (d_tmp & m_tmp) | (reg_nwedys1ths6.field.yts13 & ~m_tmp);
			break;

		case 0x251C:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S14(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys1ths7.field.yts14 = (d_tmp & m_tmp) | (reg_nwedys1ths7.field.yts14 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys1ths7.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys1ths7.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S15(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys1ths7.field.yts15 = (d_tmp & m_tmp) | (reg_nwedys1ths7.field.yts15 & ~m_tmp);
			break;

		case 0x2520:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S0(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths0.field.yts0 = (d_tmp & m_tmp) | (reg_nwedys6ths0.field.yts0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths0.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S1(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths0.field.yts1 = (d_tmp & m_tmp) | (reg_nwedys6ths0.field.yts1 & ~m_tmp);
			break;

		case 0x2524:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S2(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths1.field.yts2 = (d_tmp & m_tmp) | (reg_nwedys6ths1.field.yts2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths1.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S3(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths1.field.yts3 = (d_tmp & m_tmp) | (reg_nwedys6ths1.field.yts3 & ~m_tmp);
			break;

		case 0x2528:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S4(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths2.field.yts4 = (d_tmp & m_tmp) | (reg_nwedys6ths2.field.yts4 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths2.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S5(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths2.field.yts5 = (d_tmp & m_tmp) | (reg_nwedys6ths2.field.yts5 & ~m_tmp);
			break;

		case 0x252C:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S6(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths3.field.yts6 = (d_tmp & m_tmp) | (reg_nwedys6ths3.field.yts6 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths3.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S7(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths3.field.yts7 = (d_tmp & m_tmp) | (reg_nwedys6ths3.field.yts7 & ~m_tmp);
			break;

		case 0x2530:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S8(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths4.field.yts8 = (d_tmp & m_tmp) | (reg_nwedys6ths4.field.yts8 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths4.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths4.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S9(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths4.field.yts9 = (d_tmp & m_tmp) | (reg_nwedys6ths4.field.yts9 & ~m_tmp);
			break;

		case 0x2534:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S10(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths5.field.yts10 = (d_tmp & m_tmp) | (reg_nwedys6ths5.field.yts10 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths5.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths5.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S11(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths5.field.yts11 = (d_tmp & m_tmp) | (reg_nwedys6ths5.field.yts11 & ~m_tmp);
			break;

		case 0x2538:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S12(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths6.field.yts12 = (d_tmp & m_tmp) | (reg_nwedys6ths6.field.yts12 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths6.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths6.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S13(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths6.field.yts13 = (d_tmp & m_tmp) | (reg_nwedys6ths6.field.yts13 & ~m_tmp);
			break;

		case 0x253C:
			// Lsb: 0, Len: 13, [12:0] Y Threshold S14(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nwedys6ths7.field.yts14 = (d_tmp & m_tmp) | (reg_nwedys6ths7.field.yts14 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nwedys6ths7.field.rsvd13 = (d_tmp & m_tmp) | (reg_nwedys6ths7.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Y Threshold S15(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nwedys6ths7.field.yts15 = (d_tmp & m_tmp) | (reg_nwedys6ths7.field.yts15 & ~m_tmp);
			break;

		case 0x2540:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S0(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths0.field.uvts0 = (d_tmp & m_tmp) | (reg_nweduvs1ths0.field.uvts0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths0.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S1(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths0.field.uvts1 = (d_tmp & m_tmp) | (reg_nweduvs1ths0.field.uvts1 & ~m_tmp);
			break;

		case 0x2544:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S2(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths1.field.uvts2 = (d_tmp & m_tmp) | (reg_nweduvs1ths1.field.uvts2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths1.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S3(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths1.field.uvts3 = (d_tmp & m_tmp) | (reg_nweduvs1ths1.field.uvts3 & ~m_tmp);
			break;

		case 0x2548:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S4(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths2.field.uvts4 = (d_tmp & m_tmp) | (reg_nweduvs1ths2.field.uvts4 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths2.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S5(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths2.field.uvts5 = (d_tmp & m_tmp) | (reg_nweduvs1ths2.field.uvts5 & ~m_tmp);
			break;

		case 0x254C:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S6(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths3.field.uvts6 = (d_tmp & m_tmp) | (reg_nweduvs1ths3.field.uvts6 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths3.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S7(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths3.field.uvts7 = (d_tmp & m_tmp) | (reg_nweduvs1ths3.field.uvts7 & ~m_tmp);
			break;

		case 0x2550:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S8(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths4.field.uvts8 = (d_tmp & m_tmp) | (reg_nweduvs1ths4.field.uvts8 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths4.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths4.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S9(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths4.field.uvts9 = (d_tmp & m_tmp) | (reg_nweduvs1ths4.field.uvts9 & ~m_tmp);
			break;

		case 0x2554:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S10(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths5.field.uvts10 = (d_tmp & m_tmp) | (reg_nweduvs1ths5.field.uvts10 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths5.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths5.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S11(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths5.field.uvts11 = (d_tmp & m_tmp) | (reg_nweduvs1ths5.field.uvts11 & ~m_tmp);
			break;

		case 0x2558:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S12(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths6.field.uvts12 = (d_tmp & m_tmp) | (reg_nweduvs1ths6.field.uvts12 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths6.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths6.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S13(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths6.field.uvts13 = (d_tmp & m_tmp) | (reg_nweduvs1ths6.field.uvts13 & ~m_tmp);
			break;

		case 0x255C:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S14(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs1ths7.field.uvts14 = (d_tmp & m_tmp) | (reg_nweduvs1ths7.field.uvts14 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs1ths7.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs1ths7.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S15(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs1ths7.field.uvts15 = (d_tmp & m_tmp) | (reg_nweduvs1ths7.field.uvts15 & ~m_tmp);
			break;

		case 0x2560:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S0(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths0.field.uvts0 = (d_tmp & m_tmp) | (reg_nweduvs6ths0.field.uvts0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths0.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S1(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths0.field.uvts1 = (d_tmp & m_tmp) | (reg_nweduvs6ths0.field.uvts1 & ~m_tmp);
			break;

		case 0x2564:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S2(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths1.field.uvts2 = (d_tmp & m_tmp) | (reg_nweduvs6ths1.field.uvts2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths1.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S3(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths1.field.uvts3 = (d_tmp & m_tmp) | (reg_nweduvs6ths1.field.uvts3 & ~m_tmp);
			break;

		case 0x2568:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S4(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths2.field.uvts4 = (d_tmp & m_tmp) | (reg_nweduvs6ths2.field.uvts4 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths2.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S5(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths2.field.uvts5 = (d_tmp & m_tmp) | (reg_nweduvs6ths2.field.uvts5 & ~m_tmp);
			break;

		case 0x256C:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S6(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths3.field.uvts6 = (d_tmp & m_tmp) | (reg_nweduvs6ths3.field.uvts6 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths3.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S7(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths3.field.uvts7 = (d_tmp & m_tmp) | (reg_nweduvs6ths3.field.uvts7 & ~m_tmp);
			break;

		case 0x2570:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S8(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths4.field.uvts8 = (d_tmp & m_tmp) | (reg_nweduvs6ths4.field.uvts8 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths4.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths4.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S9(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths4.field.uvts9 = (d_tmp & m_tmp) | (reg_nweduvs6ths4.field.uvts9 & ~m_tmp);
			break;

		case 0x2574:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S10(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths5.field.uvts10 = (d_tmp & m_tmp) | (reg_nweduvs6ths5.field.uvts10 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths5.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths5.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S11(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths5.field.uvts11 = (d_tmp & m_tmp) | (reg_nweduvs6ths5.field.uvts11 & ~m_tmp);
			break;

		case 0x2578:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S12(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths6.field.uvts12 = (d_tmp & m_tmp) | (reg_nweduvs6ths6.field.uvts12 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths6.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths6.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S13(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths6.field.uvts13 = (d_tmp & m_tmp) | (reg_nweduvs6ths6.field.uvts13 & ~m_tmp);
			break;

		case 0x257C:
			// Lsb: 0, Len: 13, [12:0] UV Threshold S14(1.4.8)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_nweduvs6ths7.field.uvts14 = (d_tmp & m_tmp) | (reg_nweduvs6ths7.field.uvts14 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_nweduvs6ths7.field.rsvd13 = (d_tmp & m_tmp) | (reg_nweduvs6ths7.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] UV Threshold S15(1.4.8)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_nweduvs6ths7.field.uvts15 = (d_tmp & m_tmp) | (reg_nweduvs6ths7.field.uvts15 & ~m_tmp);
			break;

		case 0x2580:
			// Lsb: 0, Len: 8, [7:0] Scalars DS0(0.4.4)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_nwedds0.field.ds0 = (d_tmp & m_tmp) | (reg_nwedds0.field.ds0 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] Scalars DS1(0.4.4)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_nwedds0.field.ds1 = (d_tmp & m_tmp) | (reg_nwedds0.field.ds1 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] Scalars DS2(0.4.4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_nwedds0.field.ds2 = (d_tmp & m_tmp) | (reg_nwedds0.field.ds2 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] Scalars DS3(0.4.4)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_nwedds0.field.ds3 = (d_tmp & m_tmp) | (reg_nwedds0.field.ds3 & ~m_tmp);
			break;

		case 0x2584:
			// Lsb: 0, Len: 8, [7:0] Scalars DS4(0.4.4)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_nwedds1.field.ds4 = (d_tmp & m_tmp) | (reg_nwedds1.field.ds4 & ~m_tmp);

			// Lsb: 8, Len: 8, [15:8] Scalars DS5(0.4.4)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x000000FF;
			reg_nwedds1.field.ds5 = (d_tmp & m_tmp) | (reg_nwedds1.field.ds5 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] Scalars DS6(0.4.4)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_nwedds1.field.ds6 = (d_tmp & m_tmp) | (reg_nwedds1.field.ds6 & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] Scalars DS7(0.4.4)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_nwedds1.field.ds7 = (d_tmp & m_tmp) | (reg_nwedds1.field.ds7 & ~m_tmp);
			break;

		case 0x3030:
			// Lsb: 0, Len: 10, [9:0] [0.6/8/10.0] Offset at point A for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_obco_cfg_4.field.a_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_4.field.a_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_obco_cfg_4.field.rsvd10 = (d_tmp & m_tmp) | (reg_obco_cfg_4.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.6/8/10.0] Offset at point B for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_obco_cfg_4.field.b_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_4.field.b_s0 & ~m_tmp);
			break;

		case 0x3034:
			// Lsb: 0, Len: 10, [9:0] [0.6/8/10.0] Offset at point C for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_obco_cfg_5.field.c_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_5.field.c_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_obco_cfg_5.field.rsvd10 = (d_tmp & m_tmp) | (reg_obco_cfg_5.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.6/8/10.0] Offset at point D for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_obco_cfg_5.field.d_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_5.field.d_s0 & ~m_tmp);
			break;

		case 0x3038:
			// Lsb: 0, Len: 10, [9:0] [0.6/8/10.0] Offset at point A for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_obco_cfg_6.field.a_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_6.field.a_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_obco_cfg_6.field.rsvd10 = (d_tmp & m_tmp) | (reg_obco_cfg_6.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.6/8/10.0] Offset at point B for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_obco_cfg_6.field.b_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_6.field.b_s0 & ~m_tmp);
			break;

		case 0x303C:
			// Lsb: 0, Len: 10, [9:0] [0.6/8/10.0] Offset at point C for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_obco_cfg_7.field.c_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_7.field.c_s0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_obco_cfg_7.field.rsvd10 = (d_tmp & m_tmp) | (reg_obco_cfg_7.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.6/8/10.0] Offset at point D for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_obco_cfg_7.field.d_s0 = (d_tmp & m_tmp) | (reg_obco_cfg_7.field.d_s0 & ~m_tmp);
			break;

		case 0x3200:
			// Lsb: 0, Len: 14, [13:0] X0 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_0.field.x0_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_0.field.x0_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_0.field.x1_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_0.field.x1_s0 & ~m_tmp);
			break;

		case 0x3204:
			// Lsb: 0, Len: 14, [13:0] X2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_1.field.x2_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_1.field.x2_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_1.field.x3_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_1.field.x3_s0 & ~m_tmp);
			break;

		case 0x3208:
			// Lsb: 0, Len: 14, [13:0] X4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_2.field.x4_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_2.field.x4_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_2.field.x5_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_2.field.x5_s0 & ~m_tmp);
			break;

		case 0x320C:
			// Lsb: 0, Len: 14, [13:0] X6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_3.field.x6_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_3.field.x6_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_3.field.x7_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_3.field.x7_s0 & ~m_tmp);
			break;

		case 0x3210:
			// Lsb: 0, Len: 14, [13:0] X8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_4.field.x8_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_4.field.x8_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_4.field.x9_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_4.field.x9_s0 & ~m_tmp);
			break;

		case 0x3214:
			// Lsb: 0, Len: 14, [13:0] X10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_5.field.x10_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_5.field.x10_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_5.field.x11_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_5.field.x11_s0 & ~m_tmp);
			break;

		case 0x3218:
			// Lsb: 0, Len: 14, [13:0] X12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_6.field.x12_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_6.field.x12_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_6.field.x13_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_6.field.x13_s0 & ~m_tmp);
			break;

		case 0x321C:
			// Lsb: 0, Len: 14, [13:0] X14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x0_cfg_7.field.x14_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_7.field.x14_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x0_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x0_cfg_7.field.x15_s0 = (d_tmp & m_tmp) | (reg_oecfc_x0_cfg_7.field.x15_s0 & ~m_tmp);
			break;

		case 0x3220:
			// Lsb: 0, Len: 14, [13:0] X0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_0.field.x0_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_0.field.x0_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_0.field.x1_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_0.field.x1_s1 & ~m_tmp);
			break;

		case 0x3224:
			// Lsb: 0, Len: 14, [13:0] X2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_1.field.x2_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_1.field.x2_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_1.field.x3_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_1.field.x3_s1 & ~m_tmp);
			break;

		case 0x3228:
			// Lsb: 0, Len: 14, [13:0] X4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_2.field.x4_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_2.field.x4_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_2.field.x5_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_2.field.x5_s1 & ~m_tmp);
			break;

		case 0x322C:
			// Lsb: 0, Len: 14, [13:0] X6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_3.field.x6_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_3.field.x6_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_3.field.x7_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_3.field.x7_s1 & ~m_tmp);
			break;

		case 0x3230:
			// Lsb: 0, Len: 14, [13:0] X8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_4.field.x8_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_4.field.x8_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_4.field.x9_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_4.field.x9_s1 & ~m_tmp);
			break;

		case 0x3234:
			// Lsb: 0, Len: 14, [13:0] X10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_5.field.x10_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_5.field.x10_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_5.field.x11_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_5.field.x11_s1 & ~m_tmp);
			break;

		case 0x3238:
			// Lsb: 0, Len: 14, [13:0] X12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_6.field.x12_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_6.field.x12_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_6.field.x13_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_6.field.x13_s1 & ~m_tmp);
			break;

		case 0x323C:
			// Lsb: 0, Len: 14, [13:0] X14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x1_cfg_7.field.x14_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_7.field.x14_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x1_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x1_cfg_7.field.x15_s1 = (d_tmp & m_tmp) | (reg_oecfc_x1_cfg_7.field.x15_s1 & ~m_tmp);
			break;

		case 0x3240:
			// Lsb: 0, Len: 14, [13:0] X0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_0.field.x0_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_0.field.x0_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_0.field.x1_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_0.field.x1_s2 & ~m_tmp);
			break;

		case 0x3244:
			// Lsb: 0, Len: 14, [13:0] X2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_1.field.x2_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_1.field.x2_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_1.field.x3_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_1.field.x3_s2 & ~m_tmp);
			break;

		case 0x3248:
			// Lsb: 0, Len: 14, [13:0] X4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_2.field.x4_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_2.field.x4_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_2.field.x5_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_2.field.x5_s2 & ~m_tmp);
			break;

		case 0x324C:
			// Lsb: 0, Len: 14, [13:0] X6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_3.field.x6_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_3.field.x6_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_3.field.x7_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_3.field.x7_s2 & ~m_tmp);
			break;

		case 0x3250:
			// Lsb: 0, Len: 14, [13:0] X8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_4.field.x8_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_4.field.x8_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_4.field.x9_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_4.field.x9_s2 & ~m_tmp);
			break;

		case 0x3254:
			// Lsb: 0, Len: 14, [13:0] X10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_5.field.x10_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_5.field.x10_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_5.field.x11_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_5.field.x11_s2 & ~m_tmp);
			break;

		case 0x3258:
			// Lsb: 0, Len: 14, [13:0] X12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_6.field.x12_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_6.field.x12_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_6.field.x13_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_6.field.x13_s2 & ~m_tmp);
			break;

		case 0x325C:
			// Lsb: 0, Len: 14, [13:0] X14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x2_cfg_7.field.x14_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_7.field.x14_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x2_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x2_cfg_7.field.x15_s2 = (d_tmp & m_tmp) | (reg_oecfc_x2_cfg_7.field.x15_s2 & ~m_tmp);
			break;

		case 0x3260:
			// Lsb: 0, Len: 14, [13:0] X0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_0.field.x0_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_0.field.x0_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_0.field.x1_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_0.field.x1_s3 & ~m_tmp);
			break;

		case 0x3264:
			// Lsb: 0, Len: 14, [13:0] X2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_1.field.x2_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_1.field.x2_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_1.field.x3_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_1.field.x3_s3 & ~m_tmp);
			break;

		case 0x3268:
			// Lsb: 0, Len: 14, [13:0] X4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_2.field.x4_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_2.field.x4_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_2.field.x5_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_2.field.x5_s3 & ~m_tmp);
			break;

		case 0x326C:
			// Lsb: 0, Len: 14, [13:0] X6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_3.field.x6_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_3.field.x6_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_3.field.x7_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_3.field.x7_s3 & ~m_tmp);
			break;

		case 0x3270:
			// Lsb: 0, Len: 14, [13:0] X8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_4.field.x8_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_4.field.x8_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_4.field.x9_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_4.field.x9_s3 & ~m_tmp);
			break;

		case 0x3274:
			// Lsb: 0, Len: 14, [13:0] X10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_5.field.x10_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_5.field.x10_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_5.field.x11_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_5.field.x11_s3 & ~m_tmp);
			break;

		case 0x3278:
			// Lsb: 0, Len: 14, [13:0] X12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_6.field.x12_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_6.field.x12_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_6.field.x13_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_6.field.x13_s3 & ~m_tmp);
			break;

		case 0x327C:
			// Lsb: 0, Len: 14, [13:0] X14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_x3_cfg_7.field.x14_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_7.field.x14_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_x3_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] X15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_x3_cfg_7.field.x15_s3 = (d_tmp & m_tmp) | (reg_oecfc_x3_cfg_7.field.x15_s3 & ~m_tmp);
			break;

		case 0x3280:
			// Lsb: 0, Len: 14, [13:0] Y0 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_0.field.y0_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_0.field.y0_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_0.field.y1_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_0.field.y1_s0 & ~m_tmp);
			break;

		case 0x3284:
			// Lsb: 0, Len: 14, [13:0] Y2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_1.field.y2_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_1.field.y2_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_1.field.y3_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_1.field.y3_s0 & ~m_tmp);
			break;

		case 0x3288:
			// Lsb: 0, Len: 14, [13:0] Y4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_2.field.y4_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_2.field.y4_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_2.field.y5_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_2.field.y5_s0 & ~m_tmp);
			break;

		case 0x328C:
			// Lsb: 0, Len: 14, [13:0] Y6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_3.field.y6_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_3.field.y6_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_3.field.y7_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_3.field.y7_s0 & ~m_tmp);
			break;

		case 0x3290:
			// Lsb: 0, Len: 14, [13:0] Y8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_4.field.y8_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_4.field.y8_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_4.field.y9_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_4.field.y9_s0 & ~m_tmp);
			break;

		case 0x3294:
			// Lsb: 0, Len: 14, [13:0] Y10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_5.field.y10_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_5.field.y10_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_5.field.y11_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_5.field.y11_s0 & ~m_tmp);
			break;

		case 0x3298:
			// Lsb: 0, Len: 14, [13:0] Y12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_6.field.y12_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_6.field.y12_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_6.field.y13_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_6.field.y13_s0 & ~m_tmp);
			break;

		case 0x329C:
			// Lsb: 0, Len: 14, [13:0] Y14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y0_cfg_7.field.y14_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_7.field.y14_s0 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y0_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y0_cfg_7.field.y15_s0 = (d_tmp & m_tmp) | (reg_oecfc_y0_cfg_7.field.y15_s0 & ~m_tmp);
			break;

		case 0x32A0:
			// Lsb: 0, Len: 14, [13:0] Y0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_0.field.y0_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_0.field.y0_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_0.field.y1_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_0.field.y1_s1 & ~m_tmp);
			break;

		case 0x32A4:
			// Lsb: 0, Len: 14, [13:0] Y2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_1.field.y2_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_1.field.y2_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_1.field.y3_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_1.field.y3_s1 & ~m_tmp);
			break;

		case 0x32A8:
			// Lsb: 0, Len: 14, [13:0] Y4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_2.field.y4_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_2.field.y4_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_2.field.y5_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_2.field.y5_s1 & ~m_tmp);
			break;

		case 0x32AC:
			// Lsb: 0, Len: 14, [13:0] Y6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_3.field.y6_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_3.field.y6_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_3.field.y7_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_3.field.y7_s1 & ~m_tmp);
			break;

		case 0x32B0:
			// Lsb: 0, Len: 14, [13:0] Y8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_4.field.y8_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_4.field.y8_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_4.field.y9_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_4.field.y9_s1 & ~m_tmp);
			break;

		case 0x32B4:
			// Lsb: 0, Len: 14, [13:0] Y10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_5.field.y10_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_5.field.y10_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_5.field.y11_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_5.field.y11_s1 & ~m_tmp);
			break;

		case 0x32B8:
			// Lsb: 0, Len: 14, [13:0] Y12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_6.field.y12_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_6.field.y12_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_6.field.y13_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_6.field.y13_s1 & ~m_tmp);
			break;

		case 0x32BC:
			// Lsb: 0, Len: 14, [13:0] Y14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y1_cfg_7.field.y14_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_7.field.y14_s1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y1_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y1_cfg_7.field.y15_s1 = (d_tmp & m_tmp) | (reg_oecfc_y1_cfg_7.field.y15_s1 & ~m_tmp);
			break;

		case 0x32C0:
			// Lsb: 0, Len: 14, [13:0] Y0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_0.field.y0_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_0.field.y0_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_0.field.y1_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_0.field.y1_s2 & ~m_tmp);
			break;

		case 0x32C4:
			// Lsb: 0, Len: 14, [13:0] Y2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_1.field.y2_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_1.field.y2_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_1.field.y3_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_1.field.y3_s2 & ~m_tmp);
			break;

		case 0x32C8:
			// Lsb: 0, Len: 14, [13:0] Y4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_2.field.y4_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_2.field.y4_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_2.field.y5_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_2.field.y5_s2 & ~m_tmp);
			break;

		case 0x32CC:
			// Lsb: 0, Len: 14, [13:0] Y6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_3.field.y6_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_3.field.y6_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_3.field.y7_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_3.field.y7_s2 & ~m_tmp);
			break;

		case 0x32D0:
			// Lsb: 0, Len: 14, [13:0] Y8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_4.field.y8_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_4.field.y8_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_4.field.y9_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_4.field.y9_s2 & ~m_tmp);
			break;

		case 0x32D4:
			// Lsb: 0, Len: 14, [13:0] Y10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_5.field.y10_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_5.field.y10_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_5.field.y11_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_5.field.y11_s2 & ~m_tmp);
			break;

		case 0x32D8:
			// Lsb: 0, Len: 14, [13:0] Y12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_6.field.y12_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_6.field.y12_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_6.field.y13_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_6.field.y13_s2 & ~m_tmp);
			break;

		case 0x32DC:
			// Lsb: 0, Len: 14, [13:0] Y14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y2_cfg_7.field.y14_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_7.field.y14_s2 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y2_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y2_cfg_7.field.y15_s2 = (d_tmp & m_tmp) | (reg_oecfc_y2_cfg_7.field.y15_s2 & ~m_tmp);
			break;

		case 0x32E0:
			// Lsb: 0, Len: 14, [13:0] Y0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_0.field.y0_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_0.field.y0_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_0.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_0.field.y1_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_0.field.y1_s3 & ~m_tmp);
			break;

		case 0x32E4:
			// Lsb: 0, Len: 14, [13:0] Y2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_1.field.y2_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_1.field.y2_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_1.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_1.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_1.field.y3_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_1.field.y3_s3 & ~m_tmp);
			break;

		case 0x32E8:
			// Lsb: 0, Len: 14, [13:0] Y4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_2.field.y4_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_2.field.y4_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_2.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_2.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_2.field.y5_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_2.field.y5_s3 & ~m_tmp);
			break;

		case 0x32EC:
			// Lsb: 0, Len: 14, [13:0] Y6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_3.field.y6_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_3.field.y6_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_3.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_3.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_3.field.y7_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_3.field.y7_s3 & ~m_tmp);
			break;

		case 0x32F0:
			// Lsb: 0, Len: 14, [13:0] Y8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_4.field.y8_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_4.field.y8_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_4.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_4.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_4.field.y9_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_4.field.y9_s3 & ~m_tmp);
			break;

		case 0x32F4:
			// Lsb: 0, Len: 14, [13:0] Y10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_5.field.y10_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_5.field.y10_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_5.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_5.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_5.field.y11_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_5.field.y11_s3 & ~m_tmp);
			break;

		case 0x32F8:
			// Lsb: 0, Len: 14, [13:0] Y12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_6.field.y12_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_6.field.y12_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_6.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_6.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_6.field.y13_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_6.field.y13_s3 & ~m_tmp);
			break;

		case 0x32FC:
			// Lsb: 0, Len: 14, [13:0] Y14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_oecfc_y3_cfg_7.field.y14_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_7.field.y14_s3 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_oecfc_y3_cfg_7.field.rsvd14 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_7.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Y15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_oecfc_y3_cfg_7.field.y15_s3 = (d_tmp & m_tmp) | (reg_oecfc_y3_cfg_7.field.y15_s3 & ~m_tmp);
			break;

		case 0x3300:
			// Lsb: 0, Len: 16, [15:0] S0 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_0.field.s0_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_0.field.s0_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S1 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_0.field.s1_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_0.field.s1_s0 & ~m_tmp);
			break;

		case 0x3304:
			// Lsb: 0, Len: 16, [15:0] S2 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_1.field.s2_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_1.field.s2_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S3 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_1.field.s3_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_1.field.s3_s0 & ~m_tmp);
			break;

		case 0x3308:
			// Lsb: 0, Len: 16, [15:0] S4 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_2.field.s4_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_2.field.s4_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S5 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_2.field.s5_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_2.field.s5_s0 & ~m_tmp);
			break;

		case 0x330C:
			// Lsb: 0, Len: 16, [15:0] S6 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_3.field.s6_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_3.field.s6_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S7 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_3.field.s7_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_3.field.s7_s0 & ~m_tmp);
			break;

		case 0x3310:
			// Lsb: 0, Len: 16, [15:0] S8 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_4.field.s8_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_4.field.s8_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S9 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_4.field.s9_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_4.field.s9_s0 & ~m_tmp);
			break;

		case 0x3314:
			// Lsb: 0, Len: 16, [15:0] S10 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_5.field.s10_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_5.field.s10_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S11 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_5.field.s11_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_5.field.s11_s0 & ~m_tmp);
			break;

		case 0x3318:
			// Lsb: 0, Len: 16, [15:0] S12 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_6.field.s12_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_6.field.s12_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S13 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_6.field.s13_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_6.field.s13_s0 & ~m_tmp);
			break;

		case 0x331C:
			// Lsb: 0, Len: 16, [15:0] S14 for symbol 0
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s0_cfg_7.field.s14_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_7.field.s14_s0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S15 for symbol 0
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s0_cfg_7.field.s15_s0 = (d_tmp & m_tmp) | (reg_oecfc_s0_cfg_7.field.s15_s0 & ~m_tmp);
			break;

		case 0x3320:
			// Lsb: 0, Len: 16, [15:0] S0 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_0.field.s0_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_0.field.s0_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S1 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_0.field.s1_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_0.field.s1_s1 & ~m_tmp);
			break;

		case 0x3324:
			// Lsb: 0, Len: 16, [15:0] S2 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_1.field.s2_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_1.field.s2_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S3 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_1.field.s3_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_1.field.s3_s1 & ~m_tmp);
			break;

		case 0x3328:
			// Lsb: 0, Len: 16, [15:0] S4 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_2.field.s4_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_2.field.s4_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S5 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_2.field.s5_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_2.field.s5_s1 & ~m_tmp);
			break;

		case 0x332C:
			// Lsb: 0, Len: 16, [15:0] S6 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_3.field.s6_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_3.field.s6_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S7 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_3.field.s7_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_3.field.s7_s1 & ~m_tmp);
			break;

		case 0x3330:
			// Lsb: 0, Len: 16, [15:0] S8 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_4.field.s8_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_4.field.s8_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S9 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_4.field.s9_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_4.field.s9_s1 & ~m_tmp);
			break;

		case 0x3334:
			// Lsb: 0, Len: 16, [15:0] S10 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_5.field.s10_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_5.field.s10_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S11 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_5.field.s11_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_5.field.s11_s1 & ~m_tmp);
			break;

		case 0x3338:
			// Lsb: 0, Len: 16, [15:0] S12 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_6.field.s12_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_6.field.s12_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S13 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_6.field.s13_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_6.field.s13_s1 & ~m_tmp);
			break;

		case 0x333C:
			// Lsb: 0, Len: 16, [15:0] S14 for symbol 1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s1_cfg_7.field.s14_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_7.field.s14_s1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S15 for symbol 1
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s1_cfg_7.field.s15_s1 = (d_tmp & m_tmp) | (reg_oecfc_s1_cfg_7.field.s15_s1 & ~m_tmp);
			break;

		case 0x3340:
			// Lsb: 0, Len: 16, [15:0] S0 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_0.field.s0_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_0.field.s0_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S1 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_0.field.s1_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_0.field.s1_s2 & ~m_tmp);
			break;

		case 0x3344:
			// Lsb: 0, Len: 16, [15:0] S2 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_1.field.s2_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_1.field.s2_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S3 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_1.field.s3_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_1.field.s3_s2 & ~m_tmp);
			break;

		case 0x3348:
			// Lsb: 0, Len: 16, [15:0] S4 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_2.field.s4_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_2.field.s4_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S5 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_2.field.s5_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_2.field.s5_s2 & ~m_tmp);
			break;

		case 0x334C:
			// Lsb: 0, Len: 16, [15:0] S6 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_3.field.s6_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_3.field.s6_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S7 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_3.field.s7_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_3.field.s7_s2 & ~m_tmp);
			break;

		case 0x3350:
			// Lsb: 0, Len: 16, [15:0] S8 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_4.field.s8_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_4.field.s8_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S9 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_4.field.s9_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_4.field.s9_s2 & ~m_tmp);
			break;

		case 0x3354:
			// Lsb: 0, Len: 16, [15:0] S10 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_5.field.s10_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_5.field.s10_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S11 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_5.field.s11_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_5.field.s11_s2 & ~m_tmp);
			break;

		case 0x3358:
			// Lsb: 0, Len: 16, [15:0] S12 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_6.field.s12_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_6.field.s12_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S13 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_6.field.s13_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_6.field.s13_s2 & ~m_tmp);
			break;

		case 0x335C:
			// Lsb: 0, Len: 16, [15:0] S14 for symbol 2
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s2_cfg_7.field.s14_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_7.field.s14_s2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S15 for symbol 2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s2_cfg_7.field.s15_s2 = (d_tmp & m_tmp) | (reg_oecfc_s2_cfg_7.field.s15_s2 & ~m_tmp);
			break;

		case 0x3360:
			// Lsb: 0, Len: 16, [15:0] S0 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_0.field.s0_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_0.field.s0_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S1 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_0.field.s1_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_0.field.s1_s3 & ~m_tmp);
			break;

		case 0x3364:
			// Lsb: 0, Len: 16, [15:0] S2 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_1.field.s2_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_1.field.s2_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S3 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_1.field.s3_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_1.field.s3_s3 & ~m_tmp);
			break;

		case 0x3368:
			// Lsb: 0, Len: 16, [15:0] S4 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_2.field.s4_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_2.field.s4_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S5 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_2.field.s5_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_2.field.s5_s3 & ~m_tmp);
			break;

		case 0x336C:
			// Lsb: 0, Len: 16, [15:0] S6 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_3.field.s6_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_3.field.s6_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S7 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_3.field.s7_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_3.field.s7_s3 & ~m_tmp);
			break;

		case 0x3370:
			// Lsb: 0, Len: 16, [15:0] S8 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_4.field.s8_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_4.field.s8_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S9 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_4.field.s9_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_4.field.s9_s3 & ~m_tmp);
			break;

		case 0x3374:
			// Lsb: 0, Len: 16, [15:0] S10 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_5.field.s10_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_5.field.s10_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S11 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_5.field.s11_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_5.field.s11_s3 & ~m_tmp);
			break;

		case 0x3378:
			// Lsb: 0, Len: 16, [15:0] S12 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_6.field.s12_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_6.field.s12_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S13 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_6.field.s13_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_6.field.s13_s3 & ~m_tmp);
			break;

		case 0x337C:
			// Lsb: 0, Len: 16, [15:0] S14 for symbol 3
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_oecfc_s3_cfg_7.field.s14_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_7.field.s14_s3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] S15 for symbol 3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_oecfc_s3_cfg_7.field.s15_s3 = (d_tmp & m_tmp) | (reg_oecfc_s3_cfg_7.field.s15_s3 & ~m_tmp);
			break;

		case 0x3810:
			// Lsb: 0, Len: 16, [15:0] Horizontal starting point for frame cropping
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_sc1_cfg_0.field.hstart = (d_tmp & m_tmp) | (reg_sc1_cfg_0.field.hstart & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical starting point for frame cropping
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_sc1_cfg_0.field.vstart = (d_tmp & m_tmp) | (reg_sc1_cfg_0.field.vstart & ~m_tmp);
			break;

		case 0x3814:
			// Lsb: 0, Len: 5, [4:0] Width of SC sub-window(SC_WIDTH+1)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_sc1_cfg_1.field.width = (d_tmp & m_tmp) | (reg_sc1_cfg_1.field.width & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_sc1_cfg_1.field.rsvd5 = (d_tmp & m_tmp) | (reg_sc1_cfg_1.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Height of SC sub-window(SC_HEIGHT+1)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_sc1_cfg_1.field.height = (d_tmp & m_tmp) | (reg_sc1_cfg_1.field.height & ~m_tmp);

			// Lsb: 13, Len: 17, [29:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x0001FFFF;
			reg_sc1_cfg_1.field.rsvd13 = (d_tmp & m_tmp) | (reg_sc1_cfg_1.field.rsvd13 & ~m_tmp);

			// Lsb: 30, Len: 2, [31:30] sc1 input mux for sc ae/af
			d_tmp = (data >> 30); m_tmp = (mask >> 30) & 0x00000003;
			reg_sc1_cfg_1.field.sc1_sel = (d_tmp & m_tmp) | (reg_sc1_cfg_1.field.sc1_sel & ~m_tmp);
			break;

		case 0x3818:
			// Lsb: 0, Len: 5, [4:0] Horizontal period(zero base)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_sc1_dec.field.hperiod = (d_tmp & m_tmp) | (reg_sc1_dec.field.hperiod & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_sc1_dec.field.rsvd5 = (d_tmp & m_tmp) | (reg_sc1_dec.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Horizontal keep(zero base)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_sc1_dec.field.hkeep = (d_tmp & m_tmp) | (reg_sc1_dec.field.hkeep & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_sc1_dec.field.rsvd7 = (d_tmp & m_tmp) | (reg_sc1_dec.field.rsvd7 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] Vertical period(zero base)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_sc1_dec.field.vperiod = (d_tmp & m_tmp) | (reg_sc1_dec.field.vperiod & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_sc1_dec.field.rsvd21 = (d_tmp & m_tmp) | (reg_sc1_dec.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] Vertical keep(zero base)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_sc1_dec.field.vkeep = (d_tmp & m_tmp) | (reg_sc1_dec.field.vkeep & ~m_tmp);
			break;

		case 0x3820:
			// Lsb: 0, Len: 16, [15:0] Horizontal starting point for frame cropping
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_sc0_cfg_0.field.hstart = (d_tmp & m_tmp) | (reg_sc0_cfg_0.field.hstart & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical starting point for frame cropping
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_sc0_cfg_0.field.vstart = (d_tmp & m_tmp) | (reg_sc0_cfg_0.field.vstart & ~m_tmp);
			break;

		case 0x3824:
			// Lsb: 0, Len: 5, [4:0] Width of SC sub-window(SC_WIDTH+1)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_sc0_cfg_1.field.width = (d_tmp & m_tmp) | (reg_sc0_cfg_1.field.width & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_sc0_cfg_1.field.rsvd5 = (d_tmp & m_tmp) | (reg_sc0_cfg_1.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Height of SC sub-window(SC_HEIGHT+1)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_sc0_cfg_1.field.height = (d_tmp & m_tmp) | (reg_sc0_cfg_1.field.height & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_sc0_cfg_1.field.rsvd13 = (d_tmp & m_tmp) | (reg_sc0_cfg_1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 8, [23:16] [0.4.4] awb b/a value
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000000FF;
			reg_sc0_cfg_1.field.awb_ps_grb_ba = (d_tmp & m_tmp) | (reg_sc0_cfg_1.field.awb_ps_grb_ba & ~m_tmp);

			// Lsb: 24, Len: 6, [29:24] 
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000003F;
			reg_sc0_cfg_1.field.rsvd24 = (d_tmp & m_tmp) | (reg_sc0_cfg_1.field.rsvd24 & ~m_tmp);

			// Lsb: 30, Len: 2, [31:30] sc0 input mux for sc awb
			d_tmp = (data >> 30); m_tmp = (mask >> 30) & 0x00000003;
			reg_sc0_cfg_1.field.sc0_sel = (d_tmp & m_tmp) | (reg_sc0_cfg_1.field.sc0_sel & ~m_tmp);
			break;

		case 0x3828:
			// Lsb: 0, Len: 5, [4:0] Horizontal period(zero base)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_sc0_dec.field.hperiod = (d_tmp & m_tmp) | (reg_sc0_dec.field.hperiod & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_sc0_dec.field.rsvd5 = (d_tmp & m_tmp) | (reg_sc0_dec.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Horizontal keep(zero base)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_sc0_dec.field.hkeep = (d_tmp & m_tmp) | (reg_sc0_dec.field.hkeep & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_sc0_dec.field.rsvd7 = (d_tmp & m_tmp) | (reg_sc0_dec.field.rsvd7 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] Vertical period(zero base)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_sc0_dec.field.vperiod = (d_tmp & m_tmp) | (reg_sc0_dec.field.vperiod & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_sc0_dec.field.rsvd21 = (d_tmp & m_tmp) | (reg_sc0_dec.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] Vertical keep(zero base)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_sc0_dec.field.vkeep = (d_tmp & m_tmp) | (reg_sc0_dec.field.vkeep & ~m_tmp);
			break;

		case 0x400C:
			// Lsb: 0, Len: 1, [0] active high
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_clkgcfg.field.dc_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.dc_clkg & ~m_tmp);

			// Lsb: 1, Len: 1, [1] active high
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_clkgcfg.field.dec_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.dec_clkg & ~m_tmp);

			// Lsb: 2, Len: 1, [2] active high
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_clkgcfg.field.obc_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.obc_clkg & ~m_tmp);

			// Lsb: 3, Len: 1, [3] active high
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_clkgcfg.field.oecfc_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.oecfc_clkg & ~m_tmp);

			// Lsb: 4, Len: 1, [4] active high
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_clkgcfg.field.oecf_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.oecf_clkg & ~m_tmp);

			// Lsb: 5, Len: 1, [5] active high
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_clkgcfg.field.lcbq_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.lcbq_clkg & ~m_tmp);

			// Lsb: 6, Len: 1, [6] active high
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000001;
			reg_clkgcfg.field.lccf_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.lccf_clkg & ~m_tmp);

			// Lsb: 7, Len: 1, [7] active high
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_clkgcfg.field.oba_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.oba_clkg & ~m_tmp);

			// Lsb: 8, Len: 1, [8] active high
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000001;
			reg_clkgcfg.field.dbc_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.dbc_clkg & ~m_tmp);

			// Lsb: 9, Len: 1, [9] active high
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_clkgcfg.field.nl3d_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.nl3d_clkg & ~m_tmp);

			// Lsb: 10, Len: 1, [10] active high
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000001;
			reg_clkgcfg.field.ctc_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.ctc_clkg & ~m_tmp);

			// Lsb: 11, Len: 1, [11] active high
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_clkgcfg.field.nl2d_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.nl2d_clkg & ~m_tmp);

			// Lsb: 12, Len: 1, [12] active high
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000001;
			reg_clkgcfg.field.ls_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.ls_clkg & ~m_tmp);

			// Lsb: 13, Len: 1, [13] active high
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000001;
			reg_clkgcfg.field.gamr_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.gamr_clkg & ~m_tmp);

			// Lsb: 14, Len: 1, [14] active high
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000001;
			reg_clkgcfg.field.pf_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.pf_clkg & ~m_tmp);

			// Lsb: 15, Len: 1, [15] active high
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_clkgcfg.field.ca_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.ca_clkg & ~m_tmp);

			// Lsb: 16, Len: 1, [16] active high
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000001;
			reg_clkgcfg.field.wdr_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.wdr_clkg & ~m_tmp);

			// Lsb: 17, Len: 1, [17] active high
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000001;
			reg_clkgcfg.field.lut_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.lut_clkg & ~m_tmp);

			// Lsb: 18, Len: 1, [18] active high
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_clkgcfg.field.ctm_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.ctm_clkg & ~m_tmp);

			// Lsb: 19, Len: 1, [19] active high
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_clkgcfg.field.ycurve_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.ycurve_clkg & ~m_tmp);

			// Lsb: 20, Len: 1, [20] active high
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000001;
			reg_clkgcfg.field.shrp_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.shrp_clkg & ~m_tmp);

			// Lsb: 21, Len: 1, [21] active high
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000001;
			reg_clkgcfg.field.bil_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.bil_clkg & ~m_tmp);

			// Lsb: 22, Len: 1, [22] active high
			d_tmp = (data >> 22); m_tmp = (mask >> 22) & 0x00000001;
			reg_clkgcfg.field.sat_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.sat_clkg & ~m_tmp);

			// Lsb: 23, Len: 1, [23] active high
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x00000001;
			reg_clkgcfg.field.yhist_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.yhist_clkg & ~m_tmp);

			// Lsb: 24, Len: 1, [24] tiling 0 read module clk gate, active high
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x00000001;
			reg_clkgcfg.field.iti0_rd_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.iti0_rd_clkg & ~m_tmp);

			// Lsb: 25, Len: 1, [25] tiling 0 write module clk gate, active high
			d_tmp = (data >> 25); m_tmp = (mask >> 25) & 0x00000001;
			reg_clkgcfg.field.iti0_wr_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.iti0_wr_clkg & ~m_tmp);

			// Lsb: 26, Len: 1, [26] tiling 1 write module clk gate, active high
			d_tmp = (data >> 26); m_tmp = (mask >> 26) & 0x00000001;
			reg_clkgcfg.field.iti1_wr_clkg = (d_tmp & m_tmp) | (reg_clkgcfg.field.iti1_wr_clkg & ~m_tmp);
			break;

		case 0x4028:
			// Lsb: 0, Len: 16, [15:0] Active capture area width (xsize)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_sensorsz.field.w = (d_tmp & m_tmp) | (reg_sensorsz.field.w & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Active capture area height(ysize)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_sensorsz.field.h = (d_tmp & m_tmp) | (reg_sensorsz.field.h & ~m_tmp);
			break;

		case 0x403C:
			// Lsb: 0, Len: 4, [3:0] pipeline module frame end interrupt mux, the same as tiling index define
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_pmimr.field.intmux = (d_tmp & m_tmp) | (reg_pmimr.field.intmux & ~m_tmp);
			break;

		case 0x404C:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ispinten.field.rsvd = (d_tmp & m_tmp) | (reg_ispinten.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] interrupt enable
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ispinten.field.inte = (d_tmp & m_tmp) | (reg_ispinten.field.inte & ~m_tmp);
			break;

		case 0x4060:
			// Lsb: 0, Len: 14, [13:0] Threshold value T1
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_itifbc0.field.t1 = (d_tmp & m_tmp) | (reg_itifbc0.field.t1 & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_itifbc0.field.rsvd14 = (d_tmp & m_tmp) | (reg_itifbc0.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Threshold value T2
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_itifbc0.field.t2 = (d_tmp & m_tmp) | (reg_itifbc0.field.t2 & ~m_tmp);
			break;

		case 0x4064:
			// Lsb: 0, Len: 1, [0] Tiling frame buffer compressed moudle enable
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_itifbc1.field.ifbce = (d_tmp & m_tmp) | (reg_itifbc1.field.ifbce & ~m_tmp);

			// Lsb: 1, Len: 3, [3:1] 
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000007;
			reg_itifbc1.field.rsvd1 = (d_tmp & m_tmp) | (reg_itifbc1.field.rsvd1 & ~m_tmp);

			// Lsb: 4, Len: 2, [5:4] Color transform
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000003;
			reg_itifbc1.field.ct = (d_tmp & m_tmp) | (reg_itifbc1.field.ct & ~m_tmp);

			// Lsb: 6, Len: 2, [7:6] RAW start color, read only
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x00000003;
			reg_itifbc1.field.rsc = (d_tmp & m_tmp) | (reg_itifbc1.field.rsc & ~m_tmp);

			// Lsb: 8, Len: 2, [9:8] Sample mode register, 2'b00 for 8bit, 2'b01 for 10bit, 2'b10 for 12bit, 2'b11 for 14bit;
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000003;
			reg_itifbc1.field.spm = (d_tmp & m_tmp) | (reg_itifbc1.field.spm & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_itifbc1.field.rsvd10 = (d_tmp & m_tmp) | (reg_itifbc1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 14, [29:16] Threshold value T3
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00003FFF;
			reg_itifbc1.field.t3 = (d_tmp & m_tmp) | (reg_itifbc1.field.t3 & ~m_tmp);
			break;

		case 0x4068:
			// Lsb: 0, Len: 5, [4:0] Horizontal period(zero base)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_itidec0.field.hperiod = (d_tmp & m_tmp) | (reg_itidec0.field.hperiod & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_itidec0.field.rsvd5 = (d_tmp & m_tmp) | (reg_itidec0.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Horizontal keep(zero base)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_itidec0.field.hkeep = (d_tmp & m_tmp) | (reg_itidec0.field.hkeep & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_itidec0.field.rsvd13 = (d_tmp & m_tmp) | (reg_itidec0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] Vertical period(zero base)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_itidec0.field.vperiod = (d_tmp & m_tmp) | (reg_itidec0.field.vperiod & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_itidec0.field.rsvd21 = (d_tmp & m_tmp) | (reg_itidec0.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] Vertical keep(zero base)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_itidec0.field.vkeep = (d_tmp & m_tmp) | (reg_itidec0.field.vkeep & ~m_tmp);

			// Lsb: 29, Len: 2, [30:29] 
			d_tmp = (data >> 29); m_tmp = (mask >> 29) & 0x00000003;
			reg_itidec0.field.rsvd29 = (d_tmp & m_tmp) | (reg_itidec0.field.rsvd29 & ~m_tmp);

			// Lsb: 31, Len: 1, [31] tiling write enable
			d_tmp = (data >> 31); m_tmp = (mask >> 31) & 0x00000001;
			reg_itidec0.field.dec_en = (d_tmp & m_tmp) | (reg_itidec0.field.dec_en & ~m_tmp);
			break;

		case 0x406C:
			// Lsb: 0, Len: 5, [4:0] Horizontal period(zero base)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_itidec1.field.hperiod = (d_tmp & m_tmp) | (reg_itidec1.field.hperiod & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_itidec1.field.rsvd5 = (d_tmp & m_tmp) | (reg_itidec1.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] Horizontal keep(zero base)
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_itidec1.field.hkeep = (d_tmp & m_tmp) | (reg_itidec1.field.hkeep & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_itidec1.field.rsvd13 = (d_tmp & m_tmp) | (reg_itidec1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] Vertical period(zero base)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_itidec1.field.vperiod = (d_tmp & m_tmp) | (reg_itidec1.field.vperiod & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_itidec1.field.rsvd21 = (d_tmp & m_tmp) | (reg_itidec1.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] Vertical keep(zero base)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_itidec1.field.vkeep = (d_tmp & m_tmp) | (reg_itidec1.field.vkeep & ~m_tmp);

			// Lsb: 29, Len: 2, [30:29] 
			d_tmp = (data >> 29); m_tmp = (mask >> 29) & 0x00000003;
			reg_itidec1.field.rsvd29 = (d_tmp & m_tmp) | (reg_itidec1.field.rsvd29 & ~m_tmp);

			// Lsb: 31, Len: 1, [31] tiling write enable
			d_tmp = (data >> 31); m_tmp = (mask >> 31) & 0x00000001;
			reg_itidec1.field.dec_en = (d_tmp & m_tmp) | (reg_itidec1.field.dec_en & ~m_tmp);
			break;

		case 0x4070:
			// Lsb: 0, Len: 16, [15:0] Horizontal starting point of capture window
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_iticrop0.field.hstart = (d_tmp & m_tmp) | (reg_iticrop0.field.hstart & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical starting point of capture window
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_iticrop0.field.vstart = (d_tmp & m_tmp) | (reg_iticrop0.field.vstart & ~m_tmp);
			break;

		case 0x4074:
			// Lsb: 0, Len: 16, [15:0] Horizontal ending point of capture window, when hend = 0 will disable cropping (default)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_iticrop1.field.hend = (d_tmp & m_tmp) | (reg_iticrop1.field.hend & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical ending point of capture window
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_iticrop1.field.vend = (d_tmp & m_tmp) | (reg_iticrop1.field.vend & ~m_tmp);
			break;

		case 0x4078:
			// Lsb: 0, Len: 16, [15:0] Horizontal starting point of capture window
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_iticrop2.field.hstart = (d_tmp & m_tmp) | (reg_iticrop2.field.hstart & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical starting point of capture window
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_iticrop2.field.vstart = (d_tmp & m_tmp) | (reg_iticrop2.field.vstart & ~m_tmp);
			break;

		case 0x407C:
			// Lsb: 0, Len: 16, [15:0] Horizontal ending point of capture window, when hend = 0 will disable cropping (default)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_iticrop3.field.hend = (d_tmp & m_tmp) | (reg_iticrop3.field.hend & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Vertical ending point of capture window
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_iticrop3.field.vend = (d_tmp & m_tmp) | (reg_iticrop3.field.vend & ~m_tmp);
			break;

		case 0x4080:
			// Lsb: 0, Len: 16, [15:0] xsize for normal tiling 0 write
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_itiiwsr__.field.wsize = (d_tmp & m_tmp) | (reg_itiiwsr__.field.wsize & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] ysize for normal tiling 0 write
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_itiiwsr__.field.hsize = (d_tmp & m_tmp) | (reg_itiiwsr__.field.hsize & ~m_tmp);
			break;

		case 0x4084:
			// Lsb: 0, Len: 16, [15:0] xsize for  tiling read
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_itirwsr__.field.wsize = (d_tmp & m_tmp) | (reg_itirwsr__.field.wsize & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] ysize for  tiling read
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_itirwsr__.field.hsize = (d_tmp & m_tmp) | (reg_itirwsr__.field.hsize & ~m_tmp);
			break;

		case 0x4088:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwlsr__.field.reserved = (d_tmp & m_tmp) | (reg_itidwlsr__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 13, [15:3] The line stride of  the next  line address  in DRAM Y buffer (8-byte Alignment) for the write path. when set to 1, indicate frame mode(no line stride)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00001FFF;
			reg_itidwlsr__.field.wstride = (d_tmp & m_tmp) | (reg_itidwlsr__.field.wstride & ~m_tmp);

			// Lsb: 16, Len: 3, [18:16] 
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000007;
			reg_itidwlsr__.field.reserved16 = (d_tmp & m_tmp) | (reg_itidwlsr__.field.reserved16 & ~m_tmp);

			// Lsb: 19, Len: 13, [31:19] The line stride of  the next  line address  in DRAM UV buffer (8-byte Alignment) for the write path. when set to 1, indicate frame mode(no line stride)
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00001FFF;
			reg_itidwlsr__.field.uvwstride = (d_tmp & m_tmp) | (reg_itidwlsr__.field.uvwstride & ~m_tmp);
			break;

		case 0x408C:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrlsr__.field.reserved0 = (d_tmp & m_tmp) | (reg_itidrlsr__.field.reserved0 & ~m_tmp);

			// Lsb: 3, Len: 13, [15:3] The line stride of  the next  line address  in DRAM Y buffer (8-byte Alignment) for the READ  path. when set to 1, indicate frame mode(no line stride)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00001FFF;
			reg_itidrlsr__.field.rstride = (d_tmp & m_tmp) | (reg_itidrlsr__.field.rstride & ~m_tmp);

			// Lsb: 16, Len: 3, [18:16] 
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000007;
			reg_itidrlsr__.field.reserved16 = (d_tmp & m_tmp) | (reg_itidrlsr__.field.reserved16 & ~m_tmp);

			// Lsb: 19, Len: 13, [31:19] The line stride of  the next  line address  in DRAM UV buffer (8-byte Alignment) for the READ  path. when set to 1, indicate frame mode(no line stride)
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00001FFF;
			reg_itidrlsr__.field.uvrstride = (d_tmp & m_tmp) | (reg_itidrlsr__.field.uvrstride & ~m_tmp);
			break;

		case 0x4090:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwysar0__.field.reserved = (d_tmp & m_tmp) | (reg_itidwysar0__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Data buffer start address 0 for writing RAW/Y plane in DRAM buffer(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwysar0__.field.wyaddr = (d_tmp & m_tmp) | (reg_itidwysar0__.field.wyaddr & ~m_tmp);
			break;

		case 0x4094:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwusar0__.field.reserved = (d_tmp & m_tmp) | (reg_itidwusar0__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] UV start address 0 (8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwusar0__.field.wuvaddr = (d_tmp & m_tmp) | (reg_itidwusar0__.field.wuvaddr & ~m_tmp);
			break;

		case 0x4098:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrysar0__.field.reserved = (d_tmp & m_tmp) | (reg_itidrysar0__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read RAW/Y plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrysar0__.field.ryaddr = (d_tmp & m_tmp) | (reg_itidrysar0__.field.ryaddr & ~m_tmp);
			break;

		case 0x409C:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrusar0__.field.reserved = (d_tmp & m_tmp) | (reg_itidrusar0__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read UV plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrusar0__.field.ruvaddr = (d_tmp & m_tmp) | (reg_itidrusar0__.field.ruvaddr & ~m_tmp);
			break;

		case 0x40A0:
			// Lsb: 0, Len: 1, [0] write0 busy, active high(read-only)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_itibsr__.field.wbusy0 = (d_tmp & m_tmp) | (reg_itibsr__.field.wbusy0 & ~m_tmp);

			// Lsb: 1, Len: 1, [1] read busy, active high(read-only)
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_itibsr__.field.rbusy = (d_tmp & m_tmp) | (reg_itibsr__.field.rbusy & ~m_tmp);

			// Lsb: 2, Len: 1, [2] write1 busy, active high(read-only)
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_itibsr__.field.wbusy1 = (d_tmp & m_tmp) | (reg_itibsr__.field.wbusy1 & ~m_tmp);
			break;

		case 0x40A4:
			// Lsb: 0, Len: 4, [3:0] Data Package Format type for the write path.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_itiwrdfr__.field.wrformat = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.wrformat & ~m_tmp);

			// Lsb: 4, Len: 5, [8:4] RAW flexible bit number for write
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000001F;
			reg_itiwrdfr__.field.wrflexiblebit = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.wrflexiblebit & ~m_tmp);

			// Lsb: 9, Len: 1, [9] 0 : frame soft-reset enable, 1 : disable
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_itiwrdfr__.field.frameswreset_dsb = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.frameswreset_dsb & ~m_tmp);

			// Lsb: 10, Len: 1, [10] tiling write 0, 0:8bit, 1:10bit
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000001;
			reg_itiwrdfr__.field.yuvbitmode = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.yuvbitmode & ~m_tmp);

			// Lsb: 11, Len: 1, [11] tiling write 0, 1:msb padding, 0:lsb padding
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_itiwrdfr__.field.yuvpaddingmode = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.yuvpaddingmode & ~m_tmp);

			// Lsb: 12, Len: 2, [13:12] tiling write 0 YUV420/422 sub-sample mode,
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000003;
			reg_itiwrdfr__.field.yuvsubsamplemode = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.yuvsubsamplemode & ~m_tmp);

			// Lsb: 14, Len: 1, [14] UV offset disable, 1:  disable add 512 in write path , 0: add 512 in write path
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000001;
			reg_itiwrdfr__.field.uvoffset_dsb = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.uvoffset_dsb & ~m_tmp);

			// Lsb: 15, Len: 1, [15] 
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_itiwrdfr__.field.rsvd15 = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.rsvd15 & ~m_tmp);

			// Lsb: 16, Len: 2, [17:16] frame image write mode
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000003;
			reg_itiwrdfr__.field.writeframemode = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.writeframemode & ~m_tmp);

			// Lsb: 18, Len: 1, [18] one valid when WriteFrameMode set to non zero
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_itiwrdfr__.field.writedumpen = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.writedumpen & ~m_tmp);

			// Lsb: 19, Len: 1, [19] frame write done flag(read-only)
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_itiwrdfr__.field.writedumpdone = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.writedumpdone & ~m_tmp);

			// Lsb: 20, Len: 2, [21:20] current write frame counter(read only)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000003;
			reg_itiwrdfr__.field.frame_cnt = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.frame_cnt & ~m_tmp);

			// Lsb: 22, Len: 2, [23:22] write rvi interface frame cnt(read only)
			d_tmp = (data >> 22); m_tmp = (mask >> 22) & 0x00000003;
			reg_itiwrdfr__.field.rvi_frame_cnt = (d_tmp & m_tmp) | (reg_itiwrdfr__.field.rvi_frame_cnt & ~m_tmp);
			break;

		case 0x40A8:
			// Lsb: 0, Len: 4, [3:0] Data Package Format type for the read path
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_itirddfr__.field.rdformat = (d_tmp & m_tmp) | (reg_itirddfr__.field.rdformat & ~m_tmp);

			// Lsb: 4, Len: 5, [8:4] RAW flexible bit number for read
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000001F;
			reg_itirddfr__.field.rdflexiblebit = (d_tmp & m_tmp) | (reg_itirddfr__.field.rdflexiblebit & ~m_tmp);

			// Lsb: 9, Len: 1, [9] 
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_itirddfr__.field.rsvd9 = (d_tmp & m_tmp) | (reg_itirddfr__.field.rsvd9 & ~m_tmp);

			// Lsb: 10, Len: 1, [10] tiling write 0, 0:8bit, 1:10bit
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000001;
			reg_itirddfr__.field.yuvbitmode = (d_tmp & m_tmp) | (reg_itirddfr__.field.yuvbitmode & ~m_tmp);

			// Lsb: 11, Len: 1, [11] tiling write 0, 1:msb padding, 0:lsb padding
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000001;
			reg_itirddfr__.field.yuvpaddingmode = (d_tmp & m_tmp) | (reg_itirddfr__.field.yuvpaddingmode & ~m_tmp);

			// Lsb: 12, Len: 2, [13:12] tiling write 0 YUV420/422 sub-sample mode,
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000003;
			reg_itirddfr__.field.yuvsubsamplemode = (d_tmp & m_tmp) | (reg_itirddfr__.field.yuvsubsamplemode & ~m_tmp);

			// Lsb: 14, Len: 1, [14] UV offset disable, 1:  disable sub 512 in read path , 0: sub 512 in read path
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000001;
			reg_itirddfr__.field.uvoffset_dsb = (d_tmp & m_tmp) | (reg_itirddfr__.field.uvoffset_dsb & ~m_tmp);

			// Lsb: 15, Len: 1, [15] Disable  UV line buffer function for  YUV de-package flow
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_itirddfr__.field.rdlinebufoff = (d_tmp & m_tmp) | (reg_itirddfr__.field.rdlinebufoff & ~m_tmp);

			// Lsb: 16, Len: 2, [17:16] read frame mode 0:continuous frame, 1 : only read one frame image , 2 : read two frame image, 3 : read four frame image
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000003;
			reg_itirddfr__.field.readframemode = (d_tmp & m_tmp) | (reg_itirddfr__.field.readframemode & ~m_tmp);

			// Lsb: 18, Len: 1, [18] 
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_itirddfr__.field.rsvd18 = (d_tmp & m_tmp) | (reg_itirddfr__.field.rsvd18 & ~m_tmp);

			// Lsb: 19, Len: 1, [19] frame read done flag(read-only)
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_itirddfr__.field.readframedone = (d_tmp & m_tmp) | (reg_itirddfr__.field.readframedone & ~m_tmp);

			// Lsb: 20, Len: 2, [21:20] current read frame counter(read only)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000003;
			reg_itirddfr__.field.frame_cnt = (d_tmp & m_tmp) | (reg_itirddfr__.field.frame_cnt & ~m_tmp);

			// Lsb: 22, Len: 1, [22] 
			d_tmp = (data >> 22); m_tmp = (mask >> 22) & 0x00000001;
			reg_itirddfr__.field.rsvd22 = (d_tmp & m_tmp) | (reg_itirddfr__.field.rsvd22 & ~m_tmp);

			// Lsb: 23, Len: 1, [23] frame blanking enable, when set to high will generate blanking by BlankSize
			d_tmp = (data >> 23); m_tmp = (mask >> 23) & 0x00000001;
			reg_itirddfr__.field.blanken = (d_tmp & m_tmp) | (reg_itirddfr__.field.blanken & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] frame blanking size, vsync generate in the center of blanking(minimum=2)
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_itirddfr__.field.blanksize = (d_tmp & m_tmp) | (reg_itirddfr__.field.blanksize & ~m_tmp);
			break;

		case 0x40AC:
			// Lsb: 0, Len: 4, [3:0] The index of the selected module whose input will be selected from DRAM buffer.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_itidpsr__.field.readindex = (d_tmp & m_tmp) | (reg_itidpsr__.field.readindex & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] The index of the selected module whose output will be written into DRAM buffer.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_itidpsr__.field.writeindex = (d_tmp & m_tmp) | (reg_itidpsr__.field.writeindex & ~m_tmp);

			// Lsb: 8, Len: 2, [9:8] (read only) tiling read raw data first pixel symbol, 0-> R 1-> Gr 2-> Gb 3-> B
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000003;
			reg_itidpsr__.field.rd_sym = (d_tmp & m_tmp) | (reg_itidpsr__.field.rd_sym & ~m_tmp);

			// Lsb: 10, Len: 2, [11:10] tiling read axi outstanding mode, 0 : 4*1*8*64, 1: 2*2*8*64, 2: 1*4*8*64
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000003;
			reg_itidpsr__.field.rbstm = (d_tmp & m_tmp) | (reg_itidpsr__.field.rbstm & ~m_tmp);

			// Lsb: 12, Len: 2, [13:12] tiling write axi burst length mode, 0: burst 16, 1: burst 8, 2: burst 4
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000003;
			reg_itidpsr__.field.wbstm = (d_tmp & m_tmp) | (reg_itidpsr__.field.wbstm & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_itidpsr__.field.rsvd14 = (d_tmp & m_tmp) | (reg_itidpsr__.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 1, [16] Enable the read function of the ITI interface from DRAM buffer.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000001;
			reg_itidpsr__.field.readdram = (d_tmp & m_tmp) | (reg_itidpsr__.field.readdram & ~m_tmp);

			// Lsb: 17, Len: 1, [17] Enable the write function of the ITI interface into DRAM buffer.
			d_tmp = (data >> 17); m_tmp = (mask >> 17) & 0x00000001;
			reg_itidpsr__.field.writedram = (d_tmp & m_tmp) | (reg_itidpsr__.field.writedram & ~m_tmp);

			// Lsb: 18, Len: 1, [18] test pipeline control, but data from read tiling to write tiling
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_itidpsr__.field.loopback = (d_tmp & m_tmp) | (reg_itidpsr__.field.loopback & ~m_tmp);

			// Lsb: 19, Len: 1, [19] from read tiling to capture tiling when INDEPENDENTRDRVI not valid
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_itidpsr__.field.movedramdata = (d_tmp & m_tmp) | (reg_itidpsr__.field.movedramdata & ~m_tmp);

			// Lsb: 20, Len: 1, [20] Enable the independent  READ RVI signal function under  the normal  DRAM read mode. when set, readindex can't set to 1
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000001;
			reg_itidpsr__.field.independentrdrvi = (d_tmp & m_tmp) | (reg_itidpsr__.field.independentrdrvi & ~m_tmp);

			// Lsb: 21, Len: 1, [21] Enable the independent  write to DRAM, ignore next pipeline RVI
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000001;
			reg_itidpsr__.field.independentwr = (d_tmp & m_tmp) | (reg_itidpsr__.field.independentwr & ~m_tmp);

			// Lsb: 22, Len: 2, [23:22] 
			d_tmp = (data >> 22); m_tmp = (mask >> 22) & 0x00000003;
			reg_itidpsr__.field.reserved22 = (d_tmp & m_tmp) | (reg_itidpsr__.field.reserved22 & ~m_tmp);

			// Lsb: 24, Len: 1, [24] read UV swap, 1 : NV21, 0 : NV12
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x00000001;
			reg_itidpsr__.field.rdnv21format = (d_tmp & m_tmp) | (reg_itidpsr__.field.rdnv21format & ~m_tmp);

			// Lsb: 25, Len: 1, [25] write UV swap, 1 : NV21, 0 : NV12
			d_tmp = (data >> 25); m_tmp = (mask >> 25) & 0x00000001;
			reg_itidpsr__.field.wrnv21format = (d_tmp & m_tmp) | (reg_itidpsr__.field.wrnv21format & ~m_tmp);

			// Lsb: 26, Len: 5, [30:26] Horizontal blanking size
			d_tmp = (data >> 26); m_tmp = (mask >> 26) & 0x0000001F;
			reg_itidpsr__.field.hblank = (d_tmp & m_tmp) | (reg_itidpsr__.field.hblank & ~m_tmp);

			// Lsb: 31, Len: 1, [31] Horizontal blanking disable,  for dram read mode, must disable.
			d_tmp = (data >> 31); m_tmp = (mask >> 31) & 0x00000001;
			reg_itidpsr__.field.hblank_dsb = (d_tmp & m_tmp) | (reg_itidpsr__.field.hblank_dsb & ~m_tmp);
			break;

		case 0x40B0:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwysar1__.field.reserved = (d_tmp & m_tmp) | (reg_itidwysar1__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] RAW/Y plane buffer address 1(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwysar1__.field.wyaddr = (d_tmp & m_tmp) | (reg_itidwysar1__.field.wyaddr & ~m_tmp);
			break;

		case 0x40B4:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwusar1__.field.reserved = (d_tmp & m_tmp) | (reg_itidwusar1__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] UV plane buffer address 1(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwusar1__.field.wuvaddr = (d_tmp & m_tmp) | (reg_itidwusar1__.field.wuvaddr & ~m_tmp);
			break;

		case 0x40B8:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwysar2__.field.reserved = (d_tmp & m_tmp) | (reg_itidwysar2__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] RAW/Y plane buffer address 2(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwysar2__.field.wyaddr = (d_tmp & m_tmp) | (reg_itidwysar2__.field.wyaddr & ~m_tmp);
			break;

		case 0x40BC:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwusar2__.field.reserved = (d_tmp & m_tmp) | (reg_itidwusar2__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] UV plane buffer address 2(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwusar2__.field.wuvaddr = (d_tmp & m_tmp) | (reg_itidwusar2__.field.wuvaddr & ~m_tmp);
			break;

		case 0x40C0:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwysar3__.field.reserved = (d_tmp & m_tmp) | (reg_itidwysar3__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] RAW/Y plane buffer address 3(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwysar3__.field.wyaddr = (d_tmp & m_tmp) | (reg_itidwysar3__.field.wyaddr & ~m_tmp);
			break;

		case 0x40C4:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidwusar3__.field.reserved = (d_tmp & m_tmp) | (reg_itidwusar3__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] UV plane buffer address 3(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidwusar3__.field.wuvaddr = (d_tmp & m_tmp) | (reg_itidwusar3__.field.wuvaddr & ~m_tmp);
			break;

		case 0x40C8:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrysar1__.field.reserved = (d_tmp & m_tmp) | (reg_itidrysar1__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read RAW/Y plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrysar1__.field.ryaddr = (d_tmp & m_tmp) | (reg_itidrysar1__.field.ryaddr & ~m_tmp);
			break;

		case 0x40CC:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrusar1__.field.reserved = (d_tmp & m_tmp) | (reg_itidrusar1__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read UV plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrusar1__.field.ruvaddr = (d_tmp & m_tmp) | (reg_itidrusar1__.field.ruvaddr & ~m_tmp);
			break;

		case 0x40D0:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrysar2__.field.reserved = (d_tmp & m_tmp) | (reg_itidrysar2__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read RAW/Y plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrysar2__.field.ryaddr = (d_tmp & m_tmp) | (reg_itidrysar2__.field.ryaddr & ~m_tmp);
			break;

		case 0x40D4:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrusar2__.field.reserved = (d_tmp & m_tmp) | (reg_itidrusar2__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read UV plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrusar2__.field.ruvaddr = (d_tmp & m_tmp) | (reg_itidrusar2__.field.ruvaddr & ~m_tmp);
			break;

		case 0x40D8:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrysar3__.field.reserved = (d_tmp & m_tmp) | (reg_itidrysar3__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read RAW/Y plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrysar3__.field.ryaddr = (d_tmp & m_tmp) | (reg_itidrysar3__.field.ryaddr & ~m_tmp);
			break;

		case 0x40DC:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_itidrusar3__.field.reserved = (d_tmp & m_tmp) | (reg_itidrusar3__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] read UV plane start addres(8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_itidrusar3__.field.ruvaddr = (d_tmp & m_tmp) | (reg_itidrusar3__.field.ruvaddr & ~m_tmp);
			break;

		case 0x40E0:
			// Lsb: 0, Len: 16, [15:0] xsize
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_iticiwsr__.field.wsize = (d_tmp & m_tmp) | (reg_iticiwsr__.field.wsize & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] ysize
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_iticiwsr__.field.hsize = (d_tmp & m_tmp) | (reg_iticiwsr__.field.hsize & ~m_tmp);
			break;

		case 0x40E4:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_iticwlsr__.field.reserved = (d_tmp & m_tmp) | (reg_iticwlsr__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 13, [15:3] line stride for capture tiling
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00001FFF;
			reg_iticwlsr__.field.wstride = (d_tmp & m_tmp) | (reg_iticwlsr__.field.wstride & ~m_tmp);
			break;

		case 0x40E8:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_iticwysar0__.field.reserved = (d_tmp & m_tmp) | (reg_iticwysar0__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Tiling Capture buffer address (8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_iticwysar0__.field.wyaddr = (d_tmp & m_tmp) | (reg_iticwysar0__.field.wyaddr & ~m_tmp);
			break;

		case 0x40EC:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_iticwysar1__.field.reserved = (d_tmp & m_tmp) | (reg_iticwysar1__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Tiling Capture buffer address (8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_iticwysar1__.field.wyaddr = (d_tmp & m_tmp) | (reg_iticwysar1__.field.wyaddr & ~m_tmp);
			break;

		case 0x40F0:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_iticwysar2__.field.reserved = (d_tmp & m_tmp) | (reg_iticwysar2__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Tiling Capture buffer address (8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_iticwysar2__.field.wyaddr = (d_tmp & m_tmp) | (reg_iticwysar2__.field.wyaddr & ~m_tmp);
			break;

		case 0x40F4:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_iticwysar3__.field.reserved = (d_tmp & m_tmp) | (reg_iticwysar3__.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Tiling Capture buffer address (8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_iticwysar3__.field.wyaddr = (d_tmp & m_tmp) | (reg_iticwysar3__.field.wyaddr & ~m_tmp);
			break;

		case 0x40F8:
			// Lsb: 0, Len: 4, [3:0] Data Package Format type for the write path.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_iticpdfr__.field.wrformat = (d_tmp & m_tmp) | (reg_iticpdfr__.field.wrformat & ~m_tmp);

			// Lsb: 4, Len: 5, [8:4] RAW flexible bit number for write
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000001F;
			reg_iticpdfr__.field.wrflexiblebit = (d_tmp & m_tmp) | (reg_iticpdfr__.field.wrflexiblebit & ~m_tmp);

			// Lsb: 9, Len: 1, [9] 0 : frame soft-reset enable, 1 : disable
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_iticpdfr__.field.frameswreset_dsb = (d_tmp & m_tmp) | (reg_iticpdfr__.field.frameswreset_dsb & ~m_tmp);

			// Lsb: 10, Len: 1, [10] tiling write 1, 0:8bit, 1:10bit
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x00000001;
			reg_iticpdfr__.field.yuvbitmode = (d_tmp & m_tmp) | (reg_iticpdfr__.field.yuvbitmode & ~m_tmp);

			// Lsb: 11, Len: 3, [13:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x00000007;
			reg_iticpdfr__.field.rsvd11 = (d_tmp & m_tmp) | (reg_iticpdfr__.field.rsvd11 & ~m_tmp);

			// Lsb: 14, Len: 1, [14] UV offset disable, 1:  disable add 512 in write path , 0: add 512 in write path
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000001;
			reg_iticpdfr__.field.uvoffset_dsb = (d_tmp & m_tmp) | (reg_iticpdfr__.field.uvoffset_dsb & ~m_tmp);

			// Lsb: 15, Len: 1, [15] write crop source, 0  : from pipeline, 1 : from tiling read(for copy)
			d_tmp = (data >> 15); m_tmp = (mask >> 15) & 0x00000001;
			reg_iticpdfr__.field.wcrop_sel = (d_tmp & m_tmp) | (reg_iticpdfr__.field.wcrop_sel & ~m_tmp);

			// Lsb: 16, Len: 2, [17:16] frame image write mode
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000003;
			reg_iticpdfr__.field.writeframemode = (d_tmp & m_tmp) | (reg_iticpdfr__.field.writeframemode & ~m_tmp);

			// Lsb: 18, Len: 1, [18] one valid when WriteFrameMode set to non zero
			d_tmp = (data >> 18); m_tmp = (mask >> 18) & 0x00000001;
			reg_iticpdfr__.field.writedumpen = (d_tmp & m_tmp) | (reg_iticpdfr__.field.writedumpen & ~m_tmp);

			// Lsb: 19, Len: 1, [19] frame write done flag(read-only)
			d_tmp = (data >> 19); m_tmp = (mask >> 19) & 0x00000001;
			reg_iticpdfr__.field.writedumpdone = (d_tmp & m_tmp) | (reg_iticpdfr__.field.writedumpdone & ~m_tmp);

			// Lsb: 20, Len: 2, [21:20] current write frame counter(read only)
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x00000003;
			reg_iticpdfr__.field.frame_cnt = (d_tmp & m_tmp) | (reg_iticpdfr__.field.frame_cnt & ~m_tmp);

			// Lsb: 22, Len: 2, [23:22] write rvi interface frame cnt(read only)
			d_tmp = (data >> 22); m_tmp = (mask >> 22) & 0x00000003;
			reg_iticpdfr__.field.rvi_frame_cnt = (d_tmp & m_tmp) | (reg_iticpdfr__.field.rvi_frame_cnt & ~m_tmp);
			break;

		case 0x40FC:
			// Lsb: 0, Len: 4, [3:0] Capture write index
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_iticdpsr__.field.writeindex = (d_tmp & m_tmp) | (reg_iticdpsr__.field.writeindex & ~m_tmp);

			// Lsb: 4, Len: 1, [4] Enable the write function of the ITI capture write interface into DRAM buffer.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_iticdpsr__.field.writedram = (d_tmp & m_tmp) | (reg_iticdpsr__.field.writedram & ~m_tmp);

			// Lsb: 5, Len: 1, [5] Enable the independent  write to DRAM, ignore next pipeline RVI
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_iticdpsr__.field.independentwr = (d_tmp & m_tmp) | (reg_iticdpsr__.field.independentwr & ~m_tmp);

			// Lsb: 6, Len: 6, [11:6] rsvd
			d_tmp = (data >> 6); m_tmp = (mask >> 6) & 0x0000003F;
			reg_iticdpsr__.field.rsvd6 = (d_tmp & m_tmp) | (reg_iticdpsr__.field.rsvd6 & ~m_tmp);

			// Lsb: 12, Len: 2, [13:12] tiling write axi burst length mode, 0: burst 16, 1: burst 8, 2: burst 4
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x00000003;
			reg_iticdpsr__.field.wbstm = (d_tmp & m_tmp) | (reg_iticdpsr__.field.wbstm & ~m_tmp);
			break;

		case 0x4104:
			// Lsb: 0, Len: 32, [31:0] DC return current buffer address
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_dc_rbadr.field.rbadr = (d_tmp & m_tmp) | (reg_dc_rbadr.field.rbadr & ~m_tmp);
			break;

		case 0x4120:
			// Lsb: 0, Len: 2, [1:0] GrGb filter mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_igrgb0.field.gf_mode = (d_tmp & m_tmp) | (reg_igrgb0.field.gf_mode & ~m_tmp);
			break;

		case 0x4124:
			// Lsb: 0, Len: 12, [11:0] (0.PW.0 format)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_igrgb1.field.mingt = (d_tmp & m_tmp) | (reg_igrgb1.field.mingt & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_igrgb1.field.rsvd12 = (d_tmp & m_tmp) | (reg_igrgb1.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] (0.PW.0 format)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_igrgb1.field.maxgt = (d_tmp & m_tmp) | (reg_igrgb1.field.maxgt & ~m_tmp);
			break;

		case 0x4128:
			// Lsb: 0, Len: 12, [11:0] (0.PW.0 format)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000FFF;
			reg_igrgb2.field.badxt = (d_tmp & m_tmp) | (reg_igrgb2.field.badxt & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] 
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_igrgb2.field.rsvd12 = (d_tmp & m_tmp) | (reg_igrgb2.field.rsvd12 & ~m_tmp);

			// Lsb: 16, Len: 12, [27:16] (0.PW.0 format)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00000FFF;
			reg_igrgb2.field.badgt = (d_tmp & m_tmp) | (reg_igrgb2.field.badgt & ~m_tmp);
			break;

		case 0x4150:
			// Lsb: 0, Len: 2, [1:0] LS grid size
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_isls0.field.size = (d_tmp & m_tmp) | (reg_isls0.field.size & ~m_tmp);

			// Lsb: 2, Len: 2, [3:2] LS grid mode
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000003;
			reg_isls0.field.mode = (d_tmp & m_tmp) | (reg_isls0.field.mode & ~m_tmp);

			// Lsb: 4, Len: 1, [4] Elliptic Gating enable
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_isls0.field.ege = (d_tmp & m_tmp) | (reg_isls0.field.ege & ~m_tmp);
			break;

		case 0x4154:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_islsgba.field.rsvd0 = (d_tmp & m_tmp) | (reg_islsgba.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] Base address in QWORD (64bit) boundary, mv/mh [1.4.11]; p[0.13.4]
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_islsgba.field.sad = (d_tmp & m_tmp) | (reg_islsgba.field.sad & ~m_tmp);
			break;

		case 0x4158:
			// Lsb: 0, Len: 3, [2:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_islsgbs.field.rsvd0 = (d_tmp & m_tmp) | (reg_islsgbs.field.rsvd0 & ~m_tmp);

			// Lsb: 3, Len: 10, [12:3] Image stride (QWORD granularity)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x000003FF;
			reg_islsgbs.field.sd = (d_tmp & m_tmp) | (reg_islsgbs.field.sd & ~m_tmp);
			break;

		case 0x415C:
			// Lsb: 0, Len: 13, [12:0] Center Y cooridnate
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_islsegc.field.cy = (d_tmp & m_tmp) | (reg_islsegc.field.cy & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_islsegc.field.rsvd13 = (d_tmp & m_tmp) | (reg_islsegc.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Center X cooridnate
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_islsegc.field.cx = (d_tmp & m_tmp) | (reg_islsegc.field.cx & ~m_tmp);
			break;

		case 0x4160:
			// Lsb: 0, Len: 20, [19:0] Semi Axis Factor X [0.-8.28]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000FFFFF;
			reg_islsegsx.field.sxf = (d_tmp & m_tmp) | (reg_islsegsx.field.sxf & ~m_tmp);
			break;

		case 0x4164:
			// Lsb: 0, Len: 20, [19:0] Semi Axis Factor Y [0.-8.28]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000FFFFF;
			reg_islsegsy.field.sxy = (d_tmp & m_tmp) | (reg_islsegsy.field.sxy & ~m_tmp);
			break;

		case 0x4168:
			// Lsb: 0, Len: 13, [12:0] Transition width (normalized) Format 0.1.12
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_islsegw.field.tw = (d_tmp & m_tmp) | (reg_islsegw.field.tw & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_islsegw.field.rsvd13 = (d_tmp & m_tmp) | (reg_islsegw.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Transition width factor (normalized) TWF = 1/(2*TW)  Format 0.11.2,
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_islsegw.field.twf = (d_tmp & m_tmp) | (reg_islsegw.field.twf & ~m_tmp);
			break;

		case 0x416C:
			// Lsb: 0, Len: 8, [7:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000000FF;
			reg_islsmrd.field.rsvd0 = (d_tmp & m_tmp) | (reg_islsmrd.field.rsvd0 & ~m_tmp);

			// Lsb: 8, Len: 6, [13:8] AXI Read Request Threshold
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000003F;
			reg_islsmrd.field.thr = (d_tmp & m_tmp) | (reg_islsmrd.field.thr & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_islsmrd.field.rsvd14 = (d_tmp & m_tmp) | (reg_islsmrd.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] AXI Maximum length(zero based)
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_islsmrd.field.len = (d_tmp & m_tmp) | (reg_islsmrd.field.len & ~m_tmp);
			break;

		case 0x4280:
			// Lsb: 0, Len: 13, [12:0] Horizontal offset, [0.13.0], must be set to even number
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_wdr_hor.field.hox = (d_tmp & m_tmp) | (reg_wdr_hor.field.hox & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_wdr_hor.field.rsvd13 = (d_tmp & m_tmp) | (reg_wdr_hor.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] Vertical offset, [0.13.0], must be set to even number
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_wdr_hor.field.hoy = (d_tmp & m_tmp) | (reg_wdr_hor.field.hoy & ~m_tmp);
			break;

		case 0x4284:
			// Lsb: 0, Len: 4, [3:0] local window width(2^BWx), range from 6 to 10
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_wdr_lwr.field.bwx = (d_tmp & m_tmp) | (reg_wdr_lwr.field.bwx & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] local window height(2^BWy), range from 6 to 10
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_wdr_lwr.field.bwy = (d_tmp & m_tmp) | (reg_wdr_lwr.field.bwy & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] the distance between adjacent local windows in horizontal direction(2^BUx), range from 6 to 10
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_wdr_lwr.field.bux = (d_tmp & m_tmp) | (reg_wdr_lwr.field.bux & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] the distance between adjacent local windows in vertical direction(2^BUy), range from 6 to 10
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_wdr_lwr.field.buy = (d_tmp & m_tmp) | (reg_wdr_lwr.field.buy & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] max window number in x direction
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_wdr_lwr.field.n = (d_tmp & m_tmp) | (reg_wdr_lwr.field.n & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_wdr_lwr.field.rsvd21 = (d_tmp & m_tmp) | (reg_wdr_lwr.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] max window number in y direction
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_wdr_lwr.field.m = (d_tmp & m_tmp) | (reg_wdr_lwr.field.m & ~m_tmp);
			break;

		case 0x4288:
			// Lsb: 0, Len: 10, [9:0] Flood threshold [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_thr0.field.tmin = (d_tmp & m_tmp) | (reg_wdr_thr0.field.tmin & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_thr0.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_thr0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Trim threshold [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_thr0.field.tmax = (d_tmp & m_tmp) | (reg_wdr_thr0.field.tmax & ~m_tmp);
			break;

		case 0x428C:
			// Lsb: 0, Len: 3, [2:0] window bin count scale down factor [0.3.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000007;
			reg_wdr_scr.field.bsx = (d_tmp & m_tmp) | (reg_wdr_scr.field.bsx & ~m_tmp);

			// Lsb: 3, Len: 1, [3] 
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_wdr_scr.field.rsvd3 = (d_tmp & m_tmp) | (reg_wdr_scr.field.rsvd3 & ~m_tmp);

			// Lsb: 4, Len: 3, [6:4] window bin count scale down factor [0.3.0]
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000007;
			reg_wdr_scr.field.bsy = (d_tmp & m_tmp) | (reg_wdr_scr.field.bsy & ~m_tmp);

			// Lsb: 7, Len: 1, [7] 
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x00000001;
			reg_wdr_scr.field.rsvd7 = (d_tmp & m_tmp) | (reg_wdr_scr.field.rsvd7 & ~m_tmp);

			// Lsb: 8, Len: 1, [8] local window data format in dram, 0 : compress mode, 6 bin count each 2W; 1: normal mode, one bin count two byte
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x00000001;
			reg_wdr_scr.field.datfmt = (d_tmp & m_tmp) | (reg_wdr_scr.field.datfmt & ~m_tmp);

			// Lsb: 9, Len: 1, [9] force use level 0 spatial weight only(debug only)
			d_tmp = (data >> 9); m_tmp = (mask >> 9) & 0x00000001;
			reg_wdr_scr.field.l0sw_force = (d_tmp & m_tmp) | (reg_wdr_scr.field.l0sw_force & ~m_tmp);
			break;

		case 0x4290:
			// Lsb: 0, Len: 7, [6:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000007F;
			reg_wdr_ibaddr0.field.rsvd0 = (d_tmp & m_tmp) | (reg_wdr_ibaddr0.field.rsvd0 & ~m_tmp);

			// Lsb: 7, Len: 25, [31:7] wdr internal buffer0 address(8x16byte align)
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x01FFFFFF;
			reg_wdr_ibaddr0.field.addr = (d_tmp & m_tmp) | (reg_wdr_ibaddr0.field.addr & ~m_tmp);
			break;

		case 0x4294:
			// Lsb: 0, Len: 7, [6:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000007F;
			reg_wdr_ibaddr1.field.rsvd0 = (d_tmp & m_tmp) | (reg_wdr_ibaddr1.field.rsvd0 & ~m_tmp);

			// Lsb: 7, Len: 25, [31:7] wdr internal buffer1 address(8x16byte align)
			d_tmp = (data >> 7); m_tmp = (mask >> 7) & 0x01FFFFFF;
			reg_wdr_ibaddr1.field.addr = (d_tmp & m_tmp) | (reg_wdr_ibaddr1.field.addr & ~m_tmp);
			break;

		case 0x4298:
			// Lsb: 0, Len: 10, [9:0] Flood threshold [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_thr1.field.tmin = (d_tmp & m_tmp) | (reg_wdr_thr1.field.tmin & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_thr1.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_thr1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Trim threshold [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_thr1.field.tmax = (d_tmp & m_tmp) | (reg_wdr_thr1.field.tmax & ~m_tmp);
			break;

		case 0x429C:
			// Lsb: 0, Len: 10, [9:0] Flood threshold [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_thr2.field.tmin = (d_tmp & m_tmp) | (reg_wdr_thr2.field.tmin & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_thr2.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_thr2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Trim threshold [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_thr2.field.tmax = (d_tmp & m_tmp) | (reg_wdr_thr2.field.tmax & ~m_tmp);
			break;

		case 0x42A0:
			// Lsb: 0, Len: 10, [9:0] Flood threshold [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_thr3.field.tmin = (d_tmp & m_tmp) | (reg_wdr_thr3.field.tmin & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_thr3.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_thr3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] Trim threshold [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_thr3.field.tmax = (d_tmp & m_tmp) | (reg_wdr_thr3.field.tmax & ~m_tmp);
			break;

		case 0x42A4:
			// Lsb: 0, Len: 5, [4:0] level 0 window spatial weight [0.5.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_wdr_wsr.field.ws0 = (d_tmp & m_tmp) | (reg_wdr_wsr.field.ws0 & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_wdr_wsr.field.rsvd5 = (d_tmp & m_tmp) | (reg_wdr_wsr.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] level 1 window spatial weight [0.5.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_wdr_wsr.field.ws1 = (d_tmp & m_tmp) | (reg_wdr_wsr.field.ws1 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_wdr_wsr.field.rsvd13 = (d_tmp & m_tmp) | (reg_wdr_wsr.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] level 2 window spatial weight [0.5.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_wdr_wsr.field.ws2 = (d_tmp & m_tmp) | (reg_wdr_wsr.field.ws2 & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_wdr_wsr.field.rsvd21 = (d_tmp & m_tmp) | (reg_wdr_wsr.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] level 3 window spatial weight [0.5.0]
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_wdr_wsr.field.ws3 = (d_tmp & m_tmp) | (reg_wdr_wsr.field.ws3 & ~m_tmp);
			break;

		case 0x42A8:
			// Lsb: 0, Len: 10, [9:0] variance value [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_vr0.field.v0 = (d_tmp & m_tmp) | (reg_wdr_vr0.field.v0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_vr0.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_vr0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] variance value [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_vr0.field.v1 = (d_tmp & m_tmp) | (reg_wdr_vr0.field.v1 & ~m_tmp);
			break;

		case 0x42AC:
			// Lsb: 0, Len: 10, [9:0] variance value [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_vr1.field.v2 = (d_tmp & m_tmp) | (reg_wdr_vr1.field.v2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_vr1.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_vr1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] variance value  [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_vr1.field.v3 = (d_tmp & m_tmp) | (reg_wdr_vr1.field.v3 & ~m_tmp);
			break;

		case 0x42B0:
			// Lsb: 0, Len: 10, [9:0] variance value  [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_vr2.field.v4 = (d_tmp & m_tmp) | (reg_wdr_vr2.field.v4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_vr2.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_vr2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] variance value  [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_vr2.field.v5 = (d_tmp & m_tmp) | (reg_wdr_vr2.field.v5 & ~m_tmp);
			break;

		case 0x42B4:
			// Lsb: 0, Len: 10, [9:0] variance value  [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_vr3.field.v6 = (d_tmp & m_tmp) | (reg_wdr_vr3.field.v6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_wdr_vr3.field.rsvd10 = (d_tmp & m_tmp) | (reg_wdr_vr3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] variance value  [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_wdr_vr3.field.v7 = (d_tmp & m_tmp) | (reg_wdr_vr3.field.v7 & ~m_tmp);
			break;

		case 0x42B8:
			// Lsb: 0, Len: 5, [4:0] intensity weight [0.5.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_wdr_wr0.field.w0 = (d_tmp & m_tmp) | (reg_wdr_wr0.field.w0 & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_wdr_wr0.field.rsvd5 = (d_tmp & m_tmp) | (reg_wdr_wr0.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] intensity weight [0.5.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_wdr_wr0.field.w1 = (d_tmp & m_tmp) | (reg_wdr_wr0.field.w1 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_wdr_wr0.field.rsvd13 = (d_tmp & m_tmp) | (reg_wdr_wr0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] intensity weight [0.5.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_wdr_wr0.field.w2 = (d_tmp & m_tmp) | (reg_wdr_wr0.field.w2 & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_wdr_wr0.field.rsvd21 = (d_tmp & m_tmp) | (reg_wdr_wr0.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] intensity weight [0.5.0]
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_wdr_wr0.field.w3 = (d_tmp & m_tmp) | (reg_wdr_wr0.field.w3 & ~m_tmp);
			break;

		case 0x42BC:
			// Lsb: 0, Len: 5, [4:0] intensity weight [0.5.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000001F;
			reg_wdr_wr1.field.w4 = (d_tmp & m_tmp) | (reg_wdr_wr1.field.w4 & ~m_tmp);

			// Lsb: 5, Len: 3, [7:5] 
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000007;
			reg_wdr_wr1.field.rsvd5 = (d_tmp & m_tmp) | (reg_wdr_wr1.field.rsvd5 & ~m_tmp);

			// Lsb: 8, Len: 5, [12:8] intensity weight [0.5.0]
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000001F;
			reg_wdr_wr1.field.w5 = (d_tmp & m_tmp) | (reg_wdr_wr1.field.w5 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_wdr_wr1.field.rsvd13 = (d_tmp & m_tmp) | (reg_wdr_wr1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 5, [20:16] intensity weight [0.5.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000001F;
			reg_wdr_wr1.field.w6 = (d_tmp & m_tmp) | (reg_wdr_wr1.field.w6 & ~m_tmp);

			// Lsb: 21, Len: 3, [23:21] 
			d_tmp = (data >> 21); m_tmp = (mask >> 21) & 0x00000007;
			reg_wdr_wr1.field.rsvd21 = (d_tmp & m_tmp) | (reg_wdr_wr1.field.rsvd21 & ~m_tmp);

			// Lsb: 24, Len: 5, [28:24] intensity weight [0.5.0]
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000001F;
			reg_wdr_wr1.field.w7 = (d_tmp & m_tmp) | (reg_wdr_wr1.field.w7 & ~m_tmp);
			break;

		case 0x42C0:
			// Lsb: 0, Len: 11, [10:0] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_wdr_sr0.field.s0 = (d_tmp & m_tmp) | (reg_wdr_sr0.field.s0 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_wdr_sr0.field.rsvd11 = (d_tmp & m_tmp) | (reg_wdr_sr0.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_wdr_sr0.field.s1 = (d_tmp & m_tmp) | (reg_wdr_sr0.field.s1 & ~m_tmp);
			break;

		case 0x42C4:
			// Lsb: 0, Len: 11, [10:0] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_wdr_sr1.field.s2 = (d_tmp & m_tmp) | (reg_wdr_sr1.field.s2 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_wdr_sr1.field.rsvd11 = (d_tmp & m_tmp) | (reg_wdr_sr1.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_wdr_sr1.field.s3 = (d_tmp & m_tmp) | (reg_wdr_sr1.field.s3 & ~m_tmp);
			break;

		case 0x42C8:
			// Lsb: 0, Len: 11, [10:0] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_wdr_sr2.field.s4 = (d_tmp & m_tmp) | (reg_wdr_sr2.field.s4 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_wdr_sr2.field.rsvd11 = (d_tmp & m_tmp) | (reg_wdr_sr2.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_wdr_sr2.field.s5 = (d_tmp & m_tmp) | (reg_wdr_sr2.field.s5 & ~m_tmp);
			break;

		case 0x42CC:
			// Lsb: 0, Len: 11, [10:0] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_wdr_sr3.field.s6 = (d_tmp & m_tmp) | (reg_wdr_sr3.field.s6 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_wdr_sr3.field.rsvd11 = (d_tmp & m_tmp) | (reg_wdr_sr3.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] intensity weigth slope  [1.0.10]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_wdr_sr3.field.s7 = (d_tmp & m_tmp) | (reg_wdr_sr3.field.s7 & ~m_tmp);
			break;

		case 0x42D0:
			// Lsb: 0, Len: 10, [9:0] level 3 histogram sum factor [0.0.10]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_wdr_l3hsr.field.factor = (d_tmp & m_tmp) | (reg_wdr_l3hsr.field.factor & ~m_tmp);
			break;

		case 0x433C:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_15.field.gval = (d_tmp & m_tmp) | (reg_igrval_15.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_15.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_15.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.[1.4.11]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_15.field.sgval = (d_tmp & m_tmp) | (reg_igrval_15.field.sgval & ~m_tmp);
			break;

		case 0x4340:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_16.field.gval = (d_tmp & m_tmp) | (reg_igrval_16.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_16.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_16.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_16.field.sgval = (d_tmp & m_tmp) | (reg_igrval_16.field.sgval & ~m_tmp);
			break;

		case 0x4344:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_17.field.gval = (d_tmp & m_tmp) | (reg_igrval_17.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_17.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_17.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_17.field.sgval = (d_tmp & m_tmp) | (reg_igrval_17.field.sgval & ~m_tmp);
			break;

		case 0x4348:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_18.field.gval = (d_tmp & m_tmp) | (reg_igrval_18.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_18.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_18.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_18.field.sgval = (d_tmp & m_tmp) | (reg_igrval_18.field.sgval & ~m_tmp);
			break;

		case 0x434C:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_19.field.gval = (d_tmp & m_tmp) | (reg_igrval_19.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_19.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_19.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_19.field.sgval = (d_tmp & m_tmp) | (reg_igrval_19.field.sgval & ~m_tmp);
			break;

		case 0x4350:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_20.field.gval = (d_tmp & m_tmp) | (reg_igrval_20.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_20.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_20.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_20.field.sgval = (d_tmp & m_tmp) | (reg_igrval_20.field.sgval & ~m_tmp);
			break;

		case 0x4354:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_21.field.gval = (d_tmp & m_tmp) | (reg_igrval_21.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_21.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_21.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_21.field.sgval = (d_tmp & m_tmp) | (reg_igrval_21.field.sgval & ~m_tmp);
			break;

		case 0x4358:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_22.field.gval = (d_tmp & m_tmp) | (reg_igrval_22.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_22.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_22.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_22.field.sgval = (d_tmp & m_tmp) | (reg_igrval_22.field.sgval & ~m_tmp);
			break;

		case 0x435C:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_23.field.gval = (d_tmp & m_tmp) | (reg_igrval_23.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_23.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_23.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_23.field.sgval = (d_tmp & m_tmp) | (reg_igrval_23.field.sgval & ~m_tmp);
			break;

		case 0x4360:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_24.field.gval = (d_tmp & m_tmp) | (reg_igrval_24.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_24.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_24.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_24.field.sgval = (d_tmp & m_tmp) | (reg_igrval_24.field.sgval & ~m_tmp);
			break;

		case 0x4364:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_25.field.gval = (d_tmp & m_tmp) | (reg_igrval_25.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_25.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_25.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_25.field.sgval = (d_tmp & m_tmp) | (reg_igrval_25.field.sgval & ~m_tmp);
			break;

		case 0x4368:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_26.field.gval = (d_tmp & m_tmp) | (reg_igrval_26.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_26.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_26.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_26.field.sgval = (d_tmp & m_tmp) | (reg_igrval_26.field.sgval & ~m_tmp);
			break;

		case 0x436C:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_27.field.gval = (d_tmp & m_tmp) | (reg_igrval_27.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_27.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_27.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_27.field.sgval = (d_tmp & m_tmp) | (reg_igrval_27.field.sgval & ~m_tmp);
			break;

		case 0x4370:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_28.field.gval = (d_tmp & m_tmp) | (reg_igrval_28.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_28.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_28.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_28.field.sgval = (d_tmp & m_tmp) | (reg_igrval_28.field.sgval & ~m_tmp);
			break;

		case 0x4374:
			// Lsb: 0, Len: 14, [13:0] Forward gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_29.field.gval = (d_tmp & m_tmp) | (reg_igrval_29.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_29.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_29.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Forward gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_29.field.sgval = (d_tmp & m_tmp) | (reg_igrval_29.field.sgval & ~m_tmp);
			break;

		case 0x4378:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_30.field.gval = (d_tmp & m_tmp) | (reg_igrval_30.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_30.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_30.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.[1.4.11]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_30.field.sgval = (d_tmp & m_tmp) | (reg_igrval_30.field.sgval & ~m_tmp);
			break;

		case 0x437C:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_31.field.gval = (d_tmp & m_tmp) | (reg_igrval_31.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_31.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_31.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_31.field.sgval = (d_tmp & m_tmp) | (reg_igrval_31.field.sgval & ~m_tmp);
			break;

		case 0x4380:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_32.field.gval = (d_tmp & m_tmp) | (reg_igrval_32.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_32.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_32.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_32.field.sgval = (d_tmp & m_tmp) | (reg_igrval_32.field.sgval & ~m_tmp);
			break;

		case 0x4384:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_33.field.gval = (d_tmp & m_tmp) | (reg_igrval_33.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_33.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_33.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_33.field.sgval = (d_tmp & m_tmp) | (reg_igrval_33.field.sgval & ~m_tmp);
			break;

		case 0x4388:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_34.field.gval = (d_tmp & m_tmp) | (reg_igrval_34.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_34.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_34.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_34.field.sgval = (d_tmp & m_tmp) | (reg_igrval_34.field.sgval & ~m_tmp);
			break;

		case 0x438C:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_35.field.gval = (d_tmp & m_tmp) | (reg_igrval_35.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_35.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_35.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_35.field.sgval = (d_tmp & m_tmp) | (reg_igrval_35.field.sgval & ~m_tmp);
			break;

		case 0x4390:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_36.field.gval = (d_tmp & m_tmp) | (reg_igrval_36.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_36.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_36.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_36.field.sgval = (d_tmp & m_tmp) | (reg_igrval_36.field.sgval & ~m_tmp);
			break;

		case 0x4394:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_37.field.gval = (d_tmp & m_tmp) | (reg_igrval_37.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_37.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_37.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_37.field.sgval = (d_tmp & m_tmp) | (reg_igrval_37.field.sgval & ~m_tmp);
			break;

		case 0x4398:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_38.field.gval = (d_tmp & m_tmp) | (reg_igrval_38.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_38.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_38.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_38.field.sgval = (d_tmp & m_tmp) | (reg_igrval_38.field.sgval & ~m_tmp);
			break;

		case 0x439C:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_39.field.gval = (d_tmp & m_tmp) | (reg_igrval_39.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_39.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_39.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_39.field.sgval = (d_tmp & m_tmp) | (reg_igrval_39.field.sgval & ~m_tmp);
			break;

		case 0x43A0:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_40.field.gval = (d_tmp & m_tmp) | (reg_igrval_40.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_40.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_40.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_40.field.sgval = (d_tmp & m_tmp) | (reg_igrval_40.field.sgval & ~m_tmp);
			break;

		case 0x43A4:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_41.field.gval = (d_tmp & m_tmp) | (reg_igrval_41.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_41.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_41.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_41.field.sgval = (d_tmp & m_tmp) | (reg_igrval_41.field.sgval & ~m_tmp);
			break;

		case 0x43A8:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_42.field.gval = (d_tmp & m_tmp) | (reg_igrval_42.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_42.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_42.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_42.field.sgval = (d_tmp & m_tmp) | (reg_igrval_42.field.sgval & ~m_tmp);
			break;

		case 0x43AC:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_43.field.gval = (d_tmp & m_tmp) | (reg_igrval_43.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_43.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_43.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_43.field.sgval = (d_tmp & m_tmp) | (reg_igrval_43.field.sgval & ~m_tmp);
			break;

		case 0x43B0:
			// Lsb: 0, Len: 14, [13:0] Reserve gamma value. [0.14/PW.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00003FFF;
			reg_igrval_44.field.gval = (d_tmp & m_tmp) | (reg_igrval_44.field.gval & ~m_tmp);

			// Lsb: 14, Len: 2, [15:14] 
			d_tmp = (data >> 14); m_tmp = (mask >> 14) & 0x00000003;
			reg_igrval_44.field.rsvd14 = (d_tmp & m_tmp) | (reg_igrval_44.field.rsvd14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] Reserve gamma slope value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_igrval_44.field.sgval = (d_tmp & m_tmp) | (reg_igrval_44.field.sgval & ~m_tmp);
			break;

		case 0x4400:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_0.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_0.field.coeff_b & ~m_tmp);
			break;

		case 0x4404:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_1.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_1.field.coeff_b & ~m_tmp);
			break;

		case 0x4408:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_2.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_2.field.coeff_b & ~m_tmp);
			break;

		case 0x440C:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_3.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_3.field.coeff_b & ~m_tmp);
			break;

		case 0x4410:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_4.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_4.field.coeff_b & ~m_tmp);
			break;

		case 0x4414:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_5.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_5.field.coeff_b & ~m_tmp);
			break;

		case 0x4418:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_6.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_6.field.coeff_b & ~m_tmp);
			break;

		case 0x441C:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_7.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_7.field.coeff_b & ~m_tmp);
			break;

		case 0x4420:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_8.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_8.field.coeff_b & ~m_tmp);
			break;

		case 0x4424:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_9.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_9.field.coeff_b & ~m_tmp);
			break;

		case 0x4428:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_10.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_10.field.coeff_b & ~m_tmp);
			break;

		case 0x442C:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_11.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_11.field.coeff_b & ~m_tmp);
			break;

		case 0x4430:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_12.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_12.field.coeff_b & ~m_tmp);
			break;

		case 0x4434:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_13.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_13.field.coeff_b & ~m_tmp);
			break;

		case 0x4438:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_14.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_14.field.coeff_b & ~m_tmp);
			break;

		case 0x443C:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_15.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_15.field.coeff_b & ~m_tmp);
			break;

		case 0x4440:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_16.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_16.field.coeff_b & ~m_tmp);
			break;

		case 0x4444:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_17.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_17.field.coeff_b & ~m_tmp);
			break;

		case 0x4448:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_18.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_18.field.coeff_b & ~m_tmp);
			break;

		case 0x444C:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_19.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_19.field.coeff_b & ~m_tmp);
			break;

		case 0x4450:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_20.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_20.field.coeff_b & ~m_tmp);
			break;

		case 0x4454:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_21.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_21.field.coeff_b & ~m_tmp);
			break;

		case 0x4458:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_22.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_22.field.coeff_b & ~m_tmp);
			break;

		case 0x445C:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_23.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_23.field.coeff_b & ~m_tmp);
			break;

		case 0x4460:
			// Lsb: 0, Len: 32, [31:0] COEFF_B[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf0_cb_24.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_24.field.coeff_b & ~m_tmp);
			break;

		case 0x4464:
			// Lsb: 0, Len: 10, [9:0] COEFF_B[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf0_cb_25.field.coeff_b = (d_tmp & m_tmp) | (reg_ipf0_cb_25.field.coeff_b & ~m_tmp);
			break;

		case 0x4468:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_0.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_0.field.coeff_rg & ~m_tmp);
			break;

		case 0x446C:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_1.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_1.field.coeff_rg & ~m_tmp);
			break;

		case 0x4470:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_2.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_2.field.coeff_rg & ~m_tmp);
			break;

		case 0x4474:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG[41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_3.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_3.field.coeff_rg & ~m_tmp);
			break;

		case 0x4478:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_4.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_4.field.coeff_rg & ~m_tmp);
			break;

		case 0x447C:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_5.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_5.field.coeff_rg & ~m_tmp);
			break;

		case 0x4480:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_6.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_6.field.coeff_rg & ~m_tmp);
			break;

		case 0x4484:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_7.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_7.field.coeff_rg & ~m_tmp);
			break;

		case 0x4488:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_8.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_8.field.coeff_rg & ~m_tmp);
			break;

		case 0x448C:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_9.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_9.field.coeff_rg & ~m_tmp);
			break;

		case 0x4490:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_10.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_10.field.coeff_rg & ~m_tmp);
			break;

		case 0x4494:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_11.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_11.field.coeff_rg & ~m_tmp);
			break;

		case 0x4498:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_12.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_12.field.coeff_rg & ~m_tmp);
			break;

		case 0x449C:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_13.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_13.field.coeff_rg & ~m_tmp);
			break;

		case 0x44A0:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_14.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_14.field.coeff_rg & ~m_tmp);
			break;

		case 0x44A4:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_15.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_15.field.coeff_rg & ~m_tmp);
			break;

		case 0x44A8:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_16.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_16.field.coeff_rg & ~m_tmp);
			break;

		case 0x44AC:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_17.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_17.field.coeff_rg & ~m_tmp);
			break;

		case 0x44B0:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_18.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_18.field.coeff_rg & ~m_tmp);
			break;

		case 0x44B4:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_19.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_19.field.coeff_rg & ~m_tmp);
			break;

		case 0x44B8:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_20.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_20.field.coeff_rg & ~m_tmp);
			break;

		case 0x44BC:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_21.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_21.field.coeff_rg & ~m_tmp);
			break;

		case 0x44C0:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_22.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_22.field.coeff_rg & ~m_tmp);
			break;

		case 0x44C4:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_23.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_23.field.coeff_rg & ~m_tmp);
			break;

		case 0x44C8:
			// Lsb: 0, Len: 32, [31:0] COEFF_RG [31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ipf1_crg_24.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_24.field.coeff_rg & ~m_tmp);
			break;

		case 0x44CC:
			// Lsb: 0, Len: 10, [9:0] COEFF_RG [41:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ipf1_crg_25.field.coeff_rg = (d_tmp & m_tmp) | (reg_ipf1_crg_25.field.coeff_rg & ~m_tmp);
			break;

		case 0x4500:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_0.field.g_f0_0 = (d_tmp & m_tmp) | (reg_ipf2_f_0.field.g_f0_0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_0.field.r_f0_0 = (d_tmp & m_tmp) | (reg_ipf2_f_0.field.r_f0_0 & ~m_tmp);
			break;

		case 0x4504:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_1.field.g_f0_1 = (d_tmp & m_tmp) | (reg_ipf2_f_1.field.g_f0_1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_1.field.r_f0_1 = (d_tmp & m_tmp) | (reg_ipf2_f_1.field.r_f0_1 & ~m_tmp);
			break;

		case 0x4508:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_2.field.g_f0_2 = (d_tmp & m_tmp) | (reg_ipf2_f_2.field.g_f0_2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_2.field.r_f0_2 = (d_tmp & m_tmp) | (reg_ipf2_f_2.field.r_f0_2 & ~m_tmp);
			break;

		case 0x450C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_3.field.g_f0_3 = (d_tmp & m_tmp) | (reg_ipf2_f_3.field.g_f0_3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_3.field.r_f0_3 = (d_tmp & m_tmp) | (reg_ipf2_f_3.field.r_f0_3 & ~m_tmp);
			break;

		case 0x4510:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_4.field.g_f0_4 = (d_tmp & m_tmp) | (reg_ipf2_f_4.field.g_f0_4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_4.field.r_f0_4 = (d_tmp & m_tmp) | (reg_ipf2_f_4.field.r_f0_4 & ~m_tmp);
			break;

		case 0x4514:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_5.field.g_f0_5 = (d_tmp & m_tmp) | (reg_ipf2_f_5.field.g_f0_5 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_5.field.r_f0_5 = (d_tmp & m_tmp) | (reg_ipf2_f_5.field.r_f0_5 & ~m_tmp);
			break;

		case 0x4518:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_6.field.g_f0_6 = (d_tmp & m_tmp) | (reg_ipf2_f_6.field.g_f0_6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_6.field.r_f0_6 = (d_tmp & m_tmp) | (reg_ipf2_f_6.field.r_f0_6 & ~m_tmp);
			break;

		case 0x451C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_7.field.g_f0_7 = (d_tmp & m_tmp) | (reg_ipf2_f_7.field.g_f0_7 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_7.field.r_f0_7 = (d_tmp & m_tmp) | (reg_ipf2_f_7.field.r_f0_7 & ~m_tmp);
			break;

		case 0x4520:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_8.field.g_f0_8 = (d_tmp & m_tmp) | (reg_ipf2_f_8.field.g_f0_8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_8.field.r_f0_8 = (d_tmp & m_tmp) | (reg_ipf2_f_8.field.r_f0_8 & ~m_tmp);
			break;

		case 0x4524:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_9.field.g_f0_9 = (d_tmp & m_tmp) | (reg_ipf2_f_9.field.g_f0_9 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_9.field.r_f0_9 = (d_tmp & m_tmp) | (reg_ipf2_f_9.field.r_f0_9 & ~m_tmp);
			break;

		case 0x4528:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_10.field.g_f0_10 = (d_tmp & m_tmp) | (reg_ipf2_f_10.field.g_f0_10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_10.field.r_f0_10 = (d_tmp & m_tmp) | (reg_ipf2_f_10.field.r_f0_10 & ~m_tmp);
			break;

		case 0x452C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_11.field.g_f0_11 = (d_tmp & m_tmp) | (reg_ipf2_f_11.field.g_f0_11 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_11.field.r_f0_11 = (d_tmp & m_tmp) | (reg_ipf2_f_11.field.r_f0_11 & ~m_tmp);
			break;

		case 0x4530:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_12.field.g_f0_12 = (d_tmp & m_tmp) | (reg_ipf2_f_12.field.g_f0_12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_12.field.r_f0_12 = (d_tmp & m_tmp) | (reg_ipf2_f_12.field.r_f0_12 & ~m_tmp);
			break;

		case 0x4534:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_13.field.g_f0_13 = (d_tmp & m_tmp) | (reg_ipf2_f_13.field.g_f0_13 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_13.field.r_f1_0 = (d_tmp & m_tmp) | (reg_ipf2_f_13.field.r_f1_0 & ~m_tmp);
			break;

		case 0x4538:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_14.field.g_f0_14 = (d_tmp & m_tmp) | (reg_ipf2_f_14.field.g_f0_14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_14.field.r_f1_1 = (d_tmp & m_tmp) | (reg_ipf2_f_14.field.r_f1_1 & ~m_tmp);
			break;

		case 0x453C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_15.field.g_f0_15 = (d_tmp & m_tmp) | (reg_ipf2_f_15.field.g_f0_15 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_15.field.r_f1_2 = (d_tmp & m_tmp) | (reg_ipf2_f_15.field.r_f1_2 & ~m_tmp);
			break;

		case 0x4540:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_16.field.g_f0_16 = (d_tmp & m_tmp) | (reg_ipf2_f_16.field.g_f0_16 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_16.field.r_f1_3 = (d_tmp & m_tmp) | (reg_ipf2_f_16.field.r_f1_3 & ~m_tmp);
			break;

		case 0x4544:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_17.field.g_f0_17 = (d_tmp & m_tmp) | (reg_ipf2_f_17.field.g_f0_17 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_17.field.r_f1_4 = (d_tmp & m_tmp) | (reg_ipf2_f_17.field.r_f1_4 & ~m_tmp);
			break;

		case 0x4548:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_18.field.g_f0_18 = (d_tmp & m_tmp) | (reg_ipf2_f_18.field.g_f0_18 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_18.field.r_f1_5 = (d_tmp & m_tmp) | (reg_ipf2_f_18.field.r_f1_5 & ~m_tmp);
			break;

		case 0x454C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_19.field.g_f1_0 = (d_tmp & m_tmp) | (reg_ipf2_f_19.field.g_f1_0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_19.field.r_f1_6 = (d_tmp & m_tmp) | (reg_ipf2_f_19.field.r_f1_6 & ~m_tmp);
			break;

		case 0x4550:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_20.field.g_f1_1 = (d_tmp & m_tmp) | (reg_ipf2_f_20.field.g_f1_1 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_20.field.r_f1_7 = (d_tmp & m_tmp) | (reg_ipf2_f_20.field.r_f1_7 & ~m_tmp);
			break;

		case 0x4554:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_21.field.g_f1_2 = (d_tmp & m_tmp) | (reg_ipf2_f_21.field.g_f1_2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_21.field.r_f1_8 = (d_tmp & m_tmp) | (reg_ipf2_f_21.field.r_f1_8 & ~m_tmp);
			break;

		case 0x4558:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_22.field.g_f1_3 = (d_tmp & m_tmp) | (reg_ipf2_f_22.field.g_f1_3 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_22.field.r_f1_9 = (d_tmp & m_tmp) | (reg_ipf2_f_22.field.r_f1_9 & ~m_tmp);
			break;

		case 0x455C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_23.field.g_f1_4 = (d_tmp & m_tmp) | (reg_ipf2_f_23.field.g_f1_4 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_23.field.r_f1_10 = (d_tmp & m_tmp) | (reg_ipf2_f_23.field.r_f1_10 & ~m_tmp);
			break;

		case 0x4560:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_24.field.g_f1_5 = (d_tmp & m_tmp) | (reg_ipf2_f_24.field.g_f1_5 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_24.field.r_f1_11 = (d_tmp & m_tmp) | (reg_ipf2_f_24.field.r_f1_11 & ~m_tmp);
			break;

		case 0x4564:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_25.field.g_f1_6 = (d_tmp & m_tmp) | (reg_ipf2_f_25.field.g_f1_6 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Red filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_25.field.r_f1_12 = (d_tmp & m_tmp) | (reg_ipf2_f_25.field.r_f1_12 & ~m_tmp);
			break;

		case 0x4568:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_26.field.g_f1_7 = (d_tmp & m_tmp) | (reg_ipf2_f_26.field.g_f1_7 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_26.field.b_f0_0 = (d_tmp & m_tmp) | (reg_ipf2_f_26.field.b_f0_0 & ~m_tmp);
			break;

		case 0x456C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_27.field.g_f1_8 = (d_tmp & m_tmp) | (reg_ipf2_f_27.field.g_f1_8 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_27.field.b_f0_1 = (d_tmp & m_tmp) | (reg_ipf2_f_27.field.b_f0_1 & ~m_tmp);
			break;

		case 0x4570:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_28.field.g_f1_9 = (d_tmp & m_tmp) | (reg_ipf2_f_28.field.g_f1_9 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_28.field.b_f0_2 = (d_tmp & m_tmp) | (reg_ipf2_f_28.field.b_f0_2 & ~m_tmp);
			break;

		case 0x4574:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_29.field.g_f1_10 = (d_tmp & m_tmp) | (reg_ipf2_f_29.field.g_f1_10 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_29.field.b_f0_3 = (d_tmp & m_tmp) | (reg_ipf2_f_29.field.b_f0_3 & ~m_tmp);
			break;

		case 0x4578:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_30.field.g_f1_11 = (d_tmp & m_tmp) | (reg_ipf2_f_30.field.g_f1_11 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_30.field.b_f0_4 = (d_tmp & m_tmp) | (reg_ipf2_f_30.field.b_f0_4 & ~m_tmp);
			break;

		case 0x457C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_31.field.g_f1_12 = (d_tmp & m_tmp) | (reg_ipf2_f_31.field.g_f1_12 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_31.field.b_f0_5 = (d_tmp & m_tmp) | (reg_ipf2_f_31.field.b_f0_5 & ~m_tmp);
			break;

		case 0x4580:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_32.field.g_f1_13 = (d_tmp & m_tmp) | (reg_ipf2_f_32.field.g_f1_13 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_32.field.b_f0_6 = (d_tmp & m_tmp) | (reg_ipf2_f_32.field.b_f0_6 & ~m_tmp);
			break;

		case 0x4584:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_33.field.g_f1_14 = (d_tmp & m_tmp) | (reg_ipf2_f_33.field.g_f1_14 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_33.field.b_f0_7 = (d_tmp & m_tmp) | (reg_ipf2_f_33.field.b_f0_7 & ~m_tmp);
			break;

		case 0x4588:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_34.field.g_f1_15 = (d_tmp & m_tmp) | (reg_ipf2_f_34.field.g_f1_15 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_34.field.b_f0_8 = (d_tmp & m_tmp) | (reg_ipf2_f_34.field.b_f0_8 & ~m_tmp);
			break;

		case 0x458C:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_35.field.g_f1_16 = (d_tmp & m_tmp) | (reg_ipf2_f_35.field.g_f1_16 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_35.field.b_f0_9 = (d_tmp & m_tmp) | (reg_ipf2_f_35.field.b_f0_9 & ~m_tmp);
			break;

		case 0x4590:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_36.field.g_f1_17 = (d_tmp & m_tmp) | (reg_ipf2_f_36.field.g_f1_17 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_36.field.b_f0_10 = (d_tmp & m_tmp) | (reg_ipf2_f_36.field.b_f0_10 & ~m_tmp);
			break;

		case 0x4594:
			// Lsb: 0, Len: 16, [15:0] PF correction Green filter value.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_37.field.g_f1_18 = (d_tmp & m_tmp) | (reg_ipf2_f_37.field.g_f1_18 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_37.field.b_f0_11 = (d_tmp & m_tmp) | (reg_ipf2_f_37.field.b_f0_11 & ~m_tmp);
			break;

		case 0x4598:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_38.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_38.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_38.field.b_f0_12 = (d_tmp & m_tmp) | (reg_ipf2_f_38.field.b_f0_12 & ~m_tmp);
			break;

		case 0x459C:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_39.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_39.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_39.field.b_f1_0 = (d_tmp & m_tmp) | (reg_ipf2_f_39.field.b_f1_0 & ~m_tmp);
			break;

		case 0x45A0:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_40.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_40.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_40.field.b_f1_1 = (d_tmp & m_tmp) | (reg_ipf2_f_40.field.b_f1_1 & ~m_tmp);
			break;

		case 0x45A4:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_41.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_41.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_41.field.b_f1_2 = (d_tmp & m_tmp) | (reg_ipf2_f_41.field.b_f1_2 & ~m_tmp);
			break;

		case 0x45A8:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_42.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_42.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_42.field.b_f1_3 = (d_tmp & m_tmp) | (reg_ipf2_f_42.field.b_f1_3 & ~m_tmp);
			break;

		case 0x45AC:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_43.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_43.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_43.field.b_f1_4 = (d_tmp & m_tmp) | (reg_ipf2_f_43.field.b_f1_4 & ~m_tmp);
			break;

		case 0x45B0:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_44.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_44.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_44.field.b_f1_5 = (d_tmp & m_tmp) | (reg_ipf2_f_44.field.b_f1_5 & ~m_tmp);
			break;

		case 0x45B4:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_45.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_45.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_45.field.b_f1_6 = (d_tmp & m_tmp) | (reg_ipf2_f_45.field.b_f1_6 & ~m_tmp);
			break;

		case 0x45B8:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_46.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_46.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_46.field.b_f1_7 = (d_tmp & m_tmp) | (reg_ipf2_f_46.field.b_f1_7 & ~m_tmp);
			break;

		case 0x45BC:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_47.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_47.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_47.field.b_f1_8 = (d_tmp & m_tmp) | (reg_ipf2_f_47.field.b_f1_8 & ~m_tmp);
			break;

		case 0x45C0:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_48.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_48.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_48.field.b_f1_9 = (d_tmp & m_tmp) | (reg_ipf2_f_48.field.b_f1_9 & ~m_tmp);
			break;

		case 0x45C4:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_49.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_49.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_49.field.b_f1_10 = (d_tmp & m_tmp) | (reg_ipf2_f_49.field.b_f1_10 & ~m_tmp);
			break;

		case 0x45C8:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_50.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_50.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_50.field.b_f1_11 = (d_tmp & m_tmp) | (reg_ipf2_f_50.field.b_f1_11 & ~m_tmp);
			break;

		case 0x45CC:
			// Lsb: 0, Len: 16, [15:0] 
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_ipf2_f_51.field.rsvd0 = (d_tmp & m_tmp) | (reg_ipf2_f_51.field.rsvd0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] PF correction Blue filter value.
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_ipf2_f_51.field.b_f1_12 = (d_tmp & m_tmp) | (reg_ipf2_f_51.field.b_f1_12 & ~m_tmp);
			break;

		case 0x45D0:
			// Lsb: 0, Len: 2, [1:0] PF correction Red Green mode
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_ipf3_rg_md.field.rg_md = (d_tmp & m_tmp) | (reg_ipf3_rg_md.field.rg_md & ~m_tmp);

			// Lsb: 2, Len: 30, [31:2] 
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x3FFFFFFF;
			reg_ipf3_rg_md.field.rsvd2 = (d_tmp & m_tmp) | (reg_ipf3_rg_md.field.rsvd2 & ~m_tmp);
			break;

		case 0x4600:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_0.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_0.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4604:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_1.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_1.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4608:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_2.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_2.field.coeff_rgx & ~m_tmp);
			break;

		case 0x460C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_3.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_3.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4610:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_4.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_4.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4614:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_5.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_5.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4618:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_6.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_6.field.coeff_rgx & ~m_tmp);
			break;

		case 0x461C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_7.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_7.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4620:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_8.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_8.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4624:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_9.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_9.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4628:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_10.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_10.field.coeff_rgx & ~m_tmp);
			break;

		case 0x462C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_11.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_11.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4630:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_12.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_12.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4634:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_13.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_13.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4638:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_14.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_14.field.coeff_rgx & ~m_tmp);
			break;

		case 0x463C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_15.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_15.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4640:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_16.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_16.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4644:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_17.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_17.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4648:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_18.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_18.field.coeff_rgx & ~m_tmp);
			break;

		case 0x464C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_19.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_19.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4650:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_20.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_20.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4654:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_21.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_21.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4658:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_22.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_22.field.coeff_rgx & ~m_tmp);
			break;

		case 0x465C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_23.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_23.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4660:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_24.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_24.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4664:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica0_crgx_25.field.coeff_rgx = (d_tmp & m_tmp) | (reg_ica0_crgx_25.field.coeff_rgx & ~m_tmp);
			break;

		case 0x4668:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_0.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_0.field.coeff_rgy & ~m_tmp);
			break;

		case 0x466C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_1.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_1.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4670:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_2.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_2.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4674:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_3.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_3.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4678:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_4.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_4.field.coeff_rgy & ~m_tmp);
			break;

		case 0x467C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_5.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_5.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4680:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_6.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_6.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4684:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_7.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_7.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4688:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_8.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_8.field.coeff_rgy & ~m_tmp);
			break;

		case 0x468C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_9.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_9.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4690:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_10.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_10.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4694:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_11.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_11.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4698:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_12.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_12.field.coeff_rgy & ~m_tmp);
			break;

		case 0x469C:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_13.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_13.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46A0:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_14.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_14.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46A4:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_15.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_15.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46A8:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_16.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_16.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46AC:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_17.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_17.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46B0:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_18.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_18.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46B4:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_19.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_19.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46B8:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_20.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_20.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46BC:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_21.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_21.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46C0:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_22.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_22.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46C4:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_23.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_23.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46C8:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_24.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_24.field.coeff_rgy & ~m_tmp);
			break;

		case 0x46CC:
			// Lsb: 0, Len: 32, [31:0] COEFF_RGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica1_crgy_25.field.coeff_rgy = (d_tmp & m_tmp) | (reg_ica1_crgy_25.field.coeff_rgy & ~m_tmp);
			break;

		case 0x4700:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_0.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_0.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4704:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_1.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_1.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4708:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_2.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_2.field.coeff_bgx & ~m_tmp);
			break;

		case 0x470C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_3.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_3.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4710:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_4.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_4.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4714:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_5.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_5.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4718:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_6.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_6.field.coeff_bgx & ~m_tmp);
			break;

		case 0x471C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_7.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_7.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4720:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_8.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_8.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4724:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_9.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_9.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4728:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_10.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_10.field.coeff_bgx & ~m_tmp);
			break;

		case 0x472C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_11.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_11.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4730:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_12.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_12.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4734:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_13.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_13.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4738:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_14.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_14.field.coeff_bgx & ~m_tmp);
			break;

		case 0x473C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_15.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_15.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4740:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_16.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_16.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4744:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_17.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_17.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4748:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_18.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_18.field.coeff_bgx & ~m_tmp);
			break;

		case 0x474C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_19.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_19.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4750:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_20.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_20.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4754:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_21.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_21.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4758:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_22.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_22.field.coeff_bgx & ~m_tmp);
			break;

		case 0x475C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_23.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_23.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4760:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_24.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_24.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4764:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGX[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica2_cbgx_25.field.coeff_bgx = (d_tmp & m_tmp) | (reg_ica2_cbgx_25.field.coeff_bgx & ~m_tmp);
			break;

		case 0x4768:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_0.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_0.field.coeff_bgy & ~m_tmp);
			break;

		case 0x476C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_1.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_1.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4770:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_2.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_2.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4774:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_3.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_3.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4778:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_4.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_4.field.coeff_bgy & ~m_tmp);
			break;

		case 0x477C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_5.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_5.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4780:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_6.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_6.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4784:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_7.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_7.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4788:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_8.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_8.field.coeff_bgy & ~m_tmp);
			break;

		case 0x478C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_9.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_9.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4790:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_10.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_10.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4794:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_11.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_11.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4798:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_12.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_12.field.coeff_bgy & ~m_tmp);
			break;

		case 0x479C:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_13.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_13.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47A0:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_14.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_14.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47A4:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_15.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_15.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47A8:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_16.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_16.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47AC:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_17.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_17.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47B0:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_18.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_18.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47B4:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_19.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_19.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47B8:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_20.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_20.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47BC:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_21.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_21.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47C0:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_22.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_22.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47C4:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_23.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_23.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47C8:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[31:0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_24.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_24.field.coeff_bgy & ~m_tmp);
			break;

		case 0x47CC:
			// Lsb: 0, Len: 32, [31:0] COEFF_BGY[63:32]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_ica3_cbgy_25.field.coeff_bgy = (d_tmp & m_tmp) | (reg_ica3_cbgy_25.field.coeff_bgy & ~m_tmp);
			break;

		case 0x4868:
			// Lsb: 0, Len: 10, [9:0] x coordinates for luminance [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_xl_cfg0.field.xl0 = (d_tmp & m_tmp) | (reg_icamd_xl_cfg0.field.xl0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_xl_cfg0.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_xl_cfg0.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for luminance [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_xl_cfg0.field.xl1 = (d_tmp & m_tmp) | (reg_icamd_xl_cfg0.field.xl1 & ~m_tmp);
			break;

		case 0x486C:
			// Lsb: 0, Len: 10, [9:0] x coordinates for luminance [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_xl_cfg1.field.xl2 = (d_tmp & m_tmp) | (reg_icamd_xl_cfg1.field.xl2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_xl_cfg1.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_xl_cfg1.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for luminance [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_xl_cfg1.field.xl3 = (d_tmp & m_tmp) | (reg_icamd_xl_cfg1.field.xl3 & ~m_tmp);
			break;

		case 0x4870:
			// Lsb: 0, Len: 10, [9:0] x coordinates for luminance [0.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_fl_cfg0.field.fl0 = (d_tmp & m_tmp) | (reg_icamd_fl_cfg0.field.fl0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_fl_cfg0.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_fl_cfg0.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for luminance [0.3.7]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_fl_cfg0.field.fl1 = (d_tmp & m_tmp) | (reg_icamd_fl_cfg0.field.fl1 & ~m_tmp);
			break;

		case 0x4874:
			// Lsb: 0, Len: 10, [9:0] x coordinates for luminance [0.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_fl_cfg1.field.fl2 = (d_tmp & m_tmp) | (reg_icamd_fl_cfg1.field.fl2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_fl_cfg1.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_fl_cfg1.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for luminance [0.3.7]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_fl_cfg1.field.fl3 = (d_tmp & m_tmp) | (reg_icamd_fl_cfg1.field.fl3 & ~m_tmp);
			break;

		case 0x4878:
			// Lsb: 0, Len: 16, [15:0] x coordinates for luminance [1.3.12]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_icamd_sl_cfg0.field.sl0 = (d_tmp & m_tmp) | (reg_icamd_sl_cfg0.field.sl0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] x coordinates for luminance [1.3.12]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_icamd_sl_cfg0.field.sl1 = (d_tmp & m_tmp) | (reg_icamd_sl_cfg0.field.sl1 & ~m_tmp);
			break;

		case 0x487C:
			// Lsb: 0, Len: 16, [15:0] x coordinates for luminance [1.3.12]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_icamd_sl_cfg1.field.sl2 = (d_tmp & m_tmp) | (reg_icamd_sl_cfg1.field.sl2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] x coordinates for luminance [1.3.12]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_icamd_sl_cfg1.field.sl3 = (d_tmp & m_tmp) | (reg_icamd_sl_cfg1.field.sl3 & ~m_tmp);
			break;

		case 0x4880:
			// Lsb: 0, Len: 10, [9:0] x coordinates for color saturation [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_xs_cfg0.field.xl0 = (d_tmp & m_tmp) | (reg_icamd_xs_cfg0.field.xl0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_xs_cfg0.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_xs_cfg0.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for color saturation [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_xs_cfg0.field.xl1 = (d_tmp & m_tmp) | (reg_icamd_xs_cfg0.field.xl1 & ~m_tmp);
			break;

		case 0x4884:
			// Lsb: 0, Len: 10, [9:0] x coordinates for color saturation [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_xs_cfg1.field.xl2 = (d_tmp & m_tmp) | (reg_icamd_xs_cfg1.field.xl2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_xs_cfg1.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_xs_cfg1.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for color saturation [0.10.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_xs_cfg1.field.xl3 = (d_tmp & m_tmp) | (reg_icamd_xs_cfg1.field.xl3 & ~m_tmp);
			break;

		case 0x4888:
			// Lsb: 0, Len: 10, [9:0] x coordinates for color saturation [0.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_fs_cfg0.field.fl0 = (d_tmp & m_tmp) | (reg_icamd_fs_cfg0.field.fl0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_fs_cfg0.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_fs_cfg0.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for color saturation [0.3.7]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_fs_cfg0.field.fl1 = (d_tmp & m_tmp) | (reg_icamd_fs_cfg0.field.fl1 & ~m_tmp);
			break;

		case 0x488C:
			// Lsb: 0, Len: 10, [9:0] x coordinates for color saturation [0.3.7]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_icamd_fs_cfg1.field.fl2 = (d_tmp & m_tmp) | (reg_icamd_fs_cfg1.field.fl2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_icamd_fs_cfg1.field.rsvd = (d_tmp & m_tmp) | (reg_icamd_fs_cfg1.field.rsvd & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] x coordinates for color saturation [0.3.7]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_icamd_fs_cfg1.field.fl3 = (d_tmp & m_tmp) | (reg_icamd_fs_cfg1.field.fl3 & ~m_tmp);
			break;

		case 0x4890:
			// Lsb: 0, Len: 16, [15:0] x coordinates for color saturation [1.3.12]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_icamd_ss_cfg0.field.sl0 = (d_tmp & m_tmp) | (reg_icamd_ss_cfg0.field.sl0 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] x coordinates for color saturation [1.3.12]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_icamd_ss_cfg0.field.sl1 = (d_tmp & m_tmp) | (reg_icamd_ss_cfg0.field.sl1 & ~m_tmp);
			break;

		case 0x4894:
			// Lsb: 0, Len: 16, [15:0] x coordinates for color saturation [1.3.12]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000FFFF;
			reg_icamd_ss_cfg1.field.sl2 = (d_tmp & m_tmp) | (reg_icamd_ss_cfg1.field.sl2 & ~m_tmp);

			// Lsb: 16, Len: 16, [31:16] x coordinates for color saturation [1.3.12]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000FFFF;
			reg_icamd_ss_cfg1.field.sl3 = (d_tmp & m_tmp) | (reg_icamd_ss_cfg1.field.sl3 & ~m_tmp);
			break;

		case 0x4A6C:
			// Lsb: 0, Len: 22, [21:0] Amplification filter weight normalization factor 2nd set
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x003FFFFF;
			reg_ishrpws2.field.wsum2 = (d_tmp & m_tmp) | (reg_ishrpws2.field.wsum2 & ~m_tmp);
			break;

		case 0x4A70:
			// Lsb: 0, Len: 10, [9:0] uv threshold [0.10.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_ishrpuvsmt.field.uv_sm_t = (d_tmp & m_tmp) | (reg_ishrpuvsmt.field.uv_sm_t & ~m_tmp);
			break;

		case 0x4A74:
			// Lsb: 0, Len: 2, [1:0] shrp axi write burst length mode, 0: burst 16, 1: burst 8, 2: burst 4
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_isfrpbuf0.field.wbstm = (d_tmp & m_tmp) | (reg_isfrpbuf0.field.wbstm & ~m_tmp);

			// Lsb: 2, Len: 1, [2] 
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_isfrpbuf0.field.reserved = (d_tmp & m_tmp) | (reg_isfrpbuf0.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] LPF buffer address (8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_isfrpbuf0.field.bufaddr = (d_tmp & m_tmp) | (reg_isfrpbuf0.field.bufaddr & ~m_tmp);
			break;

		case 0x4A78:
			// Lsb: 0, Len: 2, [1:0] shrp read axi outstanding mode, 0 : 4*1*8*64, 1: 2*2*8*64, 2: 1*4*8*64
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000003;
			reg_isfrpbuf1.field.rbstm = (d_tmp & m_tmp) | (reg_isfrpbuf1.field.rbstm & ~m_tmp);

			// Lsb: 2, Len: 1, [2] 
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_isfrpbuf1.field.reserved = (d_tmp & m_tmp) | (reg_isfrpbuf1.field.reserved & ~m_tmp);

			// Lsb: 3, Len: 29, [31:3] LPF buffer address (8-byte Alignment)
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x1FFFFFFF;
			reg_isfrpbuf1.field.bufaddr = (d_tmp & m_tmp) | (reg_isfrpbuf1.field.bufaddr & ~m_tmp);
			break;

		case 0x4A7C:
			// Lsb: 0, Len: 1, [0] LPF write buffer status
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_isfrpbufst.field.bufst = (d_tmp & m_tmp) | (reg_isfrpbufst.field.bufst & ~m_tmp);
			break;

		case 0x4B00:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_obc_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_obc_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B04:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_nl3d_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_nl3d_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B08:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_nl2d_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_nl2d_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B0C:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_grgb_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_grgb_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B10:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_awb_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_awb_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B14:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ccm_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_ccm_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B18:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_lut_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_lut_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B1C:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_gamrgb_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_gamrgb_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B20:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_r2y_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_r2y_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B24:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ycur_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_ycur_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B28:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_nwed_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_nwed_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B2C:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_shrp_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_shrp_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B30:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_sat_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_sat_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B34:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_sc0_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_sc0_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B38:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_sc1_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_sc1_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B3C:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_yhist_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_yhist_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B40:
			// Lsb: 0, Len: 1, [0] tiling read  enable  shadow, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_iti_sud.field.iti_read_shadow_md = (d_tmp & m_tmp) | (reg_iti_sud.field.iti_read_shadow_md & ~m_tmp);

			// Lsb: 1, Len: 1, [1] tiling write0  enable  shadow, active high.
			d_tmp = (data >> 1); m_tmp = (mask >> 1) & 0x00000001;
			reg_iti_sud.field.iti_write0_shadow_md = (d_tmp & m_tmp) | (reg_iti_sud.field.iti_write0_shadow_md & ~m_tmp);

			// Lsb: 2, Len: 1, [2] tiling write1  enable shadow, active high.
			d_tmp = (data >> 2); m_tmp = (mask >> 2) & 0x00000001;
			reg_iti_sud.field.iti_write1_shadow_md = (d_tmp & m_tmp) | (reg_iti_sud.field.iti_write1_shadow_md & ~m_tmp);

			// Lsb: 3, Len: 1, [3] tiling write0 crop register update enable, active high.
			d_tmp = (data >> 3); m_tmp = (mask >> 3) & 0x00000001;
			reg_iti_sud.field.iti_write0_crop_ud = (d_tmp & m_tmp) | (reg_iti_sud.field.iti_write0_crop_ud & ~m_tmp);

			// Lsb: 4, Len: 1, [4] tiling write1 crop register update enable, active high.
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_iti_sud.field.iti_write1_crop_ud = (d_tmp & m_tmp) | (reg_iti_sud.field.iti_write1_crop_ud & ~m_tmp);
			break;

		case 0x4B44:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_wdr_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_wdr_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B48:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_biyuv_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_biyuv_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B4C:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_ctm_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_ctm_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4B50:
			// Lsb: 0, Len: 1, [0] shadow register update enable, active high.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_oecf_sud.field.shadow_ud = (d_tmp & m_tmp) | (reg_oecf_sud.field.shadow_ud & ~m_tmp);
			break;

		case 0x4C00:
			// Lsb: 0, Len: 1, [0] rdma enable, active high, internal check rise edge for rdma_en for rdma start
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_rdma_enr.field.rdma_en = (d_tmp & m_tmp) | (reg_rdma_enr.field.rdma_en & ~m_tmp);
			break;

		case 0x4C04:
			// Lsb: 0, Len: 1, [0] when RDMA descriptor include DESP_SINT with flag[1] set to high, need write this register, then rdma will execute next line descriptor.
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00000001;
			reg_rdma_sackr.field.sack = (d_tmp & m_tmp) | (reg_rdma_sackr.field.sack & ~m_tmp);
			break;

		case 0x4C08:
			// Lsb: 0, Len: 32, [31:0] RDMA Descriptor Start Addresse register(8 byte align, low 3bit always set to 0)
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_rdma_daddr.field.desp_baddr = (d_tmp & m_tmp) | (reg_rdma_daddr.field.desp_baddr & ~m_tmp);
			break;

		case 0x4C0C:
			// Lsb: 0, Len: 32, [31:0] RDMA Descriptor current address
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0xFFFFFFFF;
			reg_rdma_caddr.field.desp_caddr = (d_tmp & m_tmp) | (reg_rdma_caddr.field.desp_caddr & ~m_tmp);
			break;

		case 0x4C10:
			// Lsb: 0, Len: 4, [3:0] internal fsm state
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_rdma_stsr.field.desp_fsm = (d_tmp & m_tmp) | (reg_rdma_stsr.field.desp_fsm & ~m_tmp);

			// Lsb: 4, Len: 1, [4] rdma finish flag(read only)
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x00000001;
			reg_rdma_stsr.field.desp_eint = (d_tmp & m_tmp) | (reg_rdma_stsr.field.desp_eint & ~m_tmp);

			// Lsb: 5, Len: 1, [5] rdma software interrupt flag(read only)
			d_tmp = (data >> 5); m_tmp = (mask >> 5) & 0x00000001;
			reg_rdma_stsr.field.desp_sint = (d_tmp & m_tmp) | (reg_rdma_stsr.field.desp_sint & ~m_tmp);
			break;

		case 0x4D00:
			// Lsb: 0, Len: 4, [3:0] [0.4.0], y channel Sa
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_biyuv_yswr0.field.yswa = (d_tmp & m_tmp) | (reg_biyuv_yswr0.field.yswa & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0], y channel Sb
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_biyuv_yswr0.field.yswb = (d_tmp & m_tmp) | (reg_biyuv_yswr0.field.yswb & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0], y channel Sc
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_biyuv_yswr0.field.yswc = (d_tmp & m_tmp) | (reg_biyuv_yswr0.field.yswc & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0], y channel Sd
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_biyuv_yswr0.field.yswd = (d_tmp & m_tmp) | (reg_biyuv_yswr0.field.yswd & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0], y channel Se
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_biyuv_yswr0.field.yswe = (d_tmp & m_tmp) | (reg_biyuv_yswr0.field.yswe & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0], y channel Sf
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_biyuv_yswr0.field.yswf = (d_tmp & m_tmp) | (reg_biyuv_yswr0.field.yswf & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] 
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_biyuv_yswr0.field.rsvd24 = (d_tmp & m_tmp) | (reg_biyuv_yswr0.field.rsvd24 & ~m_tmp);
			break;

		case 0x4D04:
			// Lsb: 0, Len: 4, [3:0] [0.4.0], y channel Sg
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_biyuv_yswr1.field.yswg = (d_tmp & m_tmp) | (reg_biyuv_yswr1.field.yswg & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0], y channel Sh
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_biyuv_yswr1.field.yswh = (d_tmp & m_tmp) | (reg_biyuv_yswr1.field.yswh & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0], y channel Si
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_biyuv_yswr1.field.yswi = (d_tmp & m_tmp) | (reg_biyuv_yswr1.field.yswi & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0], y channel Sj
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_biyuv_yswr1.field.yswj = (d_tmp & m_tmp) | (reg_biyuv_yswr1.field.yswj & ~m_tmp);
			break;

		case 0x4D08:
			// Lsb: 0, Len: 4, [3:0] [0.4.0], uv channel Sa
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_biyuv_uvswr0.field.uvswa = (d_tmp & m_tmp) | (reg_biyuv_uvswr0.field.uvswa & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0], uv channel Sb
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_biyuv_uvswr0.field.uvswb = (d_tmp & m_tmp) | (reg_biyuv_uvswr0.field.uvswb & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0], uv channel Sc
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_biyuv_uvswr0.field.uvswc = (d_tmp & m_tmp) | (reg_biyuv_uvswr0.field.uvswc & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0], uv channel Sd
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_biyuv_uvswr0.field.uvswd = (d_tmp & m_tmp) | (reg_biyuv_uvswr0.field.uvswd & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0], uv channel Se
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_biyuv_uvswr0.field.uvswe = (d_tmp & m_tmp) | (reg_biyuv_uvswr0.field.uvswe & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0], uv channel Sf
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_biyuv_uvswr0.field.uvswf = (d_tmp & m_tmp) | (reg_biyuv_uvswr0.field.uvswf & ~m_tmp);

			// Lsb: 24, Len: 8, [31:24] 
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x000000FF;
			reg_biyuv_uvswr0.field.rsvd24 = (d_tmp & m_tmp) | (reg_biyuv_uvswr0.field.rsvd24 & ~m_tmp);
			break;

		case 0x4D0C:
			// Lsb: 0, Len: 4, [3:0] [0.4.0], uv channel Sg
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_biyuv_uvswr1.field.uvswg = (d_tmp & m_tmp) | (reg_biyuv_uvswr1.field.uvswg & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0], uv channel Sh
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_biyuv_uvswr1.field.uvswh = (d_tmp & m_tmp) | (reg_biyuv_uvswr1.field.uvswh & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0], uv channel Si
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_biyuv_uvswr1.field.uvswi = (d_tmp & m_tmp) | (reg_biyuv_uvswr1.field.uvswi & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0], uv channel Sj
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_biyuv_uvswr1.field.uvswj = (d_tmp & m_tmp) | (reg_biyuv_uvswr1.field.uvswj & ~m_tmp);
			break;

		case 0x4D10:
			// Lsb: 0, Len: 4, [3:0] [0.4.0], Curve I components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_biyuv_ycir.field.yci0 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0], Curve I components for Y
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_biyuv_ycir.field.yci1 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0], Curve I components for Y
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_biyuv_ycir.field.yci2 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0], Curve I components for Y
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_biyuv_ycir.field.yci3 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0], Curve I components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_biyuv_ycir.field.yci4 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0], Curve I components for Y
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_biyuv_ycir.field.yci5 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0], Curve I components forY
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_biyuv_ycir.field.yci6 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0], Curve I components for Y
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_biyuv_ycir.field.yci7 = (d_tmp & m_tmp) | (reg_biyuv_ycir.field.yci7 & ~m_tmp);
			break;

		case 0x4D14:
			// Lsb: 0, Len: 4, [3:0] [0.4.0], Curve I components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci0 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci0 & ~m_tmp);

			// Lsb: 4, Len: 4, [7:4] [0.4.0], Curve I components for UV
			d_tmp = (data >> 4); m_tmp = (mask >> 4) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci1 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci1 & ~m_tmp);

			// Lsb: 8, Len: 4, [11:8] [0.4.0], Curve I components for UV
			d_tmp = (data >> 8); m_tmp = (mask >> 8) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci2 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci2 & ~m_tmp);

			// Lsb: 12, Len: 4, [15:12] [0.4.0], Curve I components for UV
			d_tmp = (data >> 12); m_tmp = (mask >> 12) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci3 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci3 & ~m_tmp);

			// Lsb: 16, Len: 4, [19:16] [0.4.0], Curve I components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci4 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci4 & ~m_tmp);

			// Lsb: 20, Len: 4, [23:20] [0.4.0], Curve I components for UV
			d_tmp = (data >> 20); m_tmp = (mask >> 20) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci5 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci5 & ~m_tmp);

			// Lsb: 24, Len: 4, [27:24] [0.4.0], Curve I components for UV
			d_tmp = (data >> 24); m_tmp = (mask >> 24) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci6 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci6 & ~m_tmp);

			// Lsb: 28, Len: 4, [31:28] [0.4.0], Curve I components for UV
			d_tmp = (data >> 28); m_tmp = (mask >> 28) & 0x0000000F;
			reg_biyuv_uvcir.field.uvci7 = (d_tmp & m_tmp) | (reg_biyuv_uvcir.field.uvci7 & ~m_tmp);
			break;

		case 0x4D18:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_ycdr0.field.ycd0 = (d_tmp & m_tmp) | (reg_biyuv_ycdr0.field.ycd0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_ycdr0.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_ycdr0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_ycdr0.field.ycd1 = (d_tmp & m_tmp) | (reg_biyuv_ycdr0.field.ycd1 & ~m_tmp);
			break;

		case 0x4D1C:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_ycdr1.field.ycd2 = (d_tmp & m_tmp) | (reg_biyuv_ycdr1.field.ycd2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_ycdr1.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_ycdr1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_ycdr1.field.ycd3 = (d_tmp & m_tmp) | (reg_biyuv_ycdr1.field.ycd3 & ~m_tmp);
			break;

		case 0x4D20:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_ycdr2.field.ycd4 = (d_tmp & m_tmp) | (reg_biyuv_ycdr2.field.ycd4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_ycdr2.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_ycdr2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_ycdr2.field.ycd5 = (d_tmp & m_tmp) | (reg_biyuv_ycdr2.field.ycd5 & ~m_tmp);
			break;

		case 0x4D24:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_ycdr3.field.ycd6 = (d_tmp & m_tmp) | (reg_biyuv_ycdr3.field.ycd6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_ycdr3.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_ycdr3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_ycdr3.field.ycd7 = (d_tmp & m_tmp) | (reg_biyuv_ycdr3.field.ycd7 & ~m_tmp);
			break;

		case 0x4D28:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_uvcdr0.field.uvcd0 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr0.field.uvcd0 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_uvcdr0.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr0.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_uvcdr0.field.uvcd1 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr0.field.uvcd1 & ~m_tmp);
			break;

		case 0x4D2C:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_uvcdr1.field.uvcd2 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr1.field.uvcd2 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_uvcdr1.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr1.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_uvcdr1.field.uvcd3 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr1.field.uvcd3 & ~m_tmp);
			break;

		case 0x4D30:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_uvcdr2.field.uvcd4 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr2.field.uvcd4 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_uvcdr2.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr2.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_uvcdr2.field.uvcd5 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr2.field.uvcd5 & ~m_tmp);
			break;

		case 0x4D34:
			// Lsb: 0, Len: 10, [9:0] [0.10.0], Curve D components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000003FF;
			reg_biyuv_uvcdr3.field.uvcd6 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr3.field.uvcd6 & ~m_tmp);

			// Lsb: 10, Len: 6, [15:10] 
			d_tmp = (data >> 10); m_tmp = (mask >> 10) & 0x0000003F;
			reg_biyuv_uvcdr3.field.rsvd10 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr3.field.rsvd10 & ~m_tmp);

			// Lsb: 16, Len: 10, [25:16] [0.10.0], Curve D components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000003FF;
			reg_biyuv_uvcdr3.field.uvcd7 = (d_tmp & m_tmp) | (reg_biyuv_uvcdr3.field.uvcd7 & ~m_tmp);
			break;

		case 0x4D38:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_ycsr0.field.ycs0 = (d_tmp & m_tmp) | (reg_biyuv_ycsr0.field.ycs0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_ycsr0.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_ycsr0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_ycsr0.field.ycs1 = (d_tmp & m_tmp) | (reg_biyuv_ycsr0.field.ycs1 & ~m_tmp);
			break;

		case 0x4D3C:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_ycsr1.field.ycs2 = (d_tmp & m_tmp) | (reg_biyuv_ycsr1.field.ycs2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_ycsr1.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_ycsr1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_ycsr1.field.ycs3 = (d_tmp & m_tmp) | (reg_biyuv_ycsr1.field.ycs3 & ~m_tmp);
			break;

		case 0x4D40:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_ycsr2.field.ycs4 = (d_tmp & m_tmp) | (reg_biyuv_ycsr2.field.ycs4 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_ycsr2.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_ycsr2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_ycsr2.field.ycs5 = (d_tmp & m_tmp) | (reg_biyuv_ycsr2.field.ycs5 & ~m_tmp);
			break;

		case 0x4D44:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for Y
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_ycsr3.field.ycs6 = (d_tmp & m_tmp) | (reg_biyuv_ycsr3.field.ycs6 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_ycsr3.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_ycsr3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for Y
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_ycsr3.field.ycs7 = (d_tmp & m_tmp) | (reg_biyuv_ycsr3.field.ycs7 & ~m_tmp);
			break;

		case 0x4D48:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_uvcsr0.field.uvcs0 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr0.field.uvcs0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_uvcsr0.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_uvcsr0.field.uvcs1 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr0.field.uvcs1 & ~m_tmp);
			break;

		case 0x4D4C:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_uvcsr1.field.uvcs2 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr1.field.uvcs2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_uvcsr1.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_uvcsr1.field.uvcs3 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr1.field.uvcs3 & ~m_tmp);
			break;

		case 0x4D50:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_uvcsr2.field.uvcs4 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr2.field.uvcs4 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_uvcsr2.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_uvcsr2.field.uvcs5 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr2.field.uvcs5 & ~m_tmp);
			break;

		case 0x4D54:
			// Lsb: 0, Len: 13, [12:0] [1.4.8], Curve S components for UV
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_biyuv_uvcsr3.field.uvcs6 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr3.field.uvcs6 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_biyuv_uvcsr3.field.rsvd13 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] [1.4.8], Curve S components for UV
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_biyuv_uvcsr3.field.uvcs7 = (d_tmp & m_tmp) | (reg_biyuv_uvcsr3.field.uvcs7 & ~m_tmp);
			break;

		case 0x4E00:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr0.field.h0 = (d_tmp & m_tmp) | (reg_ctm_hr0.field.h0 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr0.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr0.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr0.field.h1 = (d_tmp & m_tmp) | (reg_ctm_hr0.field.h1 & ~m_tmp);
			break;

		case 0x4E04:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr1.field.h2 = (d_tmp & m_tmp) | (reg_ctm_hr1.field.h2 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr1.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr1.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr1.field.h3 = (d_tmp & m_tmp) | (reg_ctm_hr1.field.h3 & ~m_tmp);
			break;

		case 0x4E08:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr2.field.h4 = (d_tmp & m_tmp) | (reg_ctm_hr2.field.h4 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr2.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr2.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr2.field.h5 = (d_tmp & m_tmp) | (reg_ctm_hr2.field.h5 & ~m_tmp);
			break;

		case 0x4E0C:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr3.field.h6 = (d_tmp & m_tmp) | (reg_ctm_hr3.field.h6 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr3.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr3.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr3.field.h7 = (d_tmp & m_tmp) | (reg_ctm_hr3.field.h7 & ~m_tmp);
			break;

		case 0x4E10:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr4.field.h8 = (d_tmp & m_tmp) | (reg_ctm_hr4.field.h8 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr4.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr4.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr4.field.h9 = (d_tmp & m_tmp) | (reg_ctm_hr4.field.h9 & ~m_tmp);
			break;

		case 0x4E14:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr5.field.h10 = (d_tmp & m_tmp) | (reg_ctm_hr5.field.h10 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr5.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr5.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr5.field.h11 = (d_tmp & m_tmp) | (reg_ctm_hr5.field.h11 & ~m_tmp);
			break;

		case 0x4E18:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr6.field.h12 = (d_tmp & m_tmp) | (reg_ctm_hr6.field.h12 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr6.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr6.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr6.field.h13 = (d_tmp & m_tmp) | (reg_ctm_hr6.field.h13 & ~m_tmp);
			break;

		case 0x4E1C:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr7.field.h14 = (d_tmp & m_tmp) | (reg_ctm_hr7.field.h14 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr7.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr7.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr7.field.h15 = (d_tmp & m_tmp) | (reg_ctm_hr7.field.h15 & ~m_tmp);
			break;

		case 0x4E20:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr8.field.h16 = (d_tmp & m_tmp) | (reg_ctm_hr8.field.h16 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr8.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr8.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr8.field.h17 = (d_tmp & m_tmp) | (reg_ctm_hr8.field.h17 & ~m_tmp);
			break;

		case 0x4E24:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr9.field.h18 = (d_tmp & m_tmp) | (reg_ctm_hr9.field.h18 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr9.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr9.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr9.field.h19 = (d_tmp & m_tmp) | (reg_ctm_hr9.field.h19 & ~m_tmp);
			break;

		case 0x4E28:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr10.field.h20 = (d_tmp & m_tmp) | (reg_ctm_hr10.field.h20 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr10.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr10.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr10.field.h21 = (d_tmp & m_tmp) | (reg_ctm_hr10.field.h21 & ~m_tmp);
			break;

		case 0x4E2C:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr11.field.h22 = (d_tmp & m_tmp) | (reg_ctm_hr11.field.h22 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr11.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr11.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr11.field.h23 = (d_tmp & m_tmp) | (reg_ctm_hr11.field.h23 & ~m_tmp);
			break;

		case 0x4E30:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr12.field.h24 = (d_tmp & m_tmp) | (reg_ctm_hr12.field.h24 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr12.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr12.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr12.field.h25 = (d_tmp & m_tmp) | (reg_ctm_hr12.field.h25 & ~m_tmp);
			break;

		case 0x4E34:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr13.field.h26 = (d_tmp & m_tmp) | (reg_ctm_hr13.field.h26 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr13.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr13.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr13.field.h27 = (d_tmp & m_tmp) | (reg_ctm_hr13.field.h27 & ~m_tmp);
			break;

		case 0x4E38:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr14.field.h28 = (d_tmp & m_tmp) | (reg_ctm_hr14.field.h28 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr14.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr14.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr14.field.h29 = (d_tmp & m_tmp) | (reg_ctm_hr14.field.h29 & ~m_tmp);
			break;

		case 0x4E3C:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr15.field.h30 = (d_tmp & m_tmp) | (reg_ctm_hr15.field.h30 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr15.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr15.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr15.field.h31 = (d_tmp & m_tmp) | (reg_ctm_hr15.field.h31 & ~m_tmp);
			break;

		case 0x4E40:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr16.field.h32 = (d_tmp & m_tmp) | (reg_ctm_hr16.field.h32 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr16.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr16.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr16.field.h33 = (d_tmp & m_tmp) | (reg_ctm_hr16.field.h33 & ~m_tmp);
			break;

		case 0x4E44:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr17.field.h34 = (d_tmp & m_tmp) | (reg_ctm_hr17.field.h34 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr17.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr17.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr17.field.h35 = (d_tmp & m_tmp) | (reg_ctm_hr17.field.h35 & ~m_tmp);
			break;

		case 0x4E48:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr18.field.h36 = (d_tmp & m_tmp) | (reg_ctm_hr18.field.h36 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr18.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr18.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr18.field.h37 = (d_tmp & m_tmp) | (reg_ctm_hr18.field.h37 & ~m_tmp);
			break;

		case 0x4E4C:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr19.field.h38 = (d_tmp & m_tmp) | (reg_ctm_hr19.field.h38 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr19.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr19.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr19.field.h39 = (d_tmp & m_tmp) | (reg_ctm_hr19.field.h39 & ~m_tmp);
			break;

		case 0x4E50:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr20.field.h40 = (d_tmp & m_tmp) | (reg_ctm_hr20.field.h40 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr20.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr20.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr20.field.h41 = (d_tmp & m_tmp) | (reg_ctm_hr20.field.h41 & ~m_tmp);
			break;

		case 0x4E54:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr21.field.h42 = (d_tmp & m_tmp) | (reg_ctm_hr21.field.h42 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr21.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr21.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr21.field.h43 = (d_tmp & m_tmp) | (reg_ctm_hr21.field.h43 & ~m_tmp);
			break;

		case 0x4E58:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr22.field.h44 = (d_tmp & m_tmp) | (reg_ctm_hr22.field.h44 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr22.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr22.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr22.field.h45 = (d_tmp & m_tmp) | (reg_ctm_hr22.field.h45 & ~m_tmp);
			break;

		case 0x4E5C:
			// Lsb: 0, Len: 13, [12:0] CTM H register [0.13.0]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x00001FFF;
			reg_ctm_hr23.field.h46 = (d_tmp & m_tmp) | (reg_ctm_hr23.field.h46 & ~m_tmp);

			// Lsb: 13, Len: 3, [15:13] 
			d_tmp = (data >> 13); m_tmp = (mask >> 13) & 0x00000007;
			reg_ctm_hr23.field.rsvd13 = (d_tmp & m_tmp) | (reg_ctm_hr23.field.rsvd13 & ~m_tmp);

			// Lsb: 16, Len: 13, [28:16] CTM H register [0.13.0]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x00001FFF;
			reg_ctm_hr23.field.h47 = (d_tmp & m_tmp) | (reg_ctm_hr23.field.h47 & ~m_tmp);
			break;

		case 0x4E60:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr0.field.gs0 = (d_tmp & m_tmp) | (reg_ctm_gsr0.field.gs0 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr0.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr0.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr0.field.gs1 = (d_tmp & m_tmp) | (reg_ctm_gsr0.field.gs1 & ~m_tmp);
			break;

		case 0x4E64:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr1.field.gs2 = (d_tmp & m_tmp) | (reg_ctm_gsr1.field.gs2 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr1.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr1.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr1.field.gs3 = (d_tmp & m_tmp) | (reg_ctm_gsr1.field.gs3 & ~m_tmp);
			break;

		case 0x4E68:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr2.field.gs4 = (d_tmp & m_tmp) | (reg_ctm_gsr2.field.gs4 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr2.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr2.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr2.field.gs5 = (d_tmp & m_tmp) | (reg_ctm_gsr2.field.gs5 & ~m_tmp);
			break;

		case 0x4E6C:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr3.field.gs6 = (d_tmp & m_tmp) | (reg_ctm_gsr3.field.gs6 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr3.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr3.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr3.field.gs7 = (d_tmp & m_tmp) | (reg_ctm_gsr3.field.gs7 & ~m_tmp);
			break;

		case 0x4E70:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr4.field.gs8 = (d_tmp & m_tmp) | (reg_ctm_gsr4.field.gs8 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr4.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr4.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr4.field.gs9 = (d_tmp & m_tmp) | (reg_ctm_gsr4.field.gs9 & ~m_tmp);
			break;

		case 0x4E74:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr5.field.gs10 = (d_tmp & m_tmp) | (reg_ctm_gsr5.field.gs10 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr5.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr5.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr5.field.gs11 = (d_tmp & m_tmp) | (reg_ctm_gsr5.field.gs11 & ~m_tmp);
			break;

		case 0x4E78:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr6.field.gs12 = (d_tmp & m_tmp) | (reg_ctm_gsr6.field.gs12 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr6.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr6.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr6.field.gs13 = (d_tmp & m_tmp) | (reg_ctm_gsr6.field.gs13 & ~m_tmp);
			break;

		case 0x4E7C:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr7.field.gs14 = (d_tmp & m_tmp) | (reg_ctm_gsr7.field.gs14 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr7.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr7.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr7.field.gs15 = (d_tmp & m_tmp) | (reg_ctm_gsr7.field.gs15 & ~m_tmp);
			break;

		case 0x4E80:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr8.field.gs16 = (d_tmp & m_tmp) | (reg_ctm_gsr8.field.gs16 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr8.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr8.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr8.field.gs17 = (d_tmp & m_tmp) | (reg_ctm_gsr8.field.gs17 & ~m_tmp);
			break;

		case 0x4E84:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr9.field.gs18 = (d_tmp & m_tmp) | (reg_ctm_gsr9.field.gs18 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr9.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr9.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr9.field.gs19 = (d_tmp & m_tmp) | (reg_ctm_gsr9.field.gs19 & ~m_tmp);
			break;

		case 0x4E88:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr10.field.gs20 = (d_tmp & m_tmp) | (reg_ctm_gsr10.field.gs20 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr10.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr10.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr10.field.gs21 = (d_tmp & m_tmp) | (reg_ctm_gsr10.field.gs21 & ~m_tmp);
			break;

		case 0x4E8C:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr11.field.gs22 = (d_tmp & m_tmp) | (reg_ctm_gsr11.field.gs22 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr11.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr11.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr11.field.gs23 = (d_tmp & m_tmp) | (reg_ctm_gsr11.field.gs23 & ~m_tmp);
			break;

		case 0x4E90:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr12.field.gs24 = (d_tmp & m_tmp) | (reg_ctm_gsr12.field.gs24 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr12.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr12.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr12.field.gs25 = (d_tmp & m_tmp) | (reg_ctm_gsr12.field.gs25 & ~m_tmp);
			break;

		case 0x4E94:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr13.field.gs26 = (d_tmp & m_tmp) | (reg_ctm_gsr13.field.gs26 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr13.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr13.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr13.field.gs27 = (d_tmp & m_tmp) | (reg_ctm_gsr13.field.gs27 & ~m_tmp);
			break;

		case 0x4E98:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr14.field.gs28 = (d_tmp & m_tmp) | (reg_ctm_gsr14.field.gs28 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr14.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr14.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr14.field.gs29 = (d_tmp & m_tmp) | (reg_ctm_gsr14.field.gs29 & ~m_tmp);
			break;

		case 0x4E9C:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr15.field.gs30 = (d_tmp & m_tmp) | (reg_ctm_gsr15.field.gs30 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr15.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr15.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr15.field.gs31 = (d_tmp & m_tmp) | (reg_ctm_gsr15.field.gs31 & ~m_tmp);
			break;

		case 0x4EA0:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr16.field.gs32 = (d_tmp & m_tmp) | (reg_ctm_gsr16.field.gs32 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr16.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr16.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr16.field.gs33 = (d_tmp & m_tmp) | (reg_ctm_gsr16.field.gs33 & ~m_tmp);
			break;

		case 0x4EA4:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr17.field.gs34 = (d_tmp & m_tmp) | (reg_ctm_gsr17.field.gs34 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr17.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr17.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr17.field.gs35 = (d_tmp & m_tmp) | (reg_ctm_gsr17.field.gs35 & ~m_tmp);
			break;

		case 0x4EA8:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr18.field.gs36 = (d_tmp & m_tmp) | (reg_ctm_gsr18.field.gs36 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr18.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr18.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr18.field.gs37 = (d_tmp & m_tmp) | (reg_ctm_gsr18.field.gs37 & ~m_tmp);
			break;

		case 0x4EAC:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr19.field.gs38 = (d_tmp & m_tmp) | (reg_ctm_gsr19.field.gs38 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr19.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr19.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr19.field.gs39 = (d_tmp & m_tmp) | (reg_ctm_gsr19.field.gs39 & ~m_tmp);
			break;

		case 0x4EB0:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr20.field.gs40 = (d_tmp & m_tmp) | (reg_ctm_gsr20.field.gs40 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr20.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr20.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr20.field.gs41 = (d_tmp & m_tmp) | (reg_ctm_gsr20.field.gs41 & ~m_tmp);
			break;

		case 0x4EB4:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr21.field.gs42 = (d_tmp & m_tmp) | (reg_ctm_gsr21.field.gs42 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr21.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr21.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr21.field.gs43 = (d_tmp & m_tmp) | (reg_ctm_gsr21.field.gs43 & ~m_tmp);
			break;

		case 0x4EB8:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr22.field.gs44 = (d_tmp & m_tmp) | (reg_ctm_gsr22.field.gs44 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr22.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr22.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr22.field.gs45 = (d_tmp & m_tmp) | (reg_ctm_gsr22.field.gs45 & ~m_tmp);
			break;

		case 0x4EBC:
			// Lsb: 0, Len: 11, [10:0] CTM GS register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gsr23.field.gs46 = (d_tmp & m_tmp) | (reg_ctm_gsr23.field.gs46 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gsr23.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gsr23.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GS register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gsr23.field.gs47 = (d_tmp & m_tmp) | (reg_ctm_gsr23.field.gs47 & ~m_tmp);
			break;

		case 0x4EC0:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr0.field.gv0 = (d_tmp & m_tmp) | (reg_ctm_gvr0.field.gv0 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr0.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr0.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr0.field.gv1 = (d_tmp & m_tmp) | (reg_ctm_gvr0.field.gv1 & ~m_tmp);
			break;

		case 0x4EC4:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr1.field.gv2 = (d_tmp & m_tmp) | (reg_ctm_gvr1.field.gv2 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr1.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr1.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr1.field.gv3 = (d_tmp & m_tmp) | (reg_ctm_gvr1.field.gv3 & ~m_tmp);
			break;

		case 0x4EC8:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr2.field.gv4 = (d_tmp & m_tmp) | (reg_ctm_gvr2.field.gv4 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr2.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr2.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr2.field.gv5 = (d_tmp & m_tmp) | (reg_ctm_gvr2.field.gv5 & ~m_tmp);
			break;

		case 0x4ECC:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr3.field.gv6 = (d_tmp & m_tmp) | (reg_ctm_gvr3.field.gv6 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr3.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr3.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr3.field.gv7 = (d_tmp & m_tmp) | (reg_ctm_gvr3.field.gv7 & ~m_tmp);
			break;

		case 0x4ED0:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr4.field.gv8 = (d_tmp & m_tmp) | (reg_ctm_gvr4.field.gv8 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr4.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr4.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr4.field.gv9 = (d_tmp & m_tmp) | (reg_ctm_gvr4.field.gv9 & ~m_tmp);
			break;

		case 0x4ED4:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr5.field.gv10 = (d_tmp & m_tmp) | (reg_ctm_gvr5.field.gv10 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr5.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr5.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr5.field.gv11 = (d_tmp & m_tmp) | (reg_ctm_gvr5.field.gv11 & ~m_tmp);
			break;

		case 0x4ED8:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr6.field.gv12 = (d_tmp & m_tmp) | (reg_ctm_gvr6.field.gv12 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr6.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr6.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr6.field.gv13 = (d_tmp & m_tmp) | (reg_ctm_gvr6.field.gv13 & ~m_tmp);
			break;

		case 0x4EDC:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr7.field.gv14 = (d_tmp & m_tmp) | (reg_ctm_gvr7.field.gv14 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr7.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr7.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr7.field.gv15 = (d_tmp & m_tmp) | (reg_ctm_gvr7.field.gv15 & ~m_tmp);
			break;

		case 0x4EE0:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr8.field.gv16 = (d_tmp & m_tmp) | (reg_ctm_gvr8.field.gv16 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr8.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr8.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr8.field.gv17 = (d_tmp & m_tmp) | (reg_ctm_gvr8.field.gv17 & ~m_tmp);
			break;

		case 0x4EE4:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr9.field.gv18 = (d_tmp & m_tmp) | (reg_ctm_gvr9.field.gv18 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr9.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr9.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr9.field.gv19 = (d_tmp & m_tmp) | (reg_ctm_gvr9.field.gv19 & ~m_tmp);
			break;

		case 0x4EE8:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr10.field.gv20 = (d_tmp & m_tmp) | (reg_ctm_gvr10.field.gv20 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr10.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr10.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr10.field.gv21 = (d_tmp & m_tmp) | (reg_ctm_gvr10.field.gv21 & ~m_tmp);
			break;

		case 0x4EEC:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr11.field.gv22 = (d_tmp & m_tmp) | (reg_ctm_gvr11.field.gv22 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr11.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr11.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr11.field.gv23 = (d_tmp & m_tmp) | (reg_ctm_gvr11.field.gv23 & ~m_tmp);
			break;

		case 0x4EF0:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr12.field.gv24 = (d_tmp & m_tmp) | (reg_ctm_gvr12.field.gv24 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr12.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr12.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr12.field.gv25 = (d_tmp & m_tmp) | (reg_ctm_gvr12.field.gv25 & ~m_tmp);
			break;

		case 0x4EF4:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr13.field.gv26 = (d_tmp & m_tmp) | (reg_ctm_gvr13.field.gv26 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr13.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr13.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr13.field.gv27 = (d_tmp & m_tmp) | (reg_ctm_gvr13.field.gv27 & ~m_tmp);
			break;

		case 0x4EF8:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr14.field.gv28 = (d_tmp & m_tmp) | (reg_ctm_gvr14.field.gv28 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr14.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr14.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr14.field.gv29 = (d_tmp & m_tmp) | (reg_ctm_gvr14.field.gv29 & ~m_tmp);
			break;

		case 0x4EFC:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr15.field.gv30 = (d_tmp & m_tmp) | (reg_ctm_gvr15.field.gv30 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr15.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr15.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr15.field.gv31 = (d_tmp & m_tmp) | (reg_ctm_gvr15.field.gv31 & ~m_tmp);
			break;

		case 0x4F00:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr16.field.gv32 = (d_tmp & m_tmp) | (reg_ctm_gvr16.field.gv32 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr16.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr16.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr16.field.gv33 = (d_tmp & m_tmp) | (reg_ctm_gvr16.field.gv33 & ~m_tmp);
			break;

		case 0x4F04:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr17.field.gv34 = (d_tmp & m_tmp) | (reg_ctm_gvr17.field.gv34 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr17.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr17.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr17.field.gv35 = (d_tmp & m_tmp) | (reg_ctm_gvr17.field.gv35 & ~m_tmp);
			break;

		case 0x4F08:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr18.field.gv36 = (d_tmp & m_tmp) | (reg_ctm_gvr18.field.gv36 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr18.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr18.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr18.field.gv37 = (d_tmp & m_tmp) | (reg_ctm_gvr18.field.gv37 & ~m_tmp);
			break;

		case 0x4F0C:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr19.field.gv38 = (d_tmp & m_tmp) | (reg_ctm_gvr19.field.gv38 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr19.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr19.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr19.field.gv39 = (d_tmp & m_tmp) | (reg_ctm_gvr19.field.gv39 & ~m_tmp);
			break;

		case 0x4F10:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr20.field.gv40 = (d_tmp & m_tmp) | (reg_ctm_gvr20.field.gv40 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr20.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr20.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr20.field.gv41 = (d_tmp & m_tmp) | (reg_ctm_gvr20.field.gv41 & ~m_tmp);
			break;

		case 0x4F14:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr21.field.gv42 = (d_tmp & m_tmp) | (reg_ctm_gvr21.field.gv42 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr21.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr21.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr21.field.gv43 = (d_tmp & m_tmp) | (reg_ctm_gvr21.field.gv43 & ~m_tmp);
			break;

		case 0x4F18:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr22.field.gv44 = (d_tmp & m_tmp) | (reg_ctm_gvr22.field.gv44 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr22.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr22.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr22.field.gv45 = (d_tmp & m_tmp) | (reg_ctm_gvr22.field.gv45 & ~m_tmp);
			break;

		case 0x4F1C:
			// Lsb: 0, Len: 11, [10:0] CTM GV register [0.3.8]
			d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x000007FF;
			reg_ctm_gvr23.field.gv46 = (d_tmp & m_tmp) | (reg_ctm_gvr23.field.gv46 & ~m_tmp);

			// Lsb: 11, Len: 5, [15:11] 
			d_tmp = (data >> 11); m_tmp = (mask >> 11) & 0x0000001F;
			reg_ctm_gvr23.field.rsvd11 = (d_tmp & m_tmp) | (reg_ctm_gvr23.field.rsvd11 & ~m_tmp);

			// Lsb: 16, Len: 11, [26:16] CTM GV register [0.3.8]
			d_tmp = (data >> 16); m_tmp = (mask >> 16) & 0x000007FF;
			reg_ctm_gvr23.field.gv47 = (d_tmp & m_tmp) | (reg_ctm_gvr23.field.gv47 & ~m_tmp);
			break;

	} // End of switch (addr)

	if (addr >= 0x8000 && addr <= 0xFFFF)
	{
		// Lsb: 0, Len: 30, [29:0] LUT value
		d_tmp = (data >> 0); m_tmp = (mask >> 0) & 0x3FFFFFFF;
		reg_i3dlut[(addr - 0x8000) >> 2].field.lut_val = (d_tmp & m_tmp) | (reg_i3dlut[(addr - 0x8000) >> 2].field.lut_val & ~m_tmp);
	}
}

#endif //REG_FUNCTION_ENABLE

#endif //__ISP_REG_H__
